JP6716045B1 - Component-embedded substrate and method for manufacturing component-embedded substrate - Google Patents

Component-embedded substrate and method for manufacturing component-embedded substrate Download PDF

Info

Publication number
JP6716045B1
JP6716045B1 JP2019569846A JP2019569846A JP6716045B1 JP 6716045 B1 JP6716045 B1 JP 6716045B1 JP 2019569846 A JP2019569846 A JP 2019569846A JP 2019569846 A JP2019569846 A JP 2019569846A JP 6716045 B1 JP6716045 B1 JP 6716045B1
Authority
JP
Japan
Prior art keywords
component
metal piece
electronic component
electrode terminal
embedded substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019569846A
Other languages
Japanese (ja)
Other versions
JPWO2020250405A1 (en
Inventor
松本　徹
徹 松本
正勝 石原
正勝 石原
保明 関
保明 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meiko Co Ltd
Original Assignee
Meiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Co Ltd filed Critical Meiko Co Ltd
Application granted granted Critical
Publication of JP6716045B1 publication Critical patent/JP6716045B1/en
Publication of JPWO2020250405A1 publication Critical patent/JPWO2020250405A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

部品内蔵基板１は、貫通孔１５が形成された第１部分基板１０と、貫通孔１５に固定された金属片１６と、金属片１６と接する第１電極端子２２が第１面２１に設けられ、第１面２１と反対側の第２面２３に第２電極端子２４が設けられた電子部品２０と、電子部品２０を埋設する第２絶縁層４１を含む第２部分基板４０と、を備える。The component-embedded substrate 1 is provided with a first partial substrate 10 having a through hole 15, a metal piece 16 fixed to the through hole 15, and a first electrode terminal 22 in contact with the metal piece 16 on the first surface 21. An electronic component 20 having a second electrode terminal 24 provided on a second surface 23 opposite to the first surface 21, and a second partial substrate 40 including a second insulating layer 41 in which the electronic component 20 is embedded. ..

Description

本発明は、部品内蔵基板、及び部品内蔵基板の製造方法に関する。 The present invention relates to a component-embedded substrate and a method for manufacturing a component-embedded substrate.

発熱部品が実装されるプリント配線基板は、例えば特許文献１及び２の従来技術として開示されているように、基板に放熱機構が備えられるのが一般的である。より具体的には、これらの従来技術は、基板を貫通するように設けられた伝熱部材を挟むように、基板の両面に発熱部品とヒートシンクとをそれぞれ設けて構成されている。これにより、基板の一方の面に実装された発熱部品が発する熱は、伝熱部材を介して基板の他方の面に配置されたヒートシンクに伝えられて放熱されることになる。このとき、発熱部品とヒートシンクとの間で放熱経路を形成する伝熱部材は、例えば銅の塊からなる金属片として形成されることにより、複数のサーマルビアが形成される場合と比較して放熱経路の断面積を確保しやすく、発熱部品の発熱量が比較的大きい場合にも効率的に放熱することができる。 A printed wiring board on which a heat-generating component is mounted is generally provided with a heat dissipation mechanism as disclosed in, for example, the prior arts of Patent Documents 1 and 2. More specifically, these prior arts are configured by respectively providing a heat-generating component and a heat sink on both sides of the substrate so as to sandwich a heat transfer member provided so as to penetrate the substrate. As a result, the heat generated by the heat-generating component mounted on one surface of the substrate is transferred to the heat sink arranged on the other surface of the substrate via the heat transfer member and is radiated. At this time, the heat transfer member that forms the heat dissipation path between the heat generating component and the heat sink is formed as a metal piece made of, for example, a mass of copper, so that heat dissipation can be performed compared to the case where a plurality of thermal vias are formed. It is easy to secure the cross-sectional area of the path, and it is possible to efficiently dissipate heat even when the heat generation amount of the heat generating component is relatively large.

ここで、特許文献１の従来技術に係る電子部品は、基板との接触面とは反対側の面に電極端子を備え、基板表面に形成された導電パターンに対して当該電極端子がボンディングワイヤで接続されている。また、特許文献２の従来技術に係る電子部品は、基板との接触面側に形成された電極端子が、基板表面に形成された導電パターンに対して半田により接続されている。すなわち、基板表面に実装される電子部品は、電極端子がいずれの面に形成されていても、上記のような伝熱部材を介する放熱機構を導入することができる。 Here, the electronic component according to the related art of Patent Document 1 includes an electrode terminal on the surface opposite to the contact surface with the substrate, and the electrode terminal is a bonding wire with respect to the conductive pattern formed on the surface of the substrate. It is connected. In addition, in the electronic component according to the related art of Patent Document 2, the electrode terminal formed on the contact surface side with the substrate is connected to the conductive pattern formed on the substrate surface by soldering. That is, in the electronic component mounted on the surface of the board, the heat dissipation mechanism via the heat transfer member as described above can be introduced regardless of which surface the electrode terminal is formed on.

ところで、上記のような発熱部品のうち、インバータやコンバータなどの電子部品は、近年のスイッチング速度の向上に伴い薄型化が進行している。このため、当該電子部品をプリント配線基板に内蔵することができれば、従来の部品内蔵基板と同様に、実装面積を節約して基板を小型化することができる他、配線長を短縮することにより配線抵抗やリアクタンス成分の影響を軽減して電気性能を向上させることができる。 By the way, among the heat-generating components as described above, electronic components such as inverters and converters are becoming thinner as the switching speed is improved in recent years. Therefore, if the electronic component can be built in the printed wiring board, the mounting area can be saved and the board can be miniaturized as in the case of the conventional component built-in board. It is possible to improve the electric performance by reducing the influence of resistance and reactance components.

特許第３９２２６４２号公報Japanese Patent No. 3922642 特許第５５４６７７８号公報Japanese Patent No. 5546778

しかしながら、従来の部品内蔵基板においては、電子部品の電極端子と基板に形成された導電パターンとが導通ビアにより接続されるのが一般的であり、電極端子が両面に形成された電子部品を基板に内蔵する場合には、電子部品の両面に導通ビアを形成しなければならず、金属片を使用して効率的に放熱する放熱機構を導入することができなかった。また、基板の表面と内蔵部品とを接続する複数のサーマルビアを密集させて形成したとしても、やはり放熱経路の断面積の限界により効率的な放熱が制限されてしまうことになる。 However, in the conventional component-embedded substrate, it is general that the electrode terminals of the electronic component and the conductive patterns formed on the substrate are connected by the conductive vias, and the electronic component having the electrode terminals formed on both sides is printed on the substrate. In the case of embedding in, the conductive vias must be formed on both sides of the electronic component, and it was not possible to introduce a heat dissipation mechanism using a metal piece for efficient heat dissipation. Even if a plurality of thermal vias that connect the surface of the substrate and the built-in components are densely formed, effective heat dissipation is also limited by the limit of the cross-sectional area of the heat dissipation path.

本発明は、このような状況に鑑みてなされたものであり、その目的とするところは、両面に電極端子が形成された電子部品を内蔵する場合であっても、放熱特性を向上させることができる部品内蔵基板、及び部品内蔵基板の製造方法を提供することにある。 The present invention has been made in view of such circumstances, and an object thereof is to improve heat dissipation characteristics even when an electronic component having electrode terminals formed on both surfaces is built in. (EN) Provided are a component-embedded substrate and a method for manufacturing a component-embedded substrate.

＜本発明の第１の態様＞
本発明の第１の態様は、貫通孔が形成された第１部分基板と、前記貫通孔に固定された金属片と、前記金属片と接する第１電極端子が第１面に設けられ、前記第１面と反対側の第２面に第２電極端子が設けられた電子部品と、前記電子部品を埋設する絶縁層を含む第２部分基板と、を備える部品内蔵基板である。<First Aspect of the Present Invention>
According to a first aspect of the present invention, a first partial substrate having a through hole formed therein, a metal piece fixed to the through hole, and a first electrode terminal in contact with the metal piece are provided on a first surface, A component-embedded substrate including an electronic component having a second electrode terminal provided on a second surface opposite to the first surface, and a second partial substrate including an insulating layer in which the electronic component is embedded.

部品内蔵基板は、第１電極端子及び第２電極端子が両面に設けられた電子部品を内蔵している。ここで、電子部品は、第１面に形成された第１電極端子が金属片に接することにより当該金属片を介して回路に実装されると共に、金属片との境界面を部品内蔵基板の内部に有しながら基板表面への放熱経路が確保されることになる。 The component-embedded substrate incorporates an electronic component having a first electrode terminal and a second electrode terminal provided on both surfaces. Here, the electronic component is mounted on the circuit through the metal piece by contacting the first electrode terminal formed on the first surface with the metal piece, and the interface with the metal piece is formed inside the component-embedded substrate. Therefore, the heat radiation path to the surface of the substrate is secured.

このとき、当該放熱経路は、複数のサーマルビアを密集して形成する従来の放熱機構と比較して断面積を大きく設定することができ、効率的な放熱が可能になる。従って、本発明の第１の態様に係る部品内蔵基板によれば、両面に電極端子が形成された電子部品を内蔵する場合であっても、放熱特性を向上させることができる。 At this time, the heat dissipation path can have a larger cross-sectional area than that of a conventional heat dissipation mechanism in which a plurality of thermal vias are densely formed, and efficient heat dissipation becomes possible. Therefore, according to the component-embedded substrate according to the first aspect of the present invention, the heat dissipation characteristic can be improved even when the electronic component having the electrode terminals formed on both surfaces is incorporated.

＜本発明の第２の態様＞
本発明の第２の態様は、上記した本発明の第１の態様において、前記金属片は、前記貫通孔の内側面との互いの応力により前記貫通孔に固定されている、部品内蔵基板である。<Second aspect of the present invention>
A second aspect of the present invention is the component-embedded substrate according to the first aspect of the present invention, in which the metal piece is fixed to the through hole by mutual stress with the inner surface of the through hole. is there.

本発明の第２の態様に係る部品内蔵基板によれば、第１部分基板の貫通孔に対する金属片の固定において、接着剤や半田等の材料を別途設ける必要がないため、当該材料の使用に伴うコスト上昇と導電性及び熱伝導性の低下とを防止することができる。特に、貫通孔に対して金属片を半田で固定するときには、半田の溶融開始温度等を適切に設定しない限り、先の工程及び後の工程において部品内蔵基板の他の部分に使用される半田が例えばリフロー処理の加熱により溶融し、半田による接続部分の導電性を低下させてしまう虞が生じる。これに対し、本発明の第２の態様に係る部品内蔵基板によれば、半田の溶融開始温度等を設定せずとも、貫通孔に金属片を固定することができる。 According to the component-embedded substrate of the second aspect of the present invention, when fixing the metal piece to the through hole of the first partial substrate, it is not necessary to separately provide a material such as an adhesive or solder, and therefore, it is possible to use the material. It is possible to prevent the accompanying increase in cost and the decrease in electrical conductivity and thermal conductivity. In particular, when the metal piece is fixed to the through hole with solder, the solder used for other parts of the component built-in board in the previous step and the subsequent step may be used unless the melting start temperature of the solder is appropriately set. For example, there is a possibility that the resin may be melted by heating in the reflow process and the conductivity of the connection portion due to solder may be reduced. On the other hand, according to the component built-in board according to the second aspect of the present invention, the metal piece can be fixed to the through hole without setting the melting start temperature of the solder.

＜本発明の第３の態様＞
本発明の第３の態様は、上記した本発明の第１又は２の態様において、前記金属片は、前記電子部品における前記第１面の全体が接する形状である、部品内蔵基板である。<Third aspect of the present invention>
A third aspect of the present invention is the component-embedded substrate according to the first or second aspect of the present invention, wherein the metal piece has a shape in which the entire first surface of the electronic component is in contact.

本発明の第３の態様に係る部品内蔵基板によれば、電子部品における第１面の全体が金属片を介した放熱経路として構成することができるため、発熱量が比較的多い電子部品に対しても効率的に放熱することができる。また、本発明の第３の態様に係る部品内蔵基板によれば、薄型化されることにより部品内蔵基板の反りに対して脆弱な電子部品を内蔵する場合であっても、金属片により電子部品が保護される他、部品内蔵基板の反りが抑制されるため導通ビアが剥離する虞を低減することができる。 According to the component-embedded substrate of the third aspect of the present invention, since the entire first surface of the electronic component can be configured as a heat radiation path via the metal piece, the electronic component that generates a relatively large amount of heat can be used. However, heat can be efficiently dissipated. Further, according to the component-embedded substrate according to the third aspect of the present invention, even when an electronic component that is vulnerable to warpage of the component-embedded substrate due to being thinned is embedded, the electronic component is formed by the metal piece. Is protected, and the warp of the component-embedded substrate is suppressed, so that the possibility that the conductive via is peeled off can be reduced.

＜本発明の第４の態様＞
本発明の第４の態様は、上記した本発明の第１乃至３のいずれかの態様において、前記電子部品の前記第１電極端子と前記金属片との接触面に導電性ペーストが塗布されている、部品内蔵基板である。<Fourth aspect of the present invention>
According to a fourth aspect of the present invention, in any one of the first to third aspects of the present invention described above, a conductive paste is applied to a contact surface between the first electrode terminal and the metal piece of the electronic component. It is a component built-in board.

本発明の第４の態様に係る部品内蔵基板によれば、導電性ペーストにより第１電極端子と金属片との電気的及び熱的な接続状態を良好に保つことができる。 According to the component-embedded substrate of the fourth aspect of the present invention, it is possible to maintain a good electrical and thermal connection between the first electrode terminal and the metal piece with the conductive paste.

＜本発明の第５の態様＞
本発明の第５の態様は、上記した本発明の第１乃至４のいずれかの態様において、前記絶縁層を貫通して前記電子部品の前記第２電極端子に接続される導通ビアを含み、前記導通ビアに接するように表面実装部品が配設されている、部品内蔵基板である。<Fifth aspect of the present invention>
A fifth aspect of the present invention is the method according to any one of the first to fourth aspects of the present invention, which includes a conductive via penetrating the insulating layer and connected to the second electrode terminal of the electronic component, A component-embedded substrate in which a surface-mounted component is disposed so as to contact the conductive via.

本発明の第５の態様に係る部品内蔵基板によれば、電子部品の第２電極端子と表面実装部品とが導通ビアを介して直接接続されている。このため、両者の間の配線長が導通ビアの高さだけに抑えられるため、配線抵抗やリアクタンス成分の影響を軽減して電気特性を向上させることができる。 According to the component-embedded substrate of the fifth aspect of the present invention, the second electrode terminal of the electronic component and the surface-mounted component are directly connected via the conductive via. Therefore, the wiring length between the two can be suppressed only to the height of the conductive via, so that the influence of the wiring resistance and the reactance component can be reduced and the electrical characteristics can be improved.

＜本発明の第６の態様＞
本発明の第６の態様は、第１面に第１電極端子が設けられ、前記第１面と反対側の第２面に第２電極端子が設けられた電子部品を内蔵する部品内蔵基板の製造方法であって、第１部分基板に貫通孔を形成する貫通孔形成工程と、金属片を前記貫通孔に固定する金属片固定工程と、前記金属片と前記第１電極端子とが接するように前記電子部品を設置する部品設置工程と、前記電子部品を絶縁層で埋設する第２部分基板を形成する部品埋設工程と、を含む、部品内蔵基板の製造方法である。<Sixth aspect of the present invention>
According to a sixth aspect of the present invention, there is provided a component-embedded substrate having a first electrode terminal provided on a first surface and a second electrode terminal provided on a second surface opposite to the first surface. A method of manufacturing, wherein a through hole forming step of forming a through hole in a first partial substrate, a metal piece fixing step of fixing a metal piece to the through hole, and the metal piece and the first electrode terminal are in contact with each other. And a component embedding step of forming a second partial substrate in which the electronic component is embedded with an insulating layer, and a component embedding step of forming the second partial substrate in which the electronic component is embedded in the insulating layer.

本発明の第６の態様に係る部品内蔵基板の製造方法によれば、第１部分基板の貫通孔に金属片を固定し、当該金属片と第１電極端子とが接するように電子部品を設置した上で、第２部分基板の絶縁層で電子部品を埋設している。そして、部品内蔵基板に内蔵された電子部品は、第１面に形成された第１電極端子が金属片に接することにより当該金属片を介して回路に実装されると共に、金属片との境界面を部品内蔵基板の内部に有しながら基板表面への放熱経路が確保されることになる。 According to the method of manufacturing a component-embedded substrate according to the sixth aspect of the present invention, a metal piece is fixed to the through hole of the first partial substrate, and the electronic component is installed so that the metal piece and the first electrode terminal are in contact with each other. Then, the electronic component is embedded in the insulating layer of the second partial substrate. The electronic component embedded in the component-embedded substrate is mounted on the circuit through the metal piece by contacting the first electrode terminal formed on the first surface with the metal piece, and the interface with the metal piece is formed. The heat radiation path to the surface of the board is ensured while having the inside of the component built-in board.

このとき、当該放熱経路は、複数のサーマルビアを密集して形成する従来の放熱機構と比較して断面積を大きく設定することができ、効率的な放熱が可能になる。従って、本発明の第６の態様によれば、両面に電極端子が形成された電子部品を内蔵する場合であっても、放熱特性を向上させることができる部品内蔵基板を製造することができる。 At this time, the heat dissipation path can have a larger cross-sectional area than that of a conventional heat dissipation mechanism in which a plurality of thermal vias are densely formed, and efficient heat dissipation becomes possible. Therefore, according to the sixth aspect of the present invention, it is possible to manufacture a component-embedded substrate that can improve heat dissipation characteristics even when an electronic component having electrode terminals formed on both surfaces is incorporated.

＜本発明の第７の態様＞
本発明の第７の態様は、上記した本発明の第６の態様において、前記金属片固定工程においては、前記貫通孔の内側面と前記金属片との互いの応力により前記金属片を前記貫通孔に固定する、部品内蔵基板の製造方法である。<Seventh Aspect of the Present Invention>
A seventh aspect of the present invention, in the sixth aspect of the present invention described above, in the metal piece fixing step, the metal piece is pierced through the metal piece due to mutual stress between the inner surface of the through hole and the metal piece. This is a method of manufacturing a component-embedded substrate that is fixed in a hole.

本発明の第７の態様に係る部品内蔵基板の製造方法によれば、第１部分基板の貫通孔に対する金属片の固定において、接着剤や半田等の材料を別途設ける必要がないため、当該材料の使用に伴うコスト上昇と導電性及び熱伝導性の低下とを防止することができる。特に、貫通孔に対して金属片を半田で固定するときには、半田の溶融開始温度等を適切に設定しない限り、先の工程及び後の工程において部品内蔵基板の他の部分に使用される半田が例えばリフロー処理の加熱により溶融し、半田による接続部分の導電性を低下させてしまう虞が生じる。これに対し、本発明の第７の態様によれば、半田の溶融開始温度等を設定せずとも、貫通孔に金属片を固定することができる部品内蔵基板を製造することができる。 According to the method of manufacturing a component-embedded substrate according to the seventh aspect of the present invention, when fixing the metal piece to the through hole of the first partial substrate, it is not necessary to separately provide a material such as an adhesive or solder, and thus the material It is possible to prevent an increase in cost and a decrease in electrical conductivity and thermal conductivity due to the use of In particular, when the metal piece is fixed to the through hole with solder, the solder used for other parts of the component built-in board in the previous step and the subsequent step may be used unless the melting start temperature of the solder is appropriately set. For example, there is a possibility that the resin may be melted by heating in the reflow process and the conductivity of the connection portion due to solder may be reduced. On the other hand, according to the seventh aspect of the present invention, it is possible to manufacture a component-embedded substrate in which a metal piece can be fixed to the through hole without setting the melting start temperature of solder or the like.

＜本発明の第８の態様＞
本発明の第８の態様は、上記した本発明の第６又は７の態様において、前記金属片固定工程においては、前記電子部品における前記第１面の全体が前記金属片に接するように前記金属片の形状が設定される、部品内蔵基板の製造方法である。<Eighth aspect of the present invention>
According to an eighth aspect of the present invention, in the sixth or seventh aspect of the present invention described above, in the metal piece fixing step, the metal so that the entire first surface of the electronic component is in contact with the metal piece. It is a method of manufacturing a component-embedded substrate in which the shape of a piece is set.

本発明の第８の態様によれば、電子部品における第１面の全体が金属片を介した放熱経路として構成することができるため、発熱量が比較的多い電子部品に対しても効率的に放熱することができる部品内蔵基板を製造することができる。また、本発明の第８の態様によれば、薄型化されることにより部品内蔵基板の反りに対して脆弱な電子部品を内蔵する場合であっても、金属片により電子部品が保護される他、部品内蔵基板の反りが抑制されるため導通ビアが抜ける虞を低減することができる部品内蔵基板を製造することができる。 According to the eighth aspect of the present invention, since the entire first surface of the electronic component can be configured as a heat radiation path via the metal piece, the electronic component that efficiently generates a relatively large amount of heat can be efficiently formed. A component built-in substrate capable of radiating heat can be manufactured. Further, according to the eighth aspect of the present invention, even when an electronic component that is vulnerable to warpage of the component-embedded substrate due to being thinned is embedded, the electronic component is protected by the metal piece. Since the warpage of the component-embedded substrate is suppressed, it is possible to manufacture the component-embedded substrate that can reduce the risk of the conductive vias coming off.

＜本発明の第９の態様＞
本発明の第９の態様は、上記した本発明の第６乃至８のいずれかの態様において、前記部品設置工程においては、前記電子部品の前記第１電極端子と前記金属片との接触面に導電性ペーストを塗布する、部品内蔵基板の製造方法である。<Ninth Aspect of the Present Invention>
In a ninth aspect of the present invention according to any one of the sixth to eighth aspects of the present invention, in the component installing step, a contact surface between the first electrode terminal of the electronic component and the metal piece is provided. This is a method of manufacturing a component-embedded substrate, in which a conductive paste is applied.

本発明の第９の態様によれば、導電性ペーストにより第１電極端子と金属片との電気的及び熱的な接続状態を良好に保つことができる部品内蔵基板を製造することができる。 According to the ninth aspect of the present invention, it is possible to manufacture a component-embedded substrate that can maintain a good electrical and thermal connection between the first electrode terminal and the metal piece with the conductive paste.

＜本発明の第１０の態様＞
本発明の第１０の態様は、上記した本発明の第６乃至９のいずれかの態様において、前記絶縁層を貫通して前記電子部品の前記第２電極端子に接続される導通ビアを形成し、前記導通ビアに接するように表面実装部品を配設する表面実装工程を含む、部品内蔵基板の製造方法である。<Tenth aspect of the present invention>
A tenth aspect of the present invention is the method according to any one of the sixth to ninth aspects of the present invention, wherein a conductive via is formed that penetrates the insulating layer and is connected to the second electrode terminal of the electronic component. A method of manufacturing a component-embedded substrate, which includes a surface-mounting step of disposing a surface-mounting component in contact with the conductive via.

本発明の第１０の態様によれば、電子部品の第２電極端子と表面実装部品とが導通ビアを介して直接接続されているため、両者の間の配線長が導通ビアの高さだけに抑えられ、配線抵抗やリアクタンス成分の影響を軽減して電気特性を向上させることができる部品内蔵基板を製造することができる。 According to the tenth aspect of the present invention, since the second electrode terminal of the electronic component and the surface mount component are directly connected to each other via the conductive via, the wiring length between them is limited to the height of the conductive via. It is possible to manufacture a component-embedded substrate that can be suppressed and can reduce the influence of wiring resistance and reactance components and improve electrical characteristics.

本発明によれば、両面に電極端子が形成された電子部品を内蔵する場合であっても、放熱特性を向上させることができる部品内蔵基板、及び部品内蔵基板の製造方法を提供することができる。 According to the present invention, it is possible to provide a component-embedded substrate and a method of manufacturing a component-embedded substrate that can improve heat dissipation characteristics even when an electronic component having electrode terminals formed on both sides is incorporated. ..

本発明の第１実施形態に係る貫通孔形成工程を表す断面図である。FIG. 4 is a cross-sectional view showing a through hole forming step according to the first embodiment of the present invention. 本発明の第１実施形態に係る金属片固定工程を表す断面図である。It is sectional drawing showing the metal piece fixing process which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る部品設置工程を表す断面図である。It is sectional drawing showing the components installation process which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る部品埋設工程を表す断面図である。It is sectional drawing showing the component burying process which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係るビア形成工程を表す断面図である。FIG. 6 is a cross-sectional view showing a via forming step according to the first embodiment of the present invention. 本発明の第１実施形態に係るパターニング工程を表す断面図である。FIG. 6 is a cross-sectional view illustrating a patterning process according to the first embodiment of the present invention. 本発明の第１実施形態に係る表面実装工程を表す断面図である。It is sectional drawing showing the surface mounting process which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る部品内蔵基板の断面図である。It is sectional drawing of the component built-in board which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る部品内蔵基板の断面図である。It is sectional drawing of the component built-in board which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係る部品設置工程を表す断面図である。It is sectional drawing showing the components installation process which concerns on 4th Embodiment of this invention. 本発明の第４実施形態に係る部品内蔵基板の断面図である。It is sectional drawing of the component built-in board which concerns on 4th Embodiment of this invention.

以下、図面を参照し、本発明の実施の形態について詳細に説明する。尚、本発明は以下に説明する内容に限定されるものではなく、その要旨を変更しない範囲において任意に変更して実施することが可能である。また、実施の形態の説明に用いる図面は、いずれも構成部材を模式的に示すものであって、理解を深めるべく部分的な強調、拡大、縮小、または省略などを行っており、構成部材の縮尺や形状等を正確に表すものとはなっていない場合がある。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the present invention is not limited to the contents described below, and can be implemented by being arbitrarily modified within the scope of the invention. In addition, the drawings used for the description of the embodiments are all schematic illustrations of constituent members, and are partially emphasized, enlarged, reduced, or omitted for better understanding. It may not be an accurate representation of scale or shape.

＜第１実施形態＞
以下において、図１乃至７を参照しつつ、本発明の第１実施形態に係る部品内蔵基板１の製造方法及び製造される部品内蔵基板１について詳細に説明する。完成形としての部品内蔵基板１は、図７において後述するように、両面に電極が形成された発熱部品としての電子部品２０を内蔵しつつ、電子部品２０を効率的に放熱させる放熱機構が設けられると共に、当該電極と導通する表面実装部品６０〜６２が実装されている。部品内蔵基板１は、例えば、携帯電話、ノートパソコン、デジタルカメラ等の電子機器や、各種の車載機器における制御装置など、様々な用途に利用することができる。<First Embodiment>
Hereinafter, the method of manufacturing the component-embedded substrate 1 and the component-embedded substrate 1 according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7. As will be described later with reference to FIG. 7, the component-embedded substrate 1 as a completed type is provided with a heat dissipation mechanism for efficiently dissipating the electronic component 20 while incorporating the electronic component 20 as a heat-generating component in which electrodes are formed on both surfaces. In addition, the surface mount components 60 to 62 that are electrically connected to the electrodes are mounted. The component-embedded substrate 1 can be used for various applications such as electronic devices such as mobile phones, notebook computers, and digital cameras, and control devices for various in-vehicle devices.

本発明の第１実施形態に係る部品内蔵基板１の製造方法は、貫通孔形成工程、金属片固定工程、部品設置工程、部品埋設工程、ビア形成工程、パターニング工程、及び表面実装工程を含む。 The method of manufacturing the component-embedded substrate 1 according to the first embodiment of the present invention includes a through hole forming step, a metal piece fixing step, a component installing step, a component burying step, a via forming step, a patterning step, and a surface mounting step.

図１は、本発明の第１実施形態に係る貫通孔形成工程を表す断面図である。まず、貫通孔形成工程では、部品内蔵基板１を製造するためのベースとなる第１部分基板１０を準備し、第１部分基板１０に貫通孔１５を形成する。ここで、本実施形態における第１部分基板１０は、第１導電層１１、第１内層パターン１２、第２内層パターン１３、及び第１絶縁層１４を含む。 FIG. 1 is a sectional view showing a through-hole forming step according to the first embodiment of the present invention. First, in the through hole forming step, the first partial substrate 10 serving as a base for manufacturing the component-embedded substrate 1 is prepared, and the through holes 15 are formed in the first partial substrate 10. Here, the first partial substrate 10 according to the present embodiment includes the first conductive layer 11, the first inner layer pattern 12, the second inner layer pattern 13, and the first insulating layer 14.

より具体的には、第１部分基板１０は、一方の面に第１導電層１１が設けられると共に、他方の面に第１内層パターン１２が設けられ、これらの間に複数の第２内層パターン１３が形成されている。第１導電層１１、第１内層パターン１２、及び第２内層パターン１３は、パターニング処理が施されることにより回路パターンとなる金属層であり、第１絶縁層１４により互いに絶縁されている。ただし、それぞれの金属層は、全体として回路が構成されるよう、図示しないビア等で部分的に接続されている。また、第１絶縁層１４は、絶縁性を有する樹脂材料からなり、剛性を有するコア基材を含んでもよく、製造工程における加熱時に流動性を有するプリプレグを含んでもよい。 More specifically, the first partial substrate 10 is provided with the first conductive layer 11 on one surface and the first inner layer pattern 12 on the other surface, and a plurality of second inner layer patterns are provided between them. 13 is formed. The first conductive layer 11, the first inner layer pattern 12, and the second inner layer pattern 13 are metal layers that become a circuit pattern by performing a patterning process, and are insulated from each other by the first insulating layer 14. However, the respective metal layers are partially connected by vias or the like not shown so that the circuit is configured as a whole. The first insulating layer 14 may be made of a resin material having an insulating property and may include a rigid core base material, or may include a prepreg having fluidity during heating in the manufacturing process.

そして、第１部分基板１０は、貫通孔形成工程において、後の工程で設置される電子部品２０に対応する位置、大きさ、形状の貫通孔１５が形成される。本実施形態においては、円柱形状を有する貫通孔１５が形成されるものとして説明する。電子部品２０と貫通孔１５との関係については詳細を後述する。 Then, in the through hole forming step, the first partial substrate 10 is provided with the through hole 15 having a position, size, and shape corresponding to the electronic component 20 installed in a later step. In the present embodiment, description will be made assuming that the through hole 15 having a cylindrical shape is formed. The relationship between the electronic component 20 and the through hole 15 will be described in detail later.

尚、第１内層パターン１２及び第２内層パターン１３は、本発明において必須の構成部材ではない。また、第２内層パターン１３の数についても部品内蔵基板１の仕様に応じて適宜変更することができる。そして、第１内層パターン１２及び第２内層パターン１３が形成される場合には、第１部分基板１０が準備される段階でパターニング処理が施されている。更に、本実施形態においては、第１部分基板１０の貫通孔１５は、その内側面に銅によるめっき処理が施されているが、当該めっき処理についても必須ではない。 The first inner layer pattern 12 and the second inner layer pattern 13 are not essential constituent members in the present invention. Also, the number of the second inner layer patterns 13 can be appropriately changed according to the specifications of the component-embedded substrate 1. When the first inner layer pattern 12 and the second inner layer pattern 13 are formed, the patterning process is performed when the first partial substrate 10 is prepared. Further, in the present embodiment, the through hole 15 of the first partial substrate 10 is plated on its inner surface with copper, but the plating process is not essential.

図２は、本発明の第１実施形態に係る金属片固定工程を表す断面図である。金属片１６は、導電性及び熱伝導性を有する金属からなり、例えば銅の塊である。すなわち、金属片１６は、所謂銅インレイ、銅コイン、又は銅ピンと呼ばれる伝熱部材である。 FIG. 2 is a cross-sectional view showing a metal piece fixing step according to the first embodiment of the present invention. The metal piece 16 is made of a metal having electrical conductivity and thermal conductivity, and is, for example, a lump of copper. That is, the metal piece 16 is a heat transfer member called a so-called copper inlay, a copper coin, or a copper pin.

金属片固定工程においては、第１部分基板１０に形成された上記の貫通孔１５を埋めるように金属片１６が固定される。 In the metal piece fixing step, the metal piece 16 is fixed so as to fill the through hole 15 formed in the first partial substrate 10.

ここで、金属片１６は、第１部分基板１０の貫通孔１５に対して、例えば圧入法やカシメ法により固定することができる。より具体的には、圧入法は、貫通孔１５の内径よりも僅かに大きく第１部分基板１０の厚みと同じ高さを有する金属片１６を、例えばプレス機で貫通孔１５に押し込むことにより、貫通孔１５を金属片１６で埋めるように固定する方法である。また、カシメ法は、貫通孔１５の内径よりも僅かに小さく第１部分基板１０の厚みよりも高さが有る金属片１６を貫通孔１５に配置し、例えばプレス機で金属片１６を押圧して変形させることにより、貫通孔１５を金属片１６で埋めるように固定する方法である。 Here, the metal piece 16 can be fixed to the through hole 15 of the first partial substrate 10 by, for example, a press fitting method or a caulking method. More specifically, in the press-fitting method, a metal piece 16 that is slightly larger than the inner diameter of the through hole 15 and has the same height as the thickness of the first partial substrate 10 is pushed into the through hole 15 by, for example, a pressing machine, This is a method of fixing the through hole 15 so as to fill it with the metal piece 16. In the crimping method, a metal piece 16 slightly smaller than the inner diameter of the through hole 15 and higher than the thickness of the first partial substrate 10 is arranged in the through hole 15, and the metal piece 16 is pressed by, for example, a pressing machine. It is a method of fixing the through hole 15 so that the through hole 15 is filled with the metal piece 16.

そして、本実施形態における金属片固定工程においては、圧入法やカシメ法のいずれの方法であっても、金属片１６を貫通孔１５の内側面との互いの応力により貫通孔１５に固定するため、接着剤や半田等の材料を別途設ける必要がない。 In the metal piece fixing step of the present embodiment, the metal piece 16 is fixed to the through hole 15 by mutual stress between the metal piece 16 and the inner surface of the through hole 15 regardless of whether the method is press fitting or caulking. It is not necessary to separately provide a material such as an adhesive or solder.

続いて、部品内蔵基板１に内蔵される電子部品２０を上記の第１部分基板１０に設置する部品設置工程について説明する。図３は、本発明の第１実施形態に係る部品設置工程を表す断面図である。 Next, a component installation process of installing the electronic component 20 built in the component built-in board 1 on the first partial board 10 will be described. FIG. 3 is a cross-sectional view showing a component installation process according to the first embodiment of the present invention.

ここで、本実施形態に係る電子部品２０は、部品内蔵基板１の厚みよりも薄い板状であり、例えばインバータやコンバータ等に使用される所謂パワーＭＯＳＦＥＴである。パワーＭＯＳＦＥＴは、通常のＭＯＳＦＥＴと比較して、スイッチング速度や変換効率が良好である反面、大電流を扱う部品であるため動作に伴う発熱への対処が課題となる。 Here, the electronic component 20 according to the present embodiment has a plate shape thinner than the thickness of the component-embedded substrate 1, and is a so-called power MOSFET used in, for example, an inverter or a converter. The power MOSFET has better switching speed and conversion efficiency than a normal MOSFET, but on the other hand, since it is a component handling a large current, it is necessary to deal with heat generation due to operation.

また、本実施形態に係る電子部品２０は、第１面２１において第１電極端子２２が設けられ、第１面２１と反対側の第２面２３において２つの第２電極端子２４が設けられている。より詳しくは、第１電極端子２２は、パワーＭＯＳＦＥＴのドレイン端子として電子部品２０の第１面２１の全体を構成している。また、２つの第２電極端子２４は、それぞれパワーＭＯＳＦＥＴのソース端子及びゲート端子として電子部品２０の第２面２３の一部を構成している。尚、電子部品２０の各電極端子は、電子部品２０の種類に応じて数量や配置、形状が異なってもよい。 Further, the electronic component 20 according to the present embodiment is provided with the first electrode terminals 22 on the first surface 21 and two second electrode terminals 24 on the second surface 23 opposite to the first surface 21. There is. More specifically, the first electrode terminal 22 constitutes the entire first surface 21 of the electronic component 20 as a drain terminal of the power MOSFET. Further, the two second electrode terminals 24 respectively configure a part of the second surface 23 of the electronic component 20 as a source terminal and a gate terminal of the power MOSFET. The electrode terminals of the electronic component 20 may be different in quantity, arrangement, and shape depending on the type of the electronic component 20.

そして、部品設置工程においては、電子部品２０は、第１部分基板１０の他方の面、すなわち第１内層パターン１２が形成された面において、金属片１６と第１電極端子２２とが接するように金属片１６に設置される。 Then, in the component installation step, the electronic component 20 is configured such that the metal piece 16 and the first electrode terminal 22 are in contact with each other on the other surface of the first partial substrate 10, that is, the surface on which the first inner layer pattern 12 is formed. It is installed on the metal piece 16.

また、電子部品２０の第１電極端子２２と金属片１６との接触面に、例えば導電性接着剤や半田等のペースト状材料からなる導電性ペースト３０を塗布するのが好適である。これにより、電子部品２０と金属片１６との間に部分的に僅かな隙間が存在する場合であっても、導電性ペースト３０で当該隙間を埋めることができ、第１電極端子２２と金属片１６との電気的な接続状態を良好に保つことができるほか、電子部品２０が発する熱を金属片１６へ効率的に伝えることができる。 Further, it is preferable to apply a conductive paste 30 made of a paste-like material such as a conductive adhesive or solder to the contact surface between the first electrode terminal 22 of the electronic component 20 and the metal piece 16. As a result, even if there is a slight gap between the electronic component 20 and the metal piece 16, the gap can be filled with the conductive paste 30, and the first electrode terminal 22 and the metal piece 16 can be filled. In addition to being able to maintain a good electrical connection with 16, it is possible to efficiently transfer the heat generated by the electronic component 20 to the metal piece 16.

このとき、導電性ペースト３０は、電子部品２０と金属片１６とを乖離させる１つの層を形成するのではなく、あくまでも電子部品２０と金属片１６との間に局所的に生じ得る僅かな隙間を埋めるものである。このため、導電性ペースト３０は、電子部品２０と金属片１６との間において最大でも数１０μｍ以下の幅に抑えられる。このため、導電性ペースト３０が例えば銅（熱伝導率：約４００Ｗ／ｍ・Ｋ）よりも熱伝導率が低い半田（主成分であるＳｎの熱伝導率：約５０Ｗ／ｍ・Ｋ）からなる場合であっても、電子部品２０から金属片１６への熱伝導が抑制される影響を最小限に留めることができる。 At this time, the conductive paste 30 does not form one layer that separates the electronic component 20 and the metal piece 16 from each other, but is a slight gap that may locally occur between the electronic component 20 and the metal piece 16. To fill in. Therefore, the conductive paste 30 is suppressed to a width of several tens of μm or less between the electronic component 20 and the metal piece 16. Therefore, the conductive paste 30 is made of, for example, a solder (thermal conductivity of Sn as a main component: about 50 W/m·K) whose thermal conductivity is lower than that of copper (thermal conductivity: about 400 W/m·K). Even in such a case, it is possible to minimize the effect of suppressing the heat conduction from the electronic component 20 to the metal piece 16.

また、金属片１６は、電子部品２０の放熱経路を構成することから、当該放熱経路の断面積が大きいことが好ましい。本実施形態における金属片１６は、電子部品２０における第１面２１の全体が接するように、その大きさを含めた形状が設定されている。より具体的には、円柱形状を有する本実施形態の金属片１６は、第１部分基板１０の貫通孔１５と共に、電子部品２０よりも水平方向の寸法が大きくなるよう形成されている。つまり、貫通孔１５及び金属片１６は、部品内蔵基板１を平面視した場合に、金属片１６の輪郭が電子部品２０の輪郭を囲むように、その位置、大きさ、形状が設定されている。 Further, since the metal piece 16 constitutes the heat dissipation path of the electronic component 20, it is preferable that the heat dissipation path has a large cross-sectional area. The metal piece 16 in the present embodiment is set to have a shape including its size so that the entire first surface 21 of the electronic component 20 contacts. More specifically, the metal piece 16 of the present embodiment having a cylindrical shape is formed so that the horizontal dimension thereof is larger than that of the electronic component 20 together with the through hole 15 of the first partial substrate 10. That is, the position, size, and shape of the through hole 15 and the metal piece 16 are set so that the contour of the metal piece 16 surrounds the contour of the electronic component 20 when the component-embedded substrate 1 is viewed in a plan view. ..

電子部品２０が第１部分基板１０に設置されると、次に、電子部品２０を埋設するように第２部分基板４０を形成する部品埋設工程が行われる。図４は、本発明の第１実施形態に係る部品埋設工程を表す断面図である。 When the electronic component 20 is installed on the first partial substrate 10, a component embedding step of forming the second partial substrate 40 so as to embed the electronic component 20 is then performed. FIG. 4 is a cross-sectional view showing a component embedding step according to the first embodiment of the present invention.

より具体的には、部品埋設工程においては、電子部品２０を第２絶縁層４１で埋設しつつ第２絶縁層４１の表面に第２導電層４２を設けて第２部分基板４０を形成する。このとき、第２絶縁層４１は、熱可塑性樹脂又は熱硬化性樹脂を用いた積層成型で構成することができる。また、第２絶縁層４１は、補強材としてのガラスクロスを含むプリプレグであってもよく、又はガラスクロスを含まない樹脂シートであってもよく、更には電子部品２０を避ける位置に図示しない回路パターンを別途含んでもよい。 More specifically, in the component embedding step, the second electrically conductive layer 42 is provided on the surface of the second insulating layer 41 while the electronic component 20 is embedded in the second insulating layer 41 to form the second partial substrate 40. At this time, the second insulating layer 41 can be formed by lamination molding using a thermoplastic resin or a thermosetting resin. Further, the second insulating layer 41 may be a prepreg containing a glass cloth as a reinforcing material, or may be a resin sheet not containing a glass cloth, and a circuit (not shown) at a position avoiding the electronic component 20. A pattern may be included separately.

第２絶縁層４１が形成されると、電子部品２０の第２電極端子２４に導通ビア５０を形成するビア形成工程が行われる。図５は、本発明の第１実施形態に係るビア形成工程を表す断面図である。 When the second insulating layer 41 is formed, a via forming step of forming the conductive via 50 in the second electrode terminal 24 of the electronic component 20 is performed. FIG. 5 is a cross-sectional view showing a via formation process according to the first embodiment of the present invention.

ビア形成工程においては、第２部分基板４０の第２導電層４２から電子部品２０の第２電極端子２４に向けて、両者を導通する導通ビア５０が形成される。例えば、第２電極端子２４の直上における第２導電層４２の位置から第２電極端子２４へレーザ加工により穴を開け、当該穴に銅めっきを充填することにより、第２導電層４２と第２電極端子２４とを導通させる導通ビア５０を形成することができる。 In the via forming step, a conductive via 50 is formed from the second conductive layer 42 of the second partial substrate 40 toward the second electrode terminal 24 of the electronic component 20 so as to conduct them. For example, a hole is formed by laser processing from the position of the second conductive layer 42 immediately above the second electrode terminal 24 to the second electrode terminal 24, and the hole is filled with copper plating. It is possible to form the conductive via 50 that is electrically connected to the electrode terminal 24.

導通ビア５０が形成されると、第１部分基板１０の第１導電層１１、及び第２部分基板４０の第２導電層４２をパターニングするパターニング工程が行われる。図６は、本発明の第１実施形態に係るパターニング工程を表す断面図である。 When the conductive via 50 is formed, a patterning process of patterning the first conductive layer 11 of the first partial substrate 10 and the second conductive layer 42 of the second partial substrate 40 is performed. FIG. 6 is a cross-sectional view showing a patterning process according to the first embodiment of the present invention.

パターニング工程においては、部品内蔵基板１の両面における外層回路を形成するため、第１導電層１１及び第２導電層４２において回路が形成されない部分の金属層がエッチング処理により取り除かれる。ここで、パターニング後の第１導電層１１及び第２導電層４２の絶縁すべき部分においては、ソルダーレジストにより被覆されてもよい。 In the patterning step, since the outer layer circuits are formed on both surfaces of the component-embedded substrate 1, the metal layers in the portions where the circuits are not formed in the first conductive layer 11 and the second conductive layer 42 are removed by the etching process. Here, the portions to be insulated of the first conductive layer 11 and the second conductive layer 42 after patterning may be covered with a solder resist.

そして、パターニング工程を経た第１導電層１１及び第２導電層４２に対して、表面実装部品６０〜６２及びヒートシンク７０を実装する表面実装工程が行われる。図７は、本発明の第１実施形態に係る表面実装工程を表す断面図である。 Then, the surface mounting process of mounting the surface mounting components 60 to 62 and the heat sink 70 is performed on the first conductive layer 11 and the second conductive layer 42 that have undergone the patterning process. FIG. 7 is a cross-sectional view showing a surface mounting process according to the first embodiment of the present invention.

表面実装工程においては、部品内蔵基板１の外層回路に設けられる複数の部品が第１導電層１１及び第２導電層４２のそれぞれに実装される。本実施形態においては、電子部品２０の第１電極端子２２、及び２つの第２電極端子２４がそれぞれ導通される部品を表面実装部品６０〜６２として示している。 In the surface mounting step, a plurality of components provided in the outer layer circuit of the component-embedded substrate 1 are mounted on each of the first conductive layer 11 and the second conductive layer 42. In the present embodiment, the components to which the first electrode terminal 22 and the two second electrode terminals 24 of the electronic component 20 are respectively conducted are shown as surface mount components 60 to 62.

ここで、表面実装部品６０〜６２は、その種類に応じて様々な形状を取り得るが、本実施形態においては、いずれも部品本体の両端部を電極が覆う形状を有するものとして例示している。そして、図７に示す部品内蔵基板１においては、表面実装部品６０及び６１は、それぞれの電極を導通ビア５０に接するように配設され、例えば半田を用いた公知のリフロー工程により実装される。さらに、図７に示す部品内蔵基板１においては、表面実装部品６２は、金属片１６と導通する第１導電層１１の回路上に、同じく半田を用いた公知のリフロー工程により実装される。 Here, the surface mount components 60 to 62 can have various shapes depending on their types, but in the present embodiment, all of them are illustrated as having a shape in which both ends of the component body are covered with electrodes. .. Then, in the component built-in board 1 shown in FIG. 7, the surface mount components 60 and 61 are arranged so that their electrodes are in contact with the conductive vias 50, and are mounted by a known reflow process using solder, for example. Further, in the component built-in board 1 shown in FIG. 7, the surface mount component 62 is mounted on the circuit of the first conductive layer 11 that is electrically connected to the metal piece 16 by a known reflow process using the same solder.

また、部品内蔵基板１の第１導電層１１が形成された面においては、金属片１６を覆うようにヒートシンク７０が設けられる。ヒートシンク７０は、第１導電層１１における金属片１６の表面を含む位置において熱伝導性を有する接着剤により取り付けることができる。このとき、金属片１６とヒートシンク７０と間を絶縁する必要がある場合には、絶縁性を有する接着剤が採用される。そして、上記の一連の製造工程により、図７に示す部品内蔵基板１が完成する。 A heat sink 70 is provided so as to cover the metal piece 16 on the surface of the component-embedded substrate 1 on which the first conductive layer 11 is formed. The heat sink 70 can be attached by an adhesive having thermal conductivity at a position including the surface of the metal piece 16 in the first conductive layer 11. At this time, when it is necessary to insulate between the metal piece 16 and the heat sink 70, an insulating adhesive is used. Then, the component-embedded substrate 1 shown in FIG. 7 is completed by the series of manufacturing steps described above.

以上のように、本発明に係る部品内蔵基板１は、内蔵される電子部品２０の両面にそれぞれ設けられた第１電極端子２２及び第２電極端子２４のそれぞれが、部品内蔵基板１の外層パターンとしての第１導電層１１及び第２導電層４２に対して導通されることで導電路が確保されることになる。このとき、電子部品２０は、両面のそれぞれに導電路が形成されているにも拘らず、第１面２１から金属片１６を介して第１導電層１１に至る放熱経路も併せて形成されていることになるため、金属片１６の断面積に応じた効率的な放熱が可能になる。従って、本発明に係る部品内蔵基板１によれば、両面に電極端子が形成された電子部品２０を内蔵する場合であっても、放熱特性を向上させることができる。 As described above, in the component-embedded substrate 1 according to the present invention, each of the first electrode terminals 22 and the second electrode terminals 24 provided on both surfaces of the embedded electronic component 20 is the outer layer pattern of the component-embedded substrate 1. A conductive path is secured by being electrically connected to the first conductive layer 11 and the second conductive layer 42. At this time, the electronic component 20 has a heat dissipation path formed from the first surface 21 to the first conductive layer 11 via the metal piece 16 even though the conductive paths are formed on both surfaces. Therefore, efficient heat dissipation according to the cross-sectional area of the metal piece 16 becomes possible. Therefore, according to the component-embedded substrate 1 of the present invention, the heat dissipation characteristics can be improved even when the electronic component 20 having the electrode terminals formed on both surfaces is incorporated.

ここで、金属片固定工程において、仮に第１部分基板１０の貫通孔１５に対して金属片１６を半田で固定するときには、半田の溶融開始温度等を適切に設定しない限り、先の工程及び後の工程において部品内蔵基板１の他の部分に使用される半田が例えばリフロー処理の加熱により溶融し、半田による接続部分の導電性を低下させてしまう虞が生じる。これに対し、本発明に係る部品内蔵基板１によれば、例えばプレス機により金属片と貫通孔とが互いの応力により固定されている。このため、部品内蔵基板１は、接着剤や半田等の材料を別途設ける必要がなく、当該材料の使用に伴うコスト上昇と導電性及び熱伝導性の低下とを防止することができる他、半田の溶融開始温度等を設定せずとも貫通孔１５に金属片１６を固定することができる。 Here, in the metal piece fixing step, if the metal piece 16 is fixed to the through hole 15 of the first partial substrate 10 with solder, unless the melting start temperature or the like of the solder is appropriately set, the previous step and the subsequent step In this step, the solder used for the other part of the component-embedded substrate 1 may be melted by, for example, the heating of the reflow process, and the conductivity of the connection part due to the solder may be reduced. On the other hand, according to the component-embedded substrate 1 of the present invention, the metal piece and the through hole are fixed by mutual stress by, for example, a pressing machine. For this reason, the component-embedded substrate 1 does not need to separately provide a material such as an adhesive or solder, which can prevent an increase in cost and a decrease in electrical conductivity and thermal conductivity associated with the use of the material, and can also prevent soldering. The metal piece 16 can be fixed to the through hole 15 without setting the melting start temperature and the like.

また、本発明に係る部品内蔵基板１は、電子部品２０における第１面２１の全体が金属片１６に接するように、金属片１６の形状が設定されている。このため、電子部品２０における第１面２１の全体が金属片１６を介した放熱経路として構成され、発熱量が比較的多い電子部品２０に対しても効率的に放熱することができる。また、本発明に係る部品内蔵基板１によれば、薄型化されることにより部品内蔵基板１の反りに対して脆弱な電子部品２０を内蔵する場合であっても、金属片１６により曲がり応力に対して補強され、電子部品２０のクラックなどを防止できる他、部品内蔵基板の反りが抑制されるため導通ビアが剥離する虞を低減することができる。 Further, in the component-embedded substrate 1 according to the present invention, the shape of the metal piece 16 is set so that the entire first surface 21 of the electronic component 20 contacts the metal piece 16. Therefore, the entire first surface 21 of the electronic component 20 is configured as a heat radiation path via the metal piece 16, and heat can be efficiently radiated even to the electronic component 20 that generates a relatively large amount of heat. Further, according to the component-embedded substrate 1 of the present invention, even when the electronic component 20 that is vulnerable to the warp of the component-embedded substrate 1 due to being thinned is embedded, the metal piece 16 prevents bending stress. In addition, the electronic component 20 is reinforced against cracks and the like, and the electronic component 20 can be prevented from cracking, and the warpage of the component-embedded substrate is suppressed.

更に、本発明に係る部品内蔵基板１は、電子部品２０の第１電極端子２２と金属片１６との接触面に導電性ペースト３０が塗布されることにより、第１電極端子２２と金属片１６との電気的及び熱的な接続状態を良好に保つことができる。 Further, in the component built-in board 1 according to the present invention, the conductive paste 30 is applied to the contact surface between the first electrode terminal 22 and the metal piece 16 of the electronic component 20, so that the first electrode terminal 22 and the metal piece 16 are applied. A good electrical and thermal connection state with can be maintained.

そして、本発明に係る部品内蔵基板１は、電子部品２０の第２電極端子２４と導通する表面実装部品６０、６１が導通ビア５０に接するように配設されているため、両者の間の配線長が導通ビア５０の高さだけに抑えられ、配線抵抗やリアクタンス成分の影響を軽減して電気性能を向上させることができる。 In the component-embedded substrate 1 according to the present invention, the surface mount components 60 and 61 that are electrically connected to the second electrode terminals 24 of the electronic component 20 are arranged so as to be in contact with the conductive vias 50, so that the wiring between them is provided. The length is suppressed only to the height of the conductive via 50, the influence of the wiring resistance and the reactance component is reduced, and the electrical performance can be improved.

＜第２実施形態＞
次に、本発明の第２実施形態について説明する。第２実施形態に係る部品内蔵基板２は、上記した第１実施形態の部品内蔵基板１における第１導電層１１の構成が第１実施形態と異なる。以下、第１実施形態と異なる部分について説明することとし、第１実施形態と共通する構成要素については、同じ符号を付して詳細な説明を省略する。<Second Embodiment>
Next, a second embodiment of the present invention will be described. The component-embedded substrate 2 according to the second embodiment is different from the first embodiment in the configuration of the first conductive layer 11 in the component-embedded substrate 1 of the first embodiment described above. Hereinafter, parts different from those of the first embodiment will be described, and constituent elements common to the first embodiment will be denoted by the same reference numerals and detailed description thereof will be omitted.

図８は、本発明の第２実施形態に係る部品内蔵基板２の断面図である。第２実施形態に係る部品内蔵基板２は、第１実施形態において説明したパターニング工程（図６）より前に、第１導電層１１の表面に対して銅によるメッキ加工を施すことにより、第１導電層１１の厚みを増加させている。 FIG. 8 is a sectional view of the component-embedded substrate 2 according to the second embodiment of the present invention. The component-embedded substrate 2 according to the second embodiment has a structure in which the surface of the first conductive layer 11 is plated with copper before the patterning step (FIG. 6) described in the first embodiment. The thickness of the conductive layer 11 is increased.

これにより、部品内蔵基板２は、図８において破線楕円ＤＥで示すように、金属片１６とヒートシンク７０と間に第１導電層１１の一部が形成され、金属片１６と第１導電層１１との電気伝導性が向上する。これにより、電子部品２０から金属片１６及び第１導電層１１を介して表面実装部品６２へ至る導電路は、電子部品２０が比較的大きな電流を扱う部品であったとしても、導電性が良好で充分な断面積を確保することができる。 As a result, in the component-embedded substrate 2, a part of the first conductive layer 11 is formed between the metal piece 16 and the heat sink 70, as shown by the broken line ellipse DE in FIG. 8, and the metal piece 16 and the first conductive layer 11 are formed. The electrical conductivity with and is improved. Thus, the conductive path from the electronic component 20 to the surface mount component 62 via the metal piece 16 and the first conductive layer 11 has good conductivity even if the electronic component 20 is a component that handles a relatively large current. It is possible to secure a sufficient cross-sectional area.

＜第３実施形態＞
次に、本発明の第３実施形態について説明する。第３実施形態に係る部品内蔵基板３は、上記した第１実施形態の部品内蔵基板１における第２部分基板４０と表面実装部品６０、６１との間に第３部分基板８０が形成されている点で第１実施形態と異なる。以下、第１実施形態と異なる部分について説明することとし、第１実施形態と共通する構成要素については、同じ符号を付して詳細な説明を省略する。<Third Embodiment>
Next, a third embodiment of the present invention will be described. In the component built-in substrate 3 according to the third embodiment, a third partial substrate 80 is formed between the second partial substrate 40 and the surface mount components 60, 61 in the component built-in substrate 1 of the first embodiment described above. It differs from the first embodiment in points. Hereinafter, parts different from those of the first embodiment will be described, and constituent elements common to the first embodiment will be denoted by the same reference numerals and detailed description thereof will be omitted.

図９は、本発明の第３実施形態に係る部品内蔵基板３の断面図である。第３実施形態に係る部品内蔵基板３は、第１実施形態において説明したパターニング工程（図６）と表面実装工程（図７）との間のタイミングにおいて、第３部分基板８０が追加される。 FIG. 9 is a cross-sectional view of the component built-in board 3 according to the third embodiment of the present invention. In the component built-in substrate 3 according to the third embodiment, the third partial substrate 80 is added at the timing between the patterning process (FIG. 6) and the surface mounting process (FIG. 7) described in the first embodiment.

第３部分基板８０は、第２部分基板４０の第２導電層４２に対して第３絶縁層８１、及び第３導電層８２を積層することで、第２部分基板４０と同様の材料及び工程により形成することができる。そして、第３導電層８２を部品内蔵基板３の外層回路として、表面実装部品６０及び６１を実装する。 The third partial substrate 80 has the same material and process as the second partial substrate 40 by stacking the third insulating layer 81 and the third conductive layer 82 on the second conductive layer 42 of the second partial substrate 40. Can be formed by. Then, the surface mount components 60 and 61 are mounted using the third conductive layer 82 as an outer layer circuit of the component-embedded substrate 3.

このとき、図９に示すように、表面実装部品６０と電子部品２０とを導通させる２つの導通ビア５０のように、互いの位置をずらして配置することができるため、表面実装部品６０の配置を含む回路構成の自由度を向上させることができる。また、表面実装部品６１と電子部品２０とを導通させる２つの導通ビア５０のように、互いの位置を合わせて直線上に配置することにより、第３部分基板８０の追加で導電層を増加させながらも、表面実装部品６１と電子部品２０との配線長の増加を最小限に抑制することができる。 At this time, as shown in FIG. 9, since the surface mounting component 60 and the electronic component 20 can be arranged such that they are displaced from each other like the two conductive vias 50 that electrically connect, the surface mounting component 60 can be arranged. It is possible to improve the degree of freedom of the circuit configuration including. Further, like the two conductive vias 50 that electrically connect the surface-mounted component 61 and the electronic component 20, by arranging them in a straight line with their positions aligned with each other, the conductive layer is increased by adding the third partial substrate 80. However, the increase in the wiring length between the surface mount component 61 and the electronic component 20 can be suppressed to the minimum.

＜第４実施形態＞
次に、本発明の第４実施形態について説明する。第４実施形態に係る部品内蔵基板４は、上記した第１実施形態の部品内蔵基板１における電子部品２０及び金属片１６の形状が第１実施形態と異なる。以下、第１実施形態と異なる部分について説明することとし、第１実施形態と共通する構成要素については、同じ符号を付して詳細な説明を省略する。<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described. The component-embedded substrate 4 according to the fourth embodiment is different from the first embodiment in the shapes of the electronic component 20 and the metal piece 16 in the component-embedded substrate 1 of the first embodiment described above. Hereinafter, parts different from those of the first embodiment will be described, and constituent elements common to the first embodiment will be denoted by the same reference numerals and detailed description thereof will be omitted.

図１０は、本発明の第４実施形態に係る部品設置工程を表す断面図である。第４実施形態に係る部品内蔵基板４の電子部品２０´は、第１面２１の表面から突出するように第１電極端子２２´が設けられ、第２面２３の表面から突出するように２つの第２電極端子２４´が設けられている。 FIG. 10 is a cross-sectional view showing a component installation step according to the fourth embodiment of the present invention. The electronic component 20 ′ of the component-embedded substrate 4 according to the fourth embodiment is provided with the first electrode terminals 22 ′ so as to project from the surface of the first surface 21, and the electronic component 20 ′ so as to project from the surface of the second surface 23. Two second electrode terminals 24' are provided.

第４実施形態に係る金属片１６´は、電子部品２０´が設置される表面において、第１電極端子２２´に嵌合する凹部１６ａが形成されている。凹部１６ａは、上記した金属片固定工程において形成される。すなわち、金属片１６´は、例えば圧入法が採用される場合には予め凹部１６ａが形成された金属片１６´を第１部分基板１０の貫通孔１５に押し込むことにより形成され、カシメ法が採用される場合には電子部品２０´の第１面２１と略同一形状のプレス治具により押圧されて形成される。 In the metal piece 16′ according to the fourth embodiment, a recess 16a that fits into the first electrode terminal 22′ is formed on the surface on which the electronic component 20′ is installed. The recess 16a is formed in the metal piece fixing process described above. That is, the metal piece 16 ′ is formed, for example, by pressing the metal piece 16 ′ in which the recess 16 a is formed in advance into the through hole 15 of the first partial substrate 10 when the press fitting method is adopted, and the caulking method is adopted. In this case, the electronic component 20' is formed by being pressed by a pressing jig having substantially the same shape as the first surface 21 of the electronic component 20'.

ここで、電子部品２０´を金属片１６´に設置する際には、上記した第１実施形態における部品設置工程と同様に、両者の接触面に導電性ペースト３０を塗布してもよい。 Here, when the electronic component 20 ′ is installed on the metal piece 16 ′, the conductive paste 30 may be applied to the contact surface between the two, as in the component installation step in the first embodiment described above.

図１１は、本発明の第４実施形態に係る部品内蔵基板４の断面図である。図１１に示されるように、電子部品２０´の第１電極端子２２´が第１面２１から突出する形状であったとしても、金属片１６´に凹部１６ａを設けることにより、電子部品２０´の第１面２１の全体が第１電極端子２２´を含めて金属片１６´に接することになる。従って、部品内蔵基板４によれば、電子部品２０´と金属片１６´との導電性及び熱伝導性を良好に保つことができる。 FIG. 11 is a sectional view of the component-embedded substrate 4 according to the fourth embodiment of the present invention. As shown in FIG. 11, even if the first electrode terminal 22 ′ of the electronic component 20 ′ has a shape protruding from the first surface 21, the recess 16 a is provided in the metal piece 16 ′, so that the electronic component 20 ′ is provided. The entire first surface 21 of the above, including the first electrode terminal 22', comes into contact with the metal piece 16'. Therefore, according to the component-embedded substrate 4, it is possible to maintain good electrical conductivity and thermal conductivity between the electronic component 20' and the metal piece 16'.

１ 部品内蔵基板
１０ 第１部分基板
１１ 第１導電層
１５ 貫通孔
１６ 金属片
２０ 電子部品
２１ 第１面
２２ 第１電極端子
２３ 第２面
２４ 第２電極端子
４０ 第２部分基板
４１ 第２絶縁層
４２ 第２導電層
５０ 導通ビア1 Component Embedded Substrate 10 First Partial Substrate 11 First Conductive Layer 15 Through Hole 16 Metal Piece 20 Electronic Component 21 First Surface 22 First Electrode Terminal 23 Second Surface 24 Second Electrode Terminal 40 Second Partial Substrate 41 Second Insulation Layer 42 Second conductive layer 50 Conductive via

Claims (10)

一方の面に第１導電層が設けられ、貫通孔が形成された第１部分基板と、
前記第１導電層と導通するように前記貫通孔に固定された金属片と、
前記第１部分基板の他方の面において前記金属片と接する第１電極端子が第１面に設けられ、前記第１面と反対側の第２面に第２電極端子が設けられた電子部品と、
前記電子部品を埋設する絶縁層を含む第２部分基板と、を備え、
前記金属片は、前記貫通孔の内側面との互いの応力により前記貫通孔に固定され、前記電子部品における前記第１面の全体が接する形状である、部品内蔵基板。A first partial substrate provided with a first conductive layer on one surface and having a through hole,
A metal piece fixed to the through hole so as to be electrically connected to the first conductive layer;
An electronic component in which a first electrode terminal in contact with the metal piece is provided on the first surface of the other surface of the first partial substrate, and a second electrode terminal is provided on a second surface opposite to the first surface. ,
A second partial substrate including an insulating layer in which the electronic component is embedded,
The component-embedded substrate, wherein the metal piece is fixed to the through hole by mutual stress with the inner surface of the through hole, and has a shape in which the entire first surface of the electronic component is in contact. 前記第１導電層の一部が前記金属片の表面に形成されている、請求項１に記載の部品内蔵基板。 The component-embedded substrate according to claim 1, wherein a part of the first conductive layer is formed on a surface of the metal piece. 前記電子部品の前記第１電極端子は、前記第１面から突出するように設けられ、
前記金属片は、前記電子部品が設置される表面において、前記第１電極端子に嵌合する凹部が形成されている、請求項１叉は２に記載の部品内蔵基板。The first electrode terminal of the electronic component is provided so as to project from the first surface,
The component built-in board according to claim 1 or 2, wherein the metal piece has a concave portion formed on the surface on which the electronic component is mounted, the concave portion being fitted into the first electrode terminal. 前記電子部品の前記第１電極端子と前記金属片との接触面に導電性ペーストが塗布されている、請求項１乃至３のいずれかに記載の部品内蔵基板。 The component-embedded substrate according to claim 1, wherein a conductive paste is applied to a contact surface between the first electrode terminal of the electronic component and the metal piece. 前記絶縁層を貫通して前記電子部品の前記第２電極端子に接続される導通ビアを含み、
前記導通ビアに接するように表面実装部品が配設されている、請求項１乃至４のいずれかに記載の部品内蔵基板。Including a conductive via penetrating the insulating layer and connected to the second electrode terminal of the electronic component;
The component-embedded substrate according to claim 1, wherein a surface-mounted component is arranged so as to be in contact with the conductive via. 第１面に第１電極端子が設けられ、前記第１面と反対側の第２面に第２電極端子が設けられた電子部品を内蔵する部品内蔵基板の製造方法であって、
一方の面に第１導電層が設けられた第１部分基板に貫通孔を形成する貫通孔形成工程と、
前記第１導電層と導通するように金属片を前記貫通孔に固定する金属片固定工程と、
前記第１部分基板の他方の面において前記金属片と前記第１電極端子とが接するように前記電子部品を設置する部品設置工程と、
前記電子部品を絶縁層で埋設する第２部分基板を形成する部品埋設工程と、を含み、
前記金属片固定工程においては、前記貫通孔の内側面と前記金属片との互いの応力により前記金属片を前記貫通孔に固定し、前記電子部品における前記第１面の全体が前記金属片に接するように前記金属片の形状が設定される、部品内蔵基板の製造方法。A method of manufacturing a component-embedded substrate having a built-in electronic component, wherein a first electrode terminal is provided on a first surface, and a second electrode terminal is provided on a second surface opposite to the first surface.
A through hole forming step of forming a through hole in the first partial substrate having the first conductive layer provided on one surface;
A metal piece fixing step of fixing the metal piece to the through hole so as to be electrically connected to the first conductive layer;
A component installation step of installing the electronic component so that the metal piece and the first electrode terminal are in contact with each other on the other surface of the first partial substrate;
A component embedding step of forming a second partial substrate in which the electronic component is embedded with an insulating layer,
In the metal piece fixing step, the metal piece is fixed to the through hole by mutual stress between the inner surface of the through hole and the metal piece, and the entire first surface of the electronic component is the metal piece. A method of manufacturing a component-embedded substrate, wherein the shape of the metal piece is set so as to be in contact with each other. 前記第１導電層の一部を前記金属片の表面に形成する、請求項６に記載の部品内蔵基板の製造方法。 The method for manufacturing a component-embedded substrate according to claim 6, wherein a part of the first conductive layer is formed on the surface of the metal piece. 前記電子部品の前記第１電極端子は、前記第１面から突出するように設けられ、
前記金属片は、前記電子部品が設置される表面において、前記第１電極端子に嵌合する凹部が形成されている、請求項６叉は７に記載の部品内蔵基板の製造方法。The first electrode terminal of the electronic component is provided so as to project from the first surface,
The method for manufacturing a component-embedded substrate according to claim 6 or 7, wherein the metal piece has a recess formed on the surface on which the electronic component is mounted, the recess being fitted to the first electrode terminal. 前記部品設置工程においては、前記電子部品の前記第１電極端子と前記金属片との接触面に導電性ペーストを塗布する、請求項６乃至８のいずれかに記載の部品内蔵基板の製造方法。 9. The method of manufacturing a component-embedded substrate according to claim 6, wherein in the component installation step, a conductive paste is applied to a contact surface between the first electrode terminal of the electronic component and the metal piece. 前記絶縁層を貫通して前記電子部品の前記第２電極端子に接続される導通ビアを形成し、前記導通ビアに接するように表面実装部品を配設する表面実装工程を含む、請求項６乃至９のいずれかに記載の部品内蔵基板の製造方法。 7. A surface mounting step of forming a conductive via penetrating the insulating layer to be connected to the second electrode terminal of the electronic component, and disposing a surface mount component in contact with the conductive via. 9. The method of manufacturing a component-embedded substrate according to any one of 9 above.
JP2019569846A 2019-06-14 2019-06-14 Component-embedded substrate and method for manufacturing component-embedded substrate Active JP6716045B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/023596 WO2020250405A1 (en) 2019-06-14 2019-06-14 Substrate with built-in component and method for manufacturing substrate with built-in component

Publications (2)

Publication Number Publication Date
JP6716045B1 true JP6716045B1 (en) 2020-07-01
JPWO2020250405A1 JPWO2020250405A1 (en) 2021-09-13

Family

ID=71131661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019569846A Active JP6716045B1 (en) 2019-06-14 2019-06-14 Component-embedded substrate and method for manufacturing component-embedded substrate

Country Status (3)

Country Link
JP (1) JP6716045B1 (en)
CN (1) CN114008769A (en)
WO (1) WO2020250405A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022009300A1 (en) * 2020-07-07 2022-01-13 株式会社メイコー Substrate with insulating heat dissipation block and method for producing same
KR20230153369A (en) 2021-03-05 2023-11-06 가부시키가이샤 메이코 Component-embedded board, and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023179842A1 (en) * 2022-03-21 2023-09-28 Hitachi Energy Switzerland Ag Power submodule, power module and method for producing a power module

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060523A (en) * 2001-08-09 2003-02-28 Tdk Corp Radio communication module
JP2011009715A (en) * 2009-05-25 2011-01-13 Denso Corp Semiconductor device
US20140070397A1 (en) * 2012-09-13 2014-03-13 Lakshminarayan Viswanathan High power semiconductor package subsystems
WO2014199456A1 (en) * 2013-06-12 2014-12-18 株式会社メイコー Manufacturing method for heat-dissipating substrate
WO2017086095A1 (en) * 2015-11-17 2017-05-26 株式会社村田製作所 Multilayer substrate and electronic apparatus
US20180190563A1 (en) * 2017-01-03 2018-07-05 Stmicroelectronics S.R.L. Semiconductor device, corresponding circuit and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060523A (en) * 2001-08-09 2003-02-28 Tdk Corp Radio communication module
JP2011009715A (en) * 2009-05-25 2011-01-13 Denso Corp Semiconductor device
US20140070397A1 (en) * 2012-09-13 2014-03-13 Lakshminarayan Viswanathan High power semiconductor package subsystems
WO2014199456A1 (en) * 2013-06-12 2014-12-18 株式会社メイコー Manufacturing method for heat-dissipating substrate
WO2017086095A1 (en) * 2015-11-17 2017-05-26 株式会社村田製作所 Multilayer substrate and electronic apparatus
US20180190563A1 (en) * 2017-01-03 2018-07-05 Stmicroelectronics S.R.L. Semiconductor device, corresponding circuit and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022009300A1 (en) * 2020-07-07 2022-01-13 株式会社メイコー Substrate with insulating heat dissipation block and method for producing same
KR20230153369A (en) 2021-03-05 2023-11-06 가부시키가이샤 메이코 Component-embedded board, and manufacturing method thereof

Also Published As

Publication number Publication date
CN114008769A (en) 2022-02-01
JPWO2020250405A1 (en) 2021-09-13
WO2020250405A1 (en) 2020-12-17

Similar Documents

Publication Publication Date Title
EP3226292B1 (en) Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device
JP6716045B1 (en) Component-embedded substrate and method for manufacturing component-embedded substrate
US20130027896A1 (en) Electronic component embedded printed circuit board and method of manufacturing the same
JP4344753B2 (en) Electronic component mounting method on circuit board
JP2008103615A (en) Electronic component mounting multilayer wiring board and its manufacturing method
US20180326924A1 (en) Circuit assembly and electrical junction box
JP2010157663A (en) Component built-in wiring board, and method of manufacturing component built-in wiring board
JP4967701B2 (en) Power semiconductor device
CN111132476A (en) Preparation method of double-sided circuit radiating substrate
US9345125B2 (en) Wiring substrate
JPWO2010103695A1 (en) Manufacturing method of component built-in module and component built-in module
JP5397012B2 (en) Component built-in wiring board, method of manufacturing component built-in wiring board
JP5369875B2 (en) Component built-in wiring board, method of manufacturing component built-in wiring board
JP6391430B2 (en) Electronic control device and manufacturing method thereof
JP2004055967A (en) Manufacturing method of board with built-in electronic component
JP2012209590A (en) Electronic component mounting multilayer wiring board and manufacturing method of the same
JP4452888B2 (en) Electronic circuit equipment
WO2022004332A1 (en) Circuit structure
JP2010003718A (en) Heat-dissipating substrate and its manufacturing method, and module using heat-dissipating substrate
JP2019029622A (en) Heat dissipation substrate and method for manufacturing heat dissipation substrate
JP5601413B2 (en) Component built-in wiring board, method of manufacturing component built-in wiring board
JP7161629B1 (en) Substrate with built-in component and method for manufacturing the same
CN110996501A (en) Circuit board and power module with through type conductive and heat dissipation component
JP7018967B2 (en) Heat dissipation board and its manufacturing method
CN216671606U (en) Chip packaging body and electronic device

Legal Events

Date Code Title Description
A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A527

Effective date: 20191216

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191216

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20191216

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20200205

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200603

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200609

R150 Certificate of patent or registration of utility model

Ref document number: 6716045

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250