JP6706942B2 - Circuit board with built-in components - Google Patents
Circuit board with built-in components Download PDFInfo
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- JP6706942B2 JP6706942B2 JP2016060734A JP2016060734A JP6706942B2 JP 6706942 B2 JP6706942 B2 JP 6706942B2 JP 2016060734 A JP2016060734 A JP 2016060734A JP 2016060734 A JP2016060734 A JP 2016060734A JP 6706942 B2 JP6706942 B2 JP 6706942B2
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- 239000000758 substrate Substances 0.000 claims description 76
- 239000011241 protective layer Substances 0.000 claims description 37
- 239000010409 thin film Substances 0.000 claims description 30
- 239000010410 layer Substances 0.000 claims description 29
- 239000010408 film Substances 0.000 claims description 25
- 229920005989 resin Polymers 0.000 claims description 16
- 239000011347 resin Substances 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000005553 drilling Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910018487 Ni—Cr Inorganic materials 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
本発明は、基板内蔵用チップ抵抗器が絶縁性の樹脂層に埋め込まれている部品内蔵型回路基板に関するものである。
The present invention relates to a component built-in circuit board which board built chip resistor is embedded in the insulating resin layer.
近年、電子機器の小型化や高機能化に伴い、チップ抵抗器を回路基板に内蔵することにより、回路基板に対する単位面積当りの回路密度を高める工夫がなされている。このような回路基板では、絶縁性の樹脂層からなるベース基板にチップ抵抗器を埋め込んだ後に、この樹脂層の表面にレーザを照射して穴あけ加工を行い、その穴の内部にメッキ処理を施してビアを形成することにより、チップ抵抗器の外部電極とビアとを接続するようになっている。 In recent years, with the miniaturization and higher functionality of electronic devices, a device for increasing the circuit density per unit area of the circuit board has been made by incorporating a chip resistor in the circuit board. In such a circuit board, after embedding a chip resistor in a base substrate made of an insulating resin layer, the surface of this resin layer is irradiated with a laser to perform a drilling process, and the inside of the hole is plated. The vias are formed by connecting the external electrodes of the chip resistor to the vias.
ここで、穴あけ加工の際には、樹脂層に埋め込まれているチップ抵抗器の外部電極に向けてレーザを照射させて外部電極を露出させる必要があるが、一般的に、樹脂層として不透明材料が使用されているため、樹脂層に埋め込まれているチップ抵抗器の外部電極を目視することができない。このため、穴あけ加工の際に穴の形成位置がずれてしまい、外部電極とビアとの接続信頼性が低下してしまうという課題がある。 Here, at the time of drilling, it is necessary to irradiate a laser toward the external electrode of the chip resistor embedded in the resin layer to expose the external electrode. Generally, the opaque material is used as the resin layer. However, the external electrodes of the chip resistor embedded in the resin layer cannot be visually inspected. Therefore, there is a problem that the hole forming position is displaced during the drilling process, and the connection reliability between the external electrode and the via is deteriorated.
このような課題を解決するために、特許文献1に記載されたチップ抵抗器では、外部電極を大きくすることによって、ビアとの接続を確実にしている。すなわち、図7に示すように、特許文献1に記載のチップ抵抗器101は、直方体状の絶縁性基板102と、絶縁性基板102の表面に所定間隔を存して対向配置された一対の第1内部電極103と、一対の第1内部電極103に接続するように絶縁性基板102の表面に設けられた抵抗体104と、抵抗体104を覆うように形成された第1保護層105および第2保護層106と、第1内部電極103の露出部および第2保護層106の端部を覆うように形成された一対の第2内部電極107と、第2内部電極107を覆うように形成された外部電極108と、を備えている。 In order to solve such a problem, in the chip resistor described in Patent Document 1, the external electrode is enlarged to ensure the connection with the via. That is, as shown in FIG. 7, a chip resistor 101 described in Patent Document 1 includes a rectangular parallelepiped insulating substrate 102 and a pair of first and second opposing faces arranged at a predetermined interval on the surface of the insulating substrate 102. 1 internal electrode 103, a resistor 104 provided on the surface of the insulating substrate 102 so as to be connected to the pair of first internal electrodes 103, a first protective layer 105 and a first protective layer 105 formed so as to cover the resistor 104, and 2 protective layer 106, a pair of second internal electrodes 107 formed so as to cover the exposed portion of the first internal electrode 103 and the end portion of the second protective layer 106, and formed so as to cover the second internal electrode 107. And an external electrode 108.
第1内部電極103は、銀を主成分とする導電材料からなり、絶縁性基板102の表面にスクリーン印刷にて厚膜形成される。具体的には、絶縁性基板102の表面にスクリーンマスクをセットし、スクリーンマスク上に印刷用のAg−Pdペーストを供給しスキージングを行うことにより、Ag−Pdペーストがスクリーンマスクのパターン孔を通して絶縁性基板102の表面に塗布され、これを乾燥させた後に焼成することで、厚膜焼成体からなる第1内部電極103が得られる。同様に、抵抗体104と両保護層105,106および第2内部電極107もスクリーン印刷にて厚膜形成される。 The first internal electrode 103 is made of a conductive material containing silver as a main component, and is formed as a thick film on the surface of the insulating substrate 102 by screen printing. Specifically, by setting a screen mask on the surface of the insulating substrate 102, supplying Ag-Pd paste for printing on the screen mask and performing squeezing, the Ag-Pd paste passes through the pattern holes of the screen mask. By coating the surface of the insulating substrate 102, drying it, and then firing it, the first internal electrode 103 made of a thick-film fired body is obtained. Similarly, the resistor 104, the protective layers 105 and 106, and the second internal electrode 107 are also formed into a thick film by screen printing.
特許文献1に記載のチップ抵抗器101では、一対の第1内部電極103の対向間隔よりも一対の第2内部電極107の対向間隔の方が狭く形成されているため、第2内部電極107を覆う外部電極108の表面積を広く確保することができる。その結果、穴の形成位置が多少ずれたとしても、チップ抵抗器の外部電極とビアとを接続することが可能になる。 In the chip resistor 101 described in Patent Document 1, since the facing distance between the pair of second internal electrodes 107 is smaller than the facing distance between the pair of first internal electrodes 103, the second internal electrode 107 is A wide surface area of the external electrode 108 to be covered can be secured. As a result, it becomes possible to connect the external electrode of the chip resistor and the via even if the formation position of the hole is slightly displaced.
ところで、スクリーン印刷による厚膜形成では、スクリーンマスクずれやペーストのダレ等に起因して内部電極の間隔や抵抗体の寸法にばらつきが生じ、抵抗値の精度に影響を与えてしまう虞があるため、内部電極と抵抗体とをスクリーン印刷による厚膜形成に替えてフォトリソ等による薄膜形成することが考えられる。このようにすると内部電極等の間隔を一定の間隔で保つことが可能になり、電極寸法精度や抵抗値精度の高いチップ抵抗器を製造することができる。また、一般的に厚膜形成される内部電極に使用される銀は、温度によって抵抗値が大きく変動するため、内部電極自体の温度変化による抵抗値の変動や、抵抗体の形成時に銀が抵抗体へ拡散することによって、抵抗体の抵抗値の変動が発生するおそれが高くなる。したがって、内部電極をCu等の材料にて薄膜形成することによって、温度変化による内部電極の抵抗値の変動を小さくすることが可能になり、温度変化による抵抗値の変動の少ないチップ抵抗器を製造することができる。 By the way, in thick film formation by screen printing, there is a possibility that variations in the intervals between internal electrodes and dimensions of resistors may occur due to screen mask displacement, paste sag, etc., which may affect the accuracy of resistance values. It is conceivable to form the thin film by photolithography or the like instead of forming the thick film by screen printing for the internal electrodes and the resistor. In this way, it becomes possible to keep the intervals of the internal electrodes and the like at constant intervals, and it is possible to manufacture a chip resistor having high electrode dimension accuracy and resistance value accuracy. In addition, since the resistance value of silver used for thick internal electrodes generally fluctuates greatly depending on the temperature, the resistance value fluctuates due to the temperature change of the internal electrodes themselves, and silver does not resist when the resistor is formed. Diffusion into the body increases the risk of fluctuations in the resistance value of the resistor. Therefore, by forming a thin film of a material such as Cu on the internal electrodes, it is possible to reduce the variation in the resistance value of the internal electrodes due to temperature changes, and manufacture a chip resistor in which the variation in resistance values due to temperature changes is small. can do.
そこで、図8に示すように、第1および第2内部電極と抵抗体とを薄膜形成すると共に、保護層を厚膜形成することにより、外部電極の表面積を広く確保しつつ、外部電極とビアとの接続を容易にしたチップ抵抗器が考えられる。すなわち、図8に示すチップ抵抗器111は、直方体状の絶縁性基板112と、絶縁性基板112における長手方向両端部に薄膜形成された一対の第1内部電極113と、これら第1内部電極113に接続するように薄膜形成された抵抗体114と、第1内部電極113の端部と抵抗体114とを連続して覆うように厚膜形成された保護層115と、一対の第1内部電極113の対向間隔よりも狭い対向間隔となるように薄膜形成された一対の第2内部電極116と、第2内部電極116を覆うようにメッキ形成された外部電極117と、を備えている。 Therefore, as shown in FIG. 8, by forming a thin film of the first and second internal electrodes and the resistor and a thick film of the protective layer, a large surface area of the external electrode is ensured and the external electrode and the via are secured. A chip resistor that can be easily connected to is considered. That is, the chip resistor 111 shown in FIG. 8 has a rectangular parallelepiped insulating substrate 112, a pair of first internal electrodes 113 formed in thin films on both ends in the longitudinal direction of the insulating substrate 112, and these first internal electrodes 113. A resistor 114 formed in a thin film so as to be connected to a resistor, a protective layer 115 formed in a thick film so as to continuously cover the end portion of the first internal electrode 113 and the resistor 114, and a pair of first internal electrodes. A pair of second internal electrodes 116 formed in a thin film so as to have an opposing interval narrower than the opposing interval of 113, and an external electrode 117 formed by plating so as to cover the second internal electrode 116.
上述のように構成したチップ抵抗器111では、薄膜の第1内部電極113上に厚膜の保護層115が形成され、これら第1内部電極113と保護層115とを第2内部電極116が連続して覆うように形成されていることから、保護層115の端面から第1内部電極113の表面にかけて段差部が形成されてしまい、その結果、第2内部電極116の表面を覆う外部電極117に大きな段差部118が生じてしまう。 In the chip resistor 111 configured as described above, the thick protective layer 115 is formed on the thin first internal electrode 113, and the first internal electrode 113 and the protective layer 115 are continuously connected to the second internal electrode 116. Since it is formed so as to cover the surface of the first internal electrode 113 from the end surface of the protective layer 115, a step portion is formed, and as a result, the external electrode 117 covering the surface of the second internal electrode 116 is formed. A large step portion 118 is generated.
このようなチップ抵抗器111が内蔵されたベース基板に穴あけ加工してビアを形成する場合、段差部118付近における外部電極117の表面は階段状に形成されていることから、段差部118の直上付近にある樹脂層にレーザを照射して穴を形成すると、穴の内部に形成されたビアと外部電極117との接続不良になる虞がある。このように、特許文献1に記載の技術を適用させて外部電極を大きく形成したとしても、外部電極117の表面のうち段差部118よりも外側の領域はビアとの接続が困難な領域となり、実質的に、外部電極117とビアとの接続可能な領域は、外部電極117の表面のうち段差部118よりも内側の同図中に示す狭い領域Fに限定されてしまう。 When forming a via in the base substrate having the chip resistor 111 built therein, the surface of the external electrode 117 in the vicinity of the step portion 118 is formed in a step-like shape, and therefore, it is directly above the step portion 118. When a hole is formed by irradiating a resin layer in the vicinity with a laser, there is a fear that the connection between the via formed inside the hole and the external electrode 117 may be poor. In this way, even if the technique described in Patent Document 1 is applied to form the external electrode in a large size, the region outside the step portion 118 on the surface of the external electrode 117 becomes a region in which connection with the via is difficult, Substantially, the area where the external electrode 117 and the via can be connected is limited to the narrow area F shown in the figure inside the step portion 118 on the surface of the external electrode 117.
本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、ビア用の穴あけ加工が容易な部品内蔵型回路基板を提供することにある。
The present invention has such has been made in view of the circumstances of prior art, and it is desirable drilling for vias to provide easy component built-in circuit board.
上記の目的を達成するために、本発明の部品内蔵型回路基板は、絶縁性の樹脂層からなるベース基板の内層にチップ抵抗器が埋め込まれている部品内蔵型回路基板において、前記チップ抵抗器が、直方体形状の絶縁性基板と、前記絶縁性基板における長手方向両端部に薄膜形成された一対の第1内部電極と、前記一対の第1内部電極に接続するように薄膜形成された抵抗体と、少なくとも前記抵抗体を覆うように厚膜形成された保護層と、前記一対の第1内部電極の対向間隔よりも狭い対向間隔となるように薄膜形成された一対の第2内部電極と、前記第2内部電極を覆うようにメッキ形成された外部電極とを備え、前記保護層が前記抵抗体と前記第1内部電極とを覆うように形成されていると共に、この第1内部電極における前記絶縁性基板の長手方向両端から内側に離反した位置に前記保護層によって覆われていない露出部が形成されており、前記第2内部電極が前記露出部を含んで前記保護層を覆うように形成されていることにより、前記露出部と対応する位置に凹部が形成され、前記凹部を跨いで前記外部電極と接続するビアを前記ベース基板に形成可能であり、前記凹部の幅は前記ビアの内径よりも狭くなるように形成されていることを特徴とする。
To achieve the above Symbol purpose of the built-in component type circuit board of the present invention is the component built-in circuit board has the chip resistor is embedded in the inner layer of the base substrate made of an insulating resin layer, said chip resistor And a resistor having a thin film formed so as to be connected to the pair of first internal electrodes, the pair of first internal electrodes having a thin film formed on both ends in the longitudinal direction of the insulating substrate. A body, a protective layer formed in a thick film so as to cover at least the resistor, and a pair of second internal electrodes formed in a thin film so as to have an opposing interval narrower than the opposing interval of the pair of first internal electrodes. An external electrode plated to cover the second internal electrode, wherein the protective layer is formed to cover the resistor and the first internal electrode, and An exposed portion that is not covered by the protective layer is formed at positions inwardly separated from both ends in the longitudinal direction of the insulating substrate, and the second internal electrode covers the protective layer including the exposed portion. by being formed, the recess is formed at a position corresponding to the exposed portion, Ri formable der vias to be connected to the external electrode across the recess on the base substrate, the width of the concave portion the via It is characterized in that it is formed to be narrower than the inner diameter of .
本発明によると、外部電極の表面の高さは、凹部を除いて殆ど同じ高さになるため、少なくとも凹部を除いた外部電極の表面をビアと接続可能な領域として利用することができる。さらに、本発明では、第1内部電極の露出部と対応する位置に形成された凹部を跨ぐようにビアをベース基板に形成可能であるため、凹部を含めた外部電極の表面全体がビアと接続可能な領域となり、ビア用の穴あけ加工が容易となる。 According to the present invention, the height of the surface of the external electrode is almost the same except for the recess, so that the surface of the external electrode except at least the recess can be used as a region connectable to the via. Further, according to the present invention, since the via can be formed in the base substrate so as to extend over the recess formed in the position corresponding to the exposed portion of the first internal electrode, the entire surface of the external electrode including the recess is connected to the via. This is a possible area, which facilitates drilling for vias.
本発明によれば、ビア用の穴あけ加工が容易な部品内蔵型回路基板を提供することができる。
According to the present invention, it is possible to drilling for vias that provide easy component built-in circuit board.
以下、本発明の実施の形態について図面を参照しながら説明する。図1,2に示すように、本発明の第1実施形態例に係る基板内層用チップ抵抗器(以下、チップ抵抗器と言う)1は、直方体形状の絶縁性基板2と、絶縁性基板2における長手方向両端部に薄膜形成された一対の第1内部電極3,4と、一対の第1内部電極3,4に接続するように薄膜形成された抵抗体5と、少なくとも抵抗体5を覆うように厚膜形成された保護層6と、一対の第1内部電極3,4の対向間隔よりも狭い対向間隔となるように薄膜形成された一対の第2内部電極7,8と、第2内部電極7,8を覆うようにメッキ形成された外部電極9,10とによって主として構成されている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, a chip resistor for a substrate inner layer (hereinafter referred to as a chip resistor) 1 according to a first embodiment of the present invention includes a rectangular parallelepiped insulating substrate 2 and an insulating substrate 2. A pair of first internal electrodes 3, 4 formed in thin films at both ends in the longitudinal direction, a resistor 5 formed in a thin film so as to be connected to the pair of first internal electrodes 3, 4, and at least the resistor 5 is covered. The protective layer 6 thus formed in a thick film, the pair of second internal electrodes 7, 8 formed in a thin film so as to have an opposing interval narrower than the opposing interval of the pair of first internal electrodes 3, 4; It is mainly configured by external electrodes 9 and 10 formed by plating so as to cover the internal electrodes 7 and 8.
絶縁性基板2はセラミックス基板からなり、この絶縁性基板2は後述する大判基板を縦横に延びる分割溝に沿って分割して多数個取りされたものである。 The insulative substrate 2 is made of a ceramic substrate, and the insulative substrate 2 is obtained by dividing a large-sized substrate, which will be described later, along division grooves extending vertically and horizontally to obtain a large number.
抵抗体5は絶縁性基板2の表面上に薄膜形成されたNi−Cr系等の抵抗材料からなり、抵抗体5の中央部がミアンダ形状(サーペンタイン形状)に蛇行した抵抗パターンとなっている。この抵抗体5は、絶縁性基板2の表面全体にNi−Cr系等を蒸着またはスパッタした後、これをフォトリソ/エッチングしてミアンダ形状にパターニングされたものである。 The resistor 5 is made of a resistive material such as Ni—Cr based on which a thin film is formed on the surface of the insulating substrate 2. The resistor 5 has a meandering (serpentine) meandering resistance pattern at its central portion. The resistor 5 is formed by vapor-depositing or sputtering a Ni—Cr-based material or the like on the entire surface of the insulating substrate 2 and then photolithographically/etching the same to pattern it in a meandering shape.
一対の第1内部電極3,4は抵抗体5の両端部上に薄膜形成されたCu等の電極材料からなり、これら第1内部電極3,4は、パターニング前の抵抗膜(抵抗体5)の表面全体にCu等を蒸着またはスパッタした後、これをフォトリソ/エッチングして矩形状にパターニングされたものである。なお、一対の第1内部電極3,4は保護層6によって覆われない露出部を有している。 The pair of first internal electrodes 3 and 4 is made of an electrode material such as Cu formed in a thin film on both ends of the resistor 5, and these first internal electrodes 3 and 4 are the resistive film (resistor 5) before patterning. After Cu or the like is vapor-deposited or sputtered on the entire surface of the above, it is photolithographically/etched and patterned into a rectangular shape. The pair of first internal electrodes 3, 4 have exposed portions that are not covered by the protective layer 6.
保護層6は第1内部電極3,4と抵抗体5とを覆うように厚膜形成されたエポキシ樹脂等の絶縁材料からなり、この保護層6は、第1内部電極3,4における絶縁性基板2の長手方向両端から内側に離反した位置にある露出部3a,4aと、図示左側の露出部3aから絶縁性基板2の両長辺まで延びて露出部3aに連続する絶縁性基板2の領域2aと、図示右側の露出部4aから絶縁性基板2の両長辺まで延びて露出部4aに連続する絶縁性基板2の領域2bとを除いて、第1内部電極3,4の表面、第1内部電極3,4から露出する抵抗体5の表面、第1内部電極3,4および抵抗体5から露出する絶縁性基板2の表面のそれぞれにエポキシ樹脂等のペースト状絶縁材料をスクリーン印刷して加熱硬化させたものである。 The protective layer 6 is made of an insulating material such as an epoxy resin formed as a thick film so as to cover the first internal electrodes 3 and 4 and the resistor 5, and the protective layer 6 has an insulating property in the first internal electrodes 3 and 4. The exposed portions 3a and 4a located at positions inwardly separated from both ends in the longitudinal direction of the substrate 2 and the insulating substrate 2 extending from the exposed portion 3a on the left side in the figure to both long sides of the insulating substrate 2 and continuing to the exposed portion 3a. Except for the region 2a and the region 2b of the insulating substrate 2 which extends from the exposed portion 4a on the right side of the figure to both long sides of the insulating substrate 2 and is continuous with the exposed portion 4a, the surfaces of the first internal electrodes 3, 4 are Screen-printing a paste-like insulating material such as epoxy resin on the surface of the resistor 5 exposed from the first internal electrodes 3 and 4, and on the surface of the insulating substrate 2 exposed from the first internal electrodes 3 and 4 and the resistor 5, respectively. It was then cured by heating.
一対の第2内部電極7,8は、第1内部電極3,4の露出部3a,4aを含んで保護層6を覆うように薄膜形成されたCu等の電極材料からなり、これら第2内部電極7,8は、絶縁性基板2の領域2a,2b、第1内部電極3,4の露出部3a,4a、保護層6の表面全体にCu等を蒸着またはスパッタした後に、これをフォトリソ/エッチングしてパターニングされたものである。 The pair of second internal electrodes 7 and 8 is made of an electrode material such as Cu that is formed in a thin film so as to cover the protective layer 6 including the exposed portions 3a and 4a of the first internal electrodes 3 and 4. The electrodes 7 and 8 are deposited on the regions 2a and 2b of the insulating substrate 2 and the exposed portions 3a and 4a of the first internal electrodes 3 and 4 and the entire surface of the protective layer 6 by depositing or sputtering Cu or the like, and then performing photolithography/ It has been etched and patterned.
一対の外部電極9,10は、第2内部電極7,8を覆うように形成されたNiやCu等の電極材料からなり、これら外部電極9,10は、第2内部電極7,8の表面全体にNiメッキやCuメッキ等を施して形成されたものである。 The pair of external electrodes 9 and 10 is made of an electrode material such as Ni or Cu formed so as to cover the second internal electrodes 7 and 8, and these external electrodes 9 and 10 are the surfaces of the second internal electrodes 7 and 8. It is formed by applying Ni plating, Cu plating or the like to the whole.
第2内部電極7,8が第1内部電極3,4の露出部3a,4aを含んで保護層6を覆うように薄膜形成されることにより、絶縁性基板2の領域2aおよび第1内部電極3の露出部3aに対応する位置に凹部11が形成され、絶縁性基板2の領域2bおよび第1内部電極4の露出部4aに対応する位置に凹部12が形成される。これら凹部11,12は、平面視した形状が長方形状であって、絶縁性基板2の上辺から下辺まで絶縁性基板2の短辺に平行に延びるように絶縁性基板2の長手方向両端よりも内側に形成されている。 The second internal electrodes 7 and 8 are formed into a thin film so as to cover the protective layer 6 including the exposed portions 3a and 4a of the first internal electrodes 3 and 4, so that the region 2a of the insulating substrate 2 and the first internal electrodes are formed. The concave portion 11 is formed at a position corresponding to the exposed portion 3a of the insulating substrate 3, and the concave portion 12 is formed at a position corresponding to the region 2b of the insulating substrate 2 and the exposed portion 4a of the first internal electrode 4. These recesses 11 and 12 have a rectangular shape in a plan view, and are longer than both ends in the longitudinal direction of the insulating substrate 2 so as to extend parallel to the short side of the insulating substrate 2 from the upper side to the lower side of the insulating substrate 2. It is formed inside.
次に、上述のごとく構成されたチップ抵抗器1の製造方法について、図3を用いて説明する。なお、図3(b1),(b2),(b3),(b4),(b5),(b6)は、それぞれ図3(a1),(a2),(a3),(a4),(a5),(a6)のA−A線に沿う断面図である。 Next, a method of manufacturing the chip resistor 1 configured as described above will be described with reference to FIG. 3(b1), (b2), (b3), (b4), (b5), and (b6) are shown in FIGS. 3(a1), (a2), (a3), (a4), and (a5), respectively. ), (a6) are sectional views taken along the line AA.
まず、図3(a1),(b1)に示すように、絶縁性基板2が多数個取りされる大判基板2Aを準備する。この大判基板2Aには予め分割溝(図示省略)が格子状に設けられており、この分割溝によって区切られたマス目の1つ1つが1個分のチップ形成領域となる。なお、図3では1個分のチップ形成領域が代表的に示されているが、実際は多数個分のチップ形成領域に相当する後述の大判基板2Aに対して以下に説明する各工程が一括して行われる。 First, as shown in FIGS. 3A1 and 3B1, a large-sized substrate 2A from which a large number of insulating substrates 2 are taken is prepared. Dividing grooves (not shown) are previously provided in a grid pattern on the large-sized substrate 2A, and each of the cells divided by the dividing groove serves as a chip forming area. Although one chip forming area is representatively shown in FIG. 3, each step described below is collectively performed on a large-sized substrate 2A described later which actually corresponds to a large number of chip forming areas. Is done.
次に、図示を省略するが、絶縁性基板2が多数個取りされる大判基板2Aの上面全体に、Ni−Cr系等をスパッタ等して抵抗膜を薄膜形成した後に、この抵抗膜の上面全体にCu等をスパッタ等して電極膜を薄膜形成する。 Next, although not shown, after forming a thin resistance film by sputtering Ni—Cr or the like on the entire upper surface of the large-sized substrate 2A on which a large number of insulating substrates 2 are taken, the upper surface of this resistance film is formed. An electrode film is thinly formed on the whole by sputtering Cu or the like.
次に、図3(a2),(b2)に示すように、抵抗膜の上面全体に薄膜形成された電極膜をフォトリソ/エッチングして、抵抗膜の両端部上に一対の第1内部電極3,4をそれぞれ形成した後に、第1内部電極3,4から露出する抵抗膜の中央部をフォトリソ/エッチングして、ミアンダ形状の抵抗体5を形成する。 Next, as shown in FIGS. 3A2 and 3B2, the electrode film formed as a thin film on the entire upper surface of the resistance film is photolithographically/etched to form a pair of first internal electrodes 3 on both ends of the resistance film. , 4 are respectively formed, the central portions of the resistance films exposed from the first internal electrodes 3, 4 are photolithographically/etched to form meander-shaped resistors 5.
なお、図示は省略するが、抵抗膜と電極膜の形成順序を逆にすることも可能であり、絶縁性基板の長手方向両端部に一対の第1内部電極を薄膜形成した後に、この一対の第1内部電極に接続するように抵抗体を薄膜形成する製造方法であっても良い。 Although not shown, the order of forming the resistance film and the electrode film can be reversed, and after the pair of first internal electrodes are thinly formed on both ends of the insulating substrate in the longitudinal direction, the pair of first internal electrodes is formed. It may be a manufacturing method in which a resistor is formed into a thin film so as to be connected to the first internal electrode.
次に、図3(a3),(b3)に示すように、第1内部電極3,4と抵抗体5とを覆うようにエポキシ樹脂等の絶縁材料をスクリーン印刷や感光性樹脂を用いてフォトリソ形成することにより、絶縁性基板2の領域2a,2bと第1内部電極3,4の露出部3a,4aとを除いて、絶縁性基板2、第1内部電極3,4および抵抗体5の各表面に絶縁材料がそれぞれ形成されることで、厚膜からなる保護層6が得られる。この保護層形成工程により、絶縁性基板2の長手方向両端から内側に離反した位置に第1内部電極3,4の露出する露出部3a,4aが形成される。 Next, as shown in FIGS. 3(a3) and 3(b3), an insulating material such as an epoxy resin is screen-printed so as to cover the first internal electrodes 3 and 4 and the resistor 5, and photolithography is performed using a photosensitive resin. By forming the insulating substrate 2, the regions 2a and 2b of the insulating substrate 2 and the exposed portions 3a and 4a of the first internal electrodes 3 and 4 of the insulating substrate 2, the first internal electrodes 3 and 4 and the resistor 5 are removed. By forming the insulating material on each surface, the protective layer 6 made of a thick film is obtained. By this protective layer forming step, exposed portions 3a, 4a where the first internal electrodes 3, 4 are exposed are formed at positions spaced inward from both ends in the longitudinal direction of the insulating substrate 2.
次に、図3(a4),(b4),(a5),(b5)に示すように、絶縁性基板2の領域2a,2b、第1内部電極3,4の露出部3a,4aおよび保護層6を覆うようにCu等をスパッタして電極膜を薄膜形成した後に、これをフォトリソ/エッチングして一対の第2内部電極7,8を形成する。この第2内部電極形成工程により、薄膜の第2内部電極7,8が薄膜の第1内部電極3,4の露出部3a,4aを含んで厚膜の保護層6を覆うため、第1内部電極3の露出部3aと対応する位置に凹部11が形成され、第1内部電極4の露出部4aと対応する位置に凹部12が形成される。 Next, as shown in FIGS. 3(a4), (b4), (a5), and (b5), regions 2a and 2b of the insulating substrate 2, exposed portions 3a and 4a of the first internal electrodes 3 and 4 and protection. After Cu or the like is sputtered so as to cover the layer 6 to form a thin electrode film, photolithography/etching is performed to form a pair of second internal electrodes 7 and 8. By this second internal electrode forming step, the second internal electrodes 7 and 8 of the thin film cover the thick protective layer 6 including the exposed portions 3a and 4a of the first internal electrodes 3 and 4 of the thin film. The recess 11 is formed at a position corresponding to the exposed portion 3a of the electrode 3, and the recess 12 is formed at a position corresponding to the exposed portion 4a of the first internal electrode 4.
次に、第2内部電極形成工程の後に大判基板2Aを分割溝に沿ってダイシングを行い(図示省略)、図3(a6),(b6)に示すように、第2内部電極7,8をNiメッキやCuメッキ等で覆うことにより一対の外部電極9,10を形成する。これにより、図1,2に示すチップ抵抗器1が完成する。 Next, after the second internal electrode forming step, the large-sized substrate 2A is diced along the dividing grooves (not shown) to form the second internal electrodes 7 and 8 as shown in FIGS. 3(a6) and 3(b6). A pair of external electrodes 9 and 10 are formed by covering with Ni plating or Cu plating. This completes the chip resistor 1 shown in FIGS.
図4は上記のごとく構成されたチップ抵抗器1を内層した部品内臓型回路基板の断面図であり、図1に対応する部分には同一の符号を付してある。 FIG. 4 is a cross-sectional view of a component built-in type circuit board in which the chip resistor 1 configured as described above is internally layered, and the portions corresponding to FIG. 1 are denoted by the same reference numerals.
図4に示すように、チップ抵抗器1は積層回路基板等のベース基板の樹脂層20の内部に埋め込まれており、この樹脂層20の上面に配線パターン(図示省略)が設けられている。樹脂層20には2つの穴21,22が形成されており、図示左側の穴21は、第2内部電極7を覆う外部電極9の上面に達し、図示右側の穴22は第2内部電極8を覆う外部電極10の上面に達している。 As shown in FIG. 4, the chip resistor 1 is embedded in a resin layer 20 of a base substrate such as a laminated circuit substrate, and a wiring pattern (not shown) is provided on the upper surface of the resin layer 20. Two holes 21 and 22 are formed in the resin layer 20, the hole 21 on the left side in the figure reaches the upper surface of the external electrode 9 which covers the second internal electrode 7, and the hole 22 on the right side in the figure is the hole 22 in the second side. Has reached the upper surface of the external electrode 10 covering the.
これら穴21,22は樹脂層20の表面にレーザを照射することによって形成され、その内部にCu等の導電材料をメッキ処理してビア(図示省略)を形成することにより、樹脂層20の上面側の配線パターンとチップ抵抗器1の外部電極9,10とを穴21,22内のビアを介して接続させることが可能となる。 These holes 21 and 22 are formed by irradiating the surface of the resin layer 20 with a laser, and a conductive material such as Cu is plated inside the holes to form vias (not shown). It becomes possible to connect the side wiring pattern and the external electrodes 9 and 10 of the chip resistor 1 through the vias in the holes 21 and 22.
以上のように、第1実施形態例の基板内層用チップ抵抗器1では、一対の第1内部電極3,4、抵抗体5および第2内部電極7,8が薄膜形成され、抵抗体5を覆う保護層6が厚膜形成されているため、抵抗値精度が高く、温度変化による抵抗値の変動の少ないチップ抵抗器を製造することができる。また、チップ抵抗器1では、一対の第2内部電極7,8の対向間隔は一対の第1内部電極3,4の対向間隔よりも狭く形成され、第2内部電極7,8が第1内部電極3,4の露出部3a,4aを含めて保護層6を覆うように形成されているため、第2内部電極7,8を覆う外部電極9,10の表面領域を広くすることができる。 As described above, in the chip resistor 1 for a substrate inner layer of the first embodiment, the pair of first internal electrodes 3, 4, the resistor 5 and the second internal electrodes 7, 8 are formed into a thin film, and the resistor 5 is formed. Since the covering protective layer 6 is formed as a thick film, it is possible to manufacture a chip resistor having a high resistance value accuracy and a small resistance value variation due to a temperature change. Further, in the chip resistor 1, the facing interval between the pair of second internal electrodes 7 and 8 is formed to be narrower than the facing interval between the pair of first internal electrodes 3 and 4, and the second internal electrodes 7 and 8 are located inside the first internal electrode. Since it is formed so as to cover the protective layer 6 including the exposed portions 3a and 4a of the electrodes 3 and 4, it is possible to widen the surface area of the external electrodes 9 and 10 that cover the second internal electrodes 7 and 8.
そして、第1実施形態例では、保護層6によって覆われていない第1内部電極3,4の露出部3a,4aが絶縁性基板2の長手方向両端から内側に離反した位置に形成されているため、第2内部電極7,8が第1内部電極3,4の露出部3a,4aを含めて保護層6を覆うように薄膜形成されると、第1内部電極の露出部3a,4aと対応する位置に凹部11,12が形成される。このとき、第2内部電極7,8を覆う外部電極9,10の表面は凹部11,12を除いて殆ど同じ高さとなるため、少なくとも凹部11,12を除く外部電極9,10の表面をビアとの接続可能な領域として利用することができる。このように、第1実施形態例の基板内層用チップ抵抗器1では、高精度なチップ抵抗器を得るために第1,第2内部電極と抵抗体とを薄膜形成したとしても、ビアと接続可能な外部電極の領域を広く確保することができる。 In the first embodiment, the exposed portions 3a and 4a of the first internal electrodes 3 and 4 which are not covered by the protective layer 6 are formed at positions inwardly separated from both longitudinal ends of the insulating substrate 2. Therefore, when the second internal electrodes 7 and 8 are formed into a thin film so as to cover the protective layer 6 including the exposed portions 3a and 4a of the first internal electrodes 3 and 4, the exposed portions 3a and 4a of the first internal electrodes are Recesses 11 and 12 are formed at corresponding positions. At this time, the surfaces of the external electrodes 9 and 10 covering the second internal electrodes 7 and 8 have almost the same height except for the recesses 11 and 12, so that at least the surfaces of the external electrodes 9 and 10 except the recesses 11 and 12 are via-formed. It can be used as a connectable area with. As described above, in the chip resistor 1 for the substrate inner layer of the first embodiment, even if the first and second internal electrodes and the resistor are formed into a thin film in order to obtain a highly accurate chip resistor, connection with the via is performed. A wide area of possible external electrodes can be secured.
また、第1実施形態例に係る基板内層用チップ抵抗器1の製造方法によると、保護層形成工程は、第1内部電極3,4における絶縁性基板2の長手方向両端から内側に離反した位置にある露出部3a,4aを除いて薄膜の抵抗体5と第1内部電極3,4とを厚膜の保護層6で覆うように形成する工程であるため、第1内部電極3,4には保護層6によって覆われていない露出部3a,4aが形成される。そして、この露出部3a,4aと保護層6とが第2内部電極7,8で覆われる第2内部電極形成工程によって、第1内部電極の露出部3a,4aと対応する位置に凹部11,12が形成される。そうすると、外部電極9,10の表面の高さは凹部11,12を除いて殆ど同じ高さになるため、少なくとも凹部11,12を除いた外部電極9,10の表面をビアと接続可能な領域として利用することが可能になる。このように、第1実施形態例の基板内層用チップ抵抗器1の製造方法では、高精度なチップ抵抗器を得るために第1,第2内部電極と抵抗体とを薄膜形成したとしても、ビアと接続可能な外部電極の領域を広く確保することができる。 Further, according to the method for manufacturing the chip resistor 1 for a substrate inner layer according to the first embodiment, the protective layer forming step is performed in the first inner electrodes 3 and 4 at positions separated inward from both longitudinal ends of the insulating substrate 2. Since it is a step of forming the thin-film resistor 5 and the first internal electrodes 3, 4 so as to be covered with the thick-film protective layer 6 except for the exposed portions 3a, 4a in FIG. The exposed portions 3a and 4a which are not covered with the protective layer 6 are formed. Then, by the second internal electrode forming step in which the exposed portions 3a and 4a and the protective layer 6 are covered with the second internal electrodes 7 and 8, a concave portion 11 is formed at a position corresponding to the exposed portions 3a and 4a of the first internal electrode. 12 is formed. Then, the heights of the surfaces of the external electrodes 9 and 10 are almost the same except for the recesses 11 and 12, so that at least the surfaces of the external electrodes 9 and 10 excluding the recesses 11 and 12 can be connected to the vias. Can be used as. As described above, in the method for manufacturing the chip inner-layer chip resistor 1 of the first embodiment, even if the first and second internal electrodes and the resistor are formed into thin films in order to obtain a highly accurate chip resistor, It is possible to secure a wide area of the external electrode that can be connected to the via.
特に、第1実施形態例では、穴21,22が凹部11,12をそれぞれ跨いで形成可能なように、凹部11,12の幅11a,12aは穴21,22の内径21a,22aよりも狭くなるように形成されている。このため、チップ抵抗器1をベース基板の内層に埋め込んで、チップ抵抗器1の凹部11,12の直上付近にある樹脂層20にレーザを照射して穴21,22を形成したとしても、穴21,22が凹部11,12をそれぞれ跨いで形成されることになるため、外部電極とビアとの接続を確実に行うことができる。したがって、ビア用の穴を形成可能な領域(外部電極とビアとの接続可能な領域)は図4に示す広い領域E、すなわち、凹部11,12を含めた外部電極9,10の表面全体となる。このように、第1実施形態例の部品内蔵型回路基板では、高精度なチップ抵抗器を得るために第1,第2内部電極と抵抗体とを薄膜形成したとしても、凹部を含めた外部電極の表面全体をビアとの接続可能な領域とすることができるため、ビア用の穴あけ加工を容易に行うことができる。 Particularly, in the first embodiment, the widths 11a and 12a of the recesses 11 and 12 are narrower than the inner diameters 21a and 22a of the holes 21 and 22 so that the holes 21 and 22 can be formed across the recesses 11 and 12, respectively. Is formed. Therefore, even if the chip resistor 1 is embedded in the inner layer of the base substrate and the resin layer 20 located immediately above the recesses 11 and 12 of the chip resistor 1 is irradiated with a laser to form the holes 21 and 22, the holes are formed. Since the parts 21 and 22 are formed so as to straddle the recesses 11 and 12, respectively, the external electrode and the via can be reliably connected. Therefore, the area where the via hole can be formed (the area where the external electrode and the via can be connected) is the wide area E shown in FIG. 4, that is, the entire surface of the external electrodes 9 and 10 including the recesses 11 and 12. Become. As described above, in the circuit board with a built-in component of the first embodiment, even if the first and second internal electrodes and the resistor are formed into a thin film in order to obtain a highly accurate chip resistor, the external part including the concave portion is formed. Since the entire surface of the electrode can be a region that can be connected to the via, it is possible to easily perform drilling processing for the via.
なお、第1実施形態例では、第1内部電極3,4の露出部3a,4aに対応する位置に形成された凹部11,12は、絶縁性基板2の短辺に略平行に沿って絶縁性基板2の両長辺まで延びるように形成されているが(図1参照)、この構成に限られなくとも良い。以下に、本発明の第2、第3実施形態例について図5、6を参照しながら説明する。 In the first embodiment, the recesses 11 and 12 formed at the positions corresponding to the exposed portions 3a and 4a of the first internal electrodes 3 and 4 are insulated along the short sides of the insulating substrate 2 substantially in parallel. Although it is formed so as to extend to both long sides of the flexible substrate 2 (see FIG. 1), the configuration is not limited to this. The second and third embodiments of the present invention will be described below with reference to FIGS.
図5に示すように、第2実施形態例に係るチップ抵抗器31の凹部は、第1実施形態例の凹部と比較すると、絶縁性基板2の上辺または下辺の一方に向かって延びるように形成されている点で異なる。すなわち、第2実施形態例の凹部32,34は絶縁性基板2の上辺に向かって当該上辺まで延びるように形成され、凹部33,35は絶縁性基板2の下辺に向かって当該下辺まで延びるように形成されている。 As shown in FIG. 5, the recess of the chip resistor 31 according to the second embodiment is formed so as to extend toward one of the upper side and the lower side of the insulating substrate 2 as compared with the recess of the first embodiment. It is different in that it is done. That is, the recesses 32 and 34 of the second embodiment are formed so as to extend toward the upper side of the insulating substrate 2 and the recesses 33 and 35 extend toward the lower side of the insulating substrate 2 toward the lower side. Is formed in.
また、図6に示すように、第3実施形態例に係るチップ抵抗器41の凹部は、第1実施形態例の凹部と比較すると、絶縁性基板2の両長辺の手前まで延びるように形成されている点で異なる。なお、第3実施形態例では、凹部42,43が第1内部電極3,4の露出部に対応する位置にのみ形成される構成になっているが、これに限られず、凹部42,43が第1内部電極3,4の露出部および絶縁性基板2の領域に対応する位置まで形成される構成であっても良い。 Further, as shown in FIG. 6, the recess of the chip resistor 41 according to the third embodiment is formed so as to extend to the front of both long sides of the insulating substrate 2 as compared with the recess of the first embodiment. It is different in that it is done. In addition, in the third embodiment, the recesses 42, 43 are formed only at the positions corresponding to the exposed portions of the first internal electrodes 3, 4, but the invention is not limited to this, and the recesses 42, 43 may be formed. The structure may be formed up to the positions corresponding to the exposed portions of the first internal electrodes 3 and 4 and the region of the insulating substrate 2.
このように、第2,第3実施形態例のように凹部を形成した場合であっても、第1実施形態例の奏する効果、すなわち、電極や抵抗体を薄膜形成しても外部電極とビアとの接続が容易なチップ抵抗器を提供すること、このようなチップ抵抗器の製造方法を提供すること、および、ビア用の穴あけ加工が容易な部品内蔵型回路基板を提供することができる。 In this way, even when the recess is formed as in the second and third embodiments, the effect of the first embodiment, that is, even if the electrodes and resistors are formed into thin films, the external electrodes and the vias are formed. It is possible to provide a chip resistor that can be easily connected to, a method of manufacturing such a chip resistor, and a component-embedded circuit board that can be easily drilled for vias.
なお、図示は省略するが、第1〜第3実施形態例の凹部は平面視長方形状に形成されているが、この構成に限られず、平面視円状や楕円状に形成されている構成であっても良い。 Although not shown, the recesses of the first to third embodiments are formed in a rectangular shape in plan view, but the configuration is not limited to this, and may be formed in a circular shape or an elliptical shape in plan view. It may be.
1,31,41 基板内層用チップ抵抗器
2 絶縁性基板
2A 大判基板
3,4 第1内部電極
5 抵抗体
6 保護層
7,8 第2内部電極
9,10 外部電極
11,12,32〜35,42,43 凹部
20 樹脂層
21,22 穴
1,31,41 Chip resistor for substrate inner layer 2 Insulating substrate 2A Large-sized substrate 3,4 First internal electrode 5 Resistor 6 Protective layer 7,8 Second internal electrode 9,10 External electrode 11,12,32-35 , 42, 43 recesses 20 resin layers 21, 22 holes
Claims (1)
前記チップ抵抗器が、直方体形状の絶縁性基板と、前記絶縁性基板における長手方向両端部に薄膜形成された一対の第1内部電極と、前記一対の第1内部電極に接続するように薄膜形成された抵抗体と、少なくとも前記抵抗体を覆うように厚膜形成された保護層と、前記一対の第1内部電極の対向間隔よりも狭い対向間隔となるように薄膜形成された一対の第2内部電極と、前記第2内部電極を覆うようにメッキ形成された外部電極とを備え、
前記保護層が前記抵抗体と前記第1内部電極とを覆うように形成されていると共に、この第1内部電極における前記絶縁性基板の長手方向両端から内側に離反した位置に前記保護層によって覆われていない露出部が形成されており、
前記第2内部電極が前記露出部を含んで前記保護層を覆うように形成されていることにより、前記露出部と対応する位置に凹部が形成され、
前記凹部を跨いで前記外部電極と接続するビアを前記ベース基板に形成可能であり、
前記凹部の幅は前記ビアの内径よりも狭くなるように形成されていることを特徴とする部品内蔵型回路基板。 In a component built-in type circuit board in which a chip resistor is embedded in the inner layer of a base board made of an insulating resin layer,
The chip resistor is formed into a rectangular parallelepiped insulating substrate, a pair of first internal electrodes formed into thin films at both ends in the longitudinal direction of the insulating substrate, and a thin film formed to be connected to the pair of first internal electrodes. Resistor, a protective layer formed as a thick film so as to cover at least the resistor, and a pair of second thin films formed so as to have an opposing interval narrower than the opposing interval between the pair of first internal electrodes. An internal electrode and an external electrode formed by plating so as to cover the second internal electrode,
The protective layer is formed so as to cover the resistor and the first internal electrode, and the protective layer covers the first internal electrode at positions separated from both ends in the longitudinal direction of the insulating substrate. An exposed part that is not exposed is formed,
Since the second internal electrode is formed so as to cover the protective layer including the exposed portion, a recess is formed at a position corresponding to the exposed portion,
Vias connecting to the external electrodes can be formed in the base substrate across the recesses,
A circuit board with a built-in component, wherein the width of the recess is formed to be narrower than the inner diameter of the via.
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