JP6674833B2 - Chip resistor and component built-in circuit board - Google Patents
Chip resistor and component built-in circuit board Download PDFInfo
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- JP6674833B2 JP6674833B2 JP2016085997A JP2016085997A JP6674833B2 JP 6674833 B2 JP6674833 B2 JP 6674833B2 JP 2016085997 A JP2016085997 A JP 2016085997A JP 2016085997 A JP2016085997 A JP 2016085997A JP 6674833 B2 JP6674833 B2 JP 6674833B2
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- 239000000758 substrate Substances 0.000 claims description 63
- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 230000001681 protective effect Effects 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000007747 plating Methods 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 6
- 238000007650 screen-printing Methods 0.000 description 6
- 238000009966 trimming Methods 0.000 description 6
- 238000001035 drying Methods 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 4
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 3
- 239000005751 Copper oxide Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 229910000431 copper oxide Inorganic materials 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- Non-Adjustable Resistors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は、積層回路基板等に内蔵される部品内蔵型として用いて好適なチップ抵抗器と、そのようなチップ抵抗器が絶縁性の樹脂層に埋め込まれている部品内蔵型回路基板に関するものである。 The present invention relates to a chip resistor suitable for use as a component built-in type built in a laminated circuit board and the like, and to a component built-in type circuit board in which such a chip resistor is embedded in an insulating resin layer. is there.
一般的にチップ抵抗器は、直方体形状の絶縁基板と、絶縁基板の表面における長手方向両端部に設けられた一対の表電極と、これら両表電極間に設けられた抵抗体と、抵抗体を覆う絶縁性の保護膜と、前記絶縁基板の裏面における長手方向両端部に設けられた一対の裏電極と、表電極と裏電極を導通する一対の端面電極と、露出する表電極と裏電極および端面電極を覆う一対の外部電極等によって主に構成されており、抵抗体には抵抗値調整のためのトリミングが施されている。 Generally, a chip resistor includes a rectangular parallelepiped-shaped insulating substrate, a pair of front electrodes provided at both ends in the longitudinal direction on the surface of the insulating substrate, a resistor provided between the front and rear electrodes, and a resistor. An insulating protective film to cover, a pair of back electrodes provided at both ends in the longitudinal direction on the back surface of the insulating substrate, a pair of end surface electrodes that conduct the front electrode and the back electrode, an exposed front electrode and a back electrode, and It is mainly composed of a pair of external electrodes covering the end face electrodes, and the resistor is trimmed for resistance adjustment.
近年、電子機器の小型・軽量化や回路構成の複雑化に伴って、このようなチップ抵抗器を回路基板上に面実装して使用するだけでなく、積層回路基板等の樹脂層の内部に埋め込んで内層型のチップ抵抗器として使用する場合が生じている。その場合、樹脂層表面の配線パターンと内部のチップ抵抗器はビアホールを介して接続されるため、ビアホールに接続される外部電極の表面は広く且つ平坦であることが望ましく、かかる要望に対応した構成例として、表面に広く且つ平坦な外部電極を有するようにしたチップ抵抗器が知られている（例えば、特許文献１参照）。 In recent years, as electronic devices have become smaller and lighter and circuit configurations have become more complex, not only are these chip resistors surface-mounted and used on circuit boards, but they are also used inside resin layers such as laminated circuit boards. There is a case where an embedded chip resistor is used as an inner layer type chip resistor. In this case, since the wiring pattern on the resin layer surface and the internal chip resistor are connected via the via hole, the surface of the external electrode connected to the via hole is desirably wide and flat. As an example, a chip resistor having a wide and flat external electrode on its surface is known (for example, see Patent Document 1).
特許文献１に開示されたチップ抵抗器では、一対の表電極上にそれぞれ第２表電極を形成すると共に、これら第２表電極を保護膜の両端部から上面に達する位置まで延ばすことにより、第２表電極を覆うように形成された外部電極の面積が大きくなっているため、ベース基板の樹脂層にレーザ光を照射してビアホールを形成する際に、ビアホールの形成位置が正規の位置に対して多少ずれたとしても、チップ抵抗器の外部電極とビアホールを確実に接続することが可能になる。 In the chip resistor disclosed in Patent Literature 1, a second front electrode is formed on each of a pair of front electrodes, and the second front electrode is extended from both ends of the protective film to a position reaching the upper surface. (2) Since the area of the external electrode formed so as to cover the front electrode is large, when the laser beam is applied to the resin layer of the base substrate to form the via hole, the via hole is formed at a position that is normal to the regular position. Even if the position is slightly shifted, the external electrode of the chip resistor and the via hole can be reliably connected.
ところで、この種のチップ抵抗器においては、互いに導通される外部電極とビアホールの材料は同じであることが好ましく、例えば、レーザ光の照射によって形成される連通孔内にＣｕメッキを施してビアホールとする場合、チップ抵抗器の外部電極もＣｕメッキによって形成するようにしている。その場合、銅（Ｃｕ）は空気中に曝されると酸化銅の被膜を形成するため、外部電極の表面に酸化銅が残ったままビアホールが形成されると、外部電極とビアホールの接続信頼性が著しく低下してしまう。 By the way, in this type of chip resistor, it is preferable that the material of the external electrode and the via hole that are conducted to each other be the same, for example, Cu plating is applied to the inside of the communication hole formed by laser light irradiation, and In this case, the external electrodes of the chip resistor are also formed by Cu plating. In this case, when copper (Cu) is exposed to air, a copper oxide film is formed. Therefore, if a via hole is formed with copper oxide remaining on the surface of the external electrode, the connection reliability between the external electrode and the via hole is reduced. Is significantly reduced.
このような理由により、従来は、チップ抵抗器を塩酸等の洗浄液に浸漬することで、外部電極の表面に形成された酸化銅を除去するようにしているが、かかる洗浄時に絶縁性樹脂からなる保護膜が洗浄液によって損傷してしまい、結果的に保護膜の耐湿性が悪くなってしまうという問題があった。 For this reason, conventionally, the chip resistor is immersed in a cleaning solution such as hydrochloric acid to remove the copper oxide formed on the surface of the external electrode. There has been a problem that the protective film is damaged by the cleaning solution, and as a result, the moisture resistance of the protective film deteriorates.
本発明は、このような従来技術の実情に鑑みてなされたもので、その第１の目的は、表面に大きな外部電極を形成できると共に耐湿性の劣化を防止できるチップ抵抗器を提供することにあり、第２の目的は、チップ抵抗器の外部電極とビアホールとを簡単かつ確実に接続することができる部品内蔵型回路基板を提供することにある。 SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances of the related art, and a first object of the present invention is to provide a chip resistor capable of forming a large external electrode on a surface and preventing deterioration of moisture resistance. A second object is to provide a component built-in type circuit board which can easily and surely connect an external electrode of a chip resistor and a via hole.
上記第１の目的を達成するために、本発明のチップ抵抗器は、直方体形状の絶縁基板と、この絶縁基板の表面に所定間隔を存して設けられた一対の表電極と、前記絶縁基板の表面に設けられて一対の前記表電極を橋絡する抵抗体と、前記抵抗体を覆う絶縁性の保護膜と、一対の前記表電極の一方とのみ接続されると共に、他方の前記表電極寄りの一端部を除いた領域の前記保護膜を覆う補助電極と、前記絶縁基板の裏面における前記表電極と対応する位置に設けられた一対の裏電極と、前記絶縁基板の両端面に設けられて対応する前記表電極と前記裏電極を導通する一対の端面電極と、少なくとも前記端面電極と前記裏電極の外表面を覆う一対の外部電極とを備え、一対の前記外部電極の一方は前記補助電極の外表面を覆っているという構成にした。 In order to achieve the first object, a chip resistor according to the present invention includes a rectangular parallelepiped insulating substrate, a pair of front electrodes provided at predetermined intervals on a surface of the insulating substrate, A resistor provided on the surface of the pair and bridging the pair of front electrodes, an insulating protective film covering the resistor, and only one of the pair of front electrodes connected to the other of the front electrodes; An auxiliary electrode that covers the protective film in a region excluding a near end, a pair of back electrodes provided at positions corresponding to the front electrode on the back surface of the insulating substrate, and provided on both end surfaces of the insulating substrate. A pair of end electrodes for electrically connecting the corresponding front electrode and the back electrode, and a pair of external electrodes covering at least the outer surfaces of the end electrodes and the back electrode, one of the pair of external electrodes being the auxiliary Configuration that covers the outer surface of the electrode It was.
このように構成されたチップ抵抗器では、保護膜の一端部を除いて抵抗体を含むそれ以外の領域を補助電極が覆っており、この補助電極が一対の表電極の一方とのみ接続されているため、補助電極を覆う広くて平坦な外部電極を形成することができ、積層回路基板等の内層に実装するに際して、外部電極とビアホールの接続を容易に行うことができる。しかも、補助電極が他方の表電極を覆う位置まで延びているため、外部電極の表面に形成された酸化物を除去する洗浄処理が行われたとしても、抵抗体を覆っている部分の保護膜が洗浄液によってダメージを受けにくくなり、保護膜の損傷に起因する耐湿性の劣化を防止することができる。さらに、電流印加時に抵抗体から発生する熱が補助電極によって放熱されるため、放熱性に優れたチップ抵抗器を実現することができる。 In the chip resistor configured as above, the auxiliary electrode covers the other area including the resistor except for one end of the protective film, and the auxiliary electrode is connected to only one of the pair of front electrodes. Therefore, a wide and flat external electrode covering the auxiliary electrode can be formed, and when the external electrode is mounted on an inner layer such as a laminated circuit board, connection between the external electrode and the via hole can be easily performed. Moreover, since the auxiliary electrode extends to a position covering the other front electrode, even if a cleaning process for removing the oxide formed on the surface of the external electrode is performed, the protective film covering the resistor is protected. Is less likely to be damaged by the cleaning liquid, and deterioration of the moisture resistance due to damage to the protective film can be prevented. Furthermore, since the heat generated from the resistor when the current is applied is radiated by the auxiliary electrode, a chip resistor excellent in heat radiation can be realized.
上記の構成において、他方の外部電極が補助電極に接続していない方の表電極の外表面を覆っており、一対の外部電極が外表面の接続層と内部のバリア層とを有していると、ベース基板の樹脂層にレーザ光を照射して補助電極上の外部電極に達するビアホールを形成する際に、外部電極のバリア層がレーザ光をブロックして補助電極や表電極まで到達しないように阻止するため、ビアホールを介しての耐湿性の劣化を防止することができる。 In the above configuration, the other external electrode covers the outer surface of the front electrode that is not connected to the auxiliary electrode, and the pair of external electrodes has a connection layer on the outer surface and an internal barrier layer. When forming a via hole reaching the external electrode on the auxiliary electrode by irradiating the resin layer of the base substrate with the laser light, the barrier layer of the external electrode blocks the laser light so that it does not reach the auxiliary electrode or the front electrode. , It is possible to prevent deterioration of the moisture resistance via the via hole.
また、上記第２の目的を達成するために、本発明の部品内蔵型回路基板は、絶縁性の樹脂層からなるベース基板の内層にチップ抵抗器が埋め込まれている部品内蔵型回路基板において、前記チップ抵抗器が、直方体形状の絶縁基板と、この絶縁基板の表面に所定間隔を存して設けられた一対の表電極と、前記絶縁基板の表面に設けられて一対の前記表電極を橋絡する抵抗体と、前記抵抗体を覆う絶縁性の保護膜と、一対の前記表電極の一方とのみ接続されると共に、他方の前記表電極寄りの一端部を除いた領域の前記保護膜を覆う補助電極と、前記絶縁基板の裏面における前記表電極と対応する位置に設けられた一対の裏電極と、前記絶縁基板の両端面に設けられて対応する前記表電極と前記裏電極を導通する一対の端面電極と、前記表電極と前記裏電極と前記端面電極および前記補助電極の外表面を覆う一対の外部電極とを備えると共に、一対の前記外部電極のうちの一方のみが前記補助電極の外表面を覆っており、前記ベース基板に、いずれか一方面から前記補助電極を覆う前記外部電極に達するビアホールと、いずれか他方面から前記補助電極に導通しない方の前記裏電極を覆う前記外部電極に達するビアホールとが設けられているという構成にした。 Further, in order to achieve the second object, a component-embedded circuit board of the present invention is a component-embedded circuit board in which a chip resistor is embedded in an inner layer of a base substrate made of an insulating resin layer. The chip resistor includes a rectangular parallelepiped-shaped insulating substrate, a pair of front electrodes provided on the surface of the insulating substrate at a predetermined interval, and a pair of front electrodes provided on the surface of the insulating substrate. And the protective film covering the resistor, and the protective film in a region that is connected to only one of the pair of front electrodes and excludes one end near the other front electrode. Auxiliary electrodes to be covered, a pair of back electrodes provided at positions corresponding to the front electrodes on the back surface of the insulating substrate, and electrical connections between the corresponding front electrodes and the back electrodes provided at both end surfaces of the insulating substrate. A pair of end electrodes and the front electrode Provided with a pair of external electrodes covering the outer surface of the end surface electrode and the auxiliary electrode and the back electrode, only one of the pair of the external electrodes covers the outer surface of the auxiliary electrode, the base substrate A via hole reaching the external electrode that covers the auxiliary electrode from any one surface, and a via hole reaching the external electrode that covers the back electrode that does not conduct to the auxiliary electrode from any other surface. Was configured.
このように構成された部品内蔵型回路基板では、ベース基板の樹脂層に埋め込まれたチップ抵抗器が保護膜の一端部を除いて抵抗体を含むそれ以外の領域を覆う補助電極を有しており、この補助電極が絶縁基板上に設けられた一対の表電極の一方とのみ接続されているため、補助電極を覆う広くて平坦な外部電極を形成することができる。したがって、ベース基板の樹脂層に内層されたチップ抵抗器の表裏両面の外部電極に対してビアホールを簡単かつ確実に接続させることができる。しかも、補助電極が他方の表電極を覆う位置まで延びているため、外部電極の表面に形成された酸化物を除去する洗浄処理が行われたとしても、抵抗体を覆う保護膜が洗浄液によってダメージを受けにくくなり、保護膜の損傷に起因する耐湿性の劣化を防止することができる。 In the component built-in type circuit board configured as described above, the chip resistor embedded in the resin layer of the base board has an auxiliary electrode that covers the other area including the resistor except for one end of the protective film. Since the auxiliary electrode is connected to only one of the pair of front electrodes provided on the insulating substrate, a wide and flat external electrode covering the auxiliary electrode can be formed. Therefore, the via holes can be easily and reliably connected to the external electrodes on both the front and back surfaces of the chip resistor provided inside the resin layer of the base substrate. In addition, since the auxiliary electrode extends to a position covering the other front electrode, even if a cleaning process for removing the oxide formed on the surface of the external electrode is performed, the protective film covering the resistor is damaged by the cleaning liquid. Therefore, deterioration of the moisture resistance due to damage to the protective film can be prevented.
本発明によれば、表面に大きな外部電極を形成できると共に耐湿性の劣化を防止できるチップ抵抗器を提供することが可能であり、また、チップ抵抗器の外部電極とビアホールとを簡単かつ確実に接続することができる部品内蔵型回路基板を提供することが可能となる。 According to the present invention, it is possible to provide a chip resistor capable of forming a large external electrode on the surface and preventing the deterioration of moisture resistance, and to easily and reliably connect the external electrode and the via hole of the chip resistor. It is possible to provide a component built-in type circuit board that can be connected.
発明の実施の形態について図面を参照して説明すると、図１に示すように、本発明の実施形態例に係るチップ抵抗器１は、直方体形状の絶縁基板２と、絶縁基板２の表面における長手方向両端部に所定間隔を存して形成された第１および第２表電極３ａ，３ｂと、これら両表電極３ａ，３ｂに接続するように形成された抵抗体４と、抵抗体４の全体を覆うように形成されたアンダーコート層５と、両表電極３ａ，３ｂの一部とアンダーコート層５の全体を覆うように形成されたオーバーコート層６と、オーバーコート層６の一端部を除いて抵抗体４を含むそれ以外の領域を覆うように形成されて図示右側の第１表電極３ａとのみ接続する補助電極７と、絶縁基板２の裏面における長手方向両端部に所定間隔を存して形成された第１および第２裏電極８ａ，８ｂと、絶縁基板２の長手方向一端面に形成されて第１表電極３ａと第１裏電極８ａを導通する第１端面電極９ａと、絶縁基板２の長手方向他端面に形成されて図示左側の第２表電極３ｂと第２裏電極８ｂを導通する第２端面電極９ｂと、補助電極７と第１表電極３ａの露出部と第１端面電極９ａおよび第１裏電極８ａを覆う第１外部電極１０ａと、第２表電極３ｂの露出部と第２端面電極９ｂおよび第２裏電極８ｂを覆う第２外部電極１０ｂとによって構成されている。 An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a chip resistor 1 according to an embodiment of the present invention includes a rectangular parallelepiped-shaped insulating substrate 2 and a longitudinally extending surface of the insulating substrate 2. First and second front electrodes 3a, 3b formed at predetermined ends at both ends in the direction, a resistor 4 formed to be connected to both front electrodes 3a, 3b, and the entire resistor 4 , An overcoat layer 6 formed to cover a part of both front electrodes 3a and 3b and the entire undercoat layer 5, and one end of the overcoat layer 6. Except for the auxiliary electrode 7 formed to cover the other area including the resistor 4 and connected only to the first front electrode 3a on the right side in the figure, a predetermined interval is provided between both ends in the longitudinal direction on the back surface of the insulating substrate 2. First and second formed Electrodes 8a and 8b, a first end surface electrode 9a formed on one end surface of the insulating substrate 2 in the longitudinal direction for conducting the first front electrode 3a and the first back electrode 8a, and a second end surface of the insulating substrate 2 in the longitudinal direction. A second end face electrode 9b for conducting the second front electrode 3b and the second back electrode 8b on the left side in the drawing, an auxiliary electrode 7, an exposed portion of the first front electrode 3a, the first end face electrode 9a and the first back electrode 8a. It comprises a first external electrode 10a to cover, an exposed portion of the second front electrode 3b, and a second external electrode 10b to cover the second end face electrode 9b and the second back electrode 8b.
絶縁基板２はセラミックス基板からなり、この絶縁基板２は後述する大判基板を縦横に延びる一次分割溝と二次分割溝に沿って分割して多数個取りされたものである。 The insulating substrate 2 is made of a ceramic substrate. The insulating substrate 2 is obtained by dividing a large-sized substrate, which will be described later, along a primary division groove and a secondary division groove extending in the vertical and horizontal directions.
第１および第２表電極３ａ，３ｂと第１および第２裏電極８ａ，８ｂはいずれもＡｇ系ペーストをスクリーン印刷して乾燥・焼成させたものであり、図示右側の第１表電極３ａと第１裏電極８ａおよび図示左側の第２表電極３ｂと第２裏電極８ｂは絶縁基板２を挟んだ対向位置に形成されている。 Each of the first and second front electrodes 3a and 3b and the first and second back electrodes 8a and 8b is formed by screen-printing an Ag-based paste and drying and firing the same. The first back electrode 8a, the second front electrode 3b on the left side in the figure, and the second back electrode 8b are formed at opposing positions with the insulating substrate 2 interposed therebetween.
抵抗体４は酸化ルテニウム等の抵抗ペーストをスクリーン印刷して乾燥・焼成させたものであり、この抵抗体４には抵抗値を調整するためのトリミング溝Ｔが形成されている。 The resistor 4 is formed by screen-printing a resistor paste such as ruthenium oxide and drying and firing the resistor. The resistor 4 has a trimming groove T for adjusting the resistance value.
アンダーコート層５はガラスペーストをスクリーン印刷して乾燥・焼成させたものであり、このアンダーコート層５の上からレーザ光を照射することでトリミング溝Ｔが形成される。オーバーコート層６はエポキシ樹脂系ペーストをスクリーン印刷して加熱硬化させたものであり、これらアンダーコート層５とオーバーコート層６によって２層構造の保護膜が構成されている。オーバーコート層６はトリミング溝Ｔを含めたアンダーコート層５の全体と第１および第２表電極３ａ，３ｂの一部を覆っているが、図示右側の第１表電極３ａの大部分はオーバーコート層６によって覆われていない接続部となっている。 The undercoat layer 5 is formed by screen printing a glass paste and drying and baking the glass paste. By irradiating a laser beam from above the undercoat layer 5, a trimming groove T is formed. The overcoat layer 6 is obtained by screen-printing an epoxy resin-based paste and curing by heating. The undercoat layer 5 and the overcoat layer 6 constitute a two-layer protective film. The overcoat layer 6 covers the entire undercoat layer 5 including the trimming groove T and a part of the first and second front electrodes 3a and 3b. The connection portion is not covered by the coat layer 6.
補助電極７はＡｇを含有する樹脂ペーストをスクリーン印刷して加熱硬化させたものであり、この補助電極７は図示右側の第１表電極３ａと接続しているが、図示左側の第２表電極３ｂとは接続されていない。すなわち、補助電極７は、第２表電極３ｂの真上に位置するオーバーコート層６の上面端部から第１表電極３ａの前記接続部に至る範囲に亘って形成されている。 The auxiliary electrode 7 is formed by screen-printing a resin paste containing Ag and heat-curing. The auxiliary electrode 7 is connected to the first front electrode 3a on the right side in the drawing, but is connected to the second front electrode 3a on the left side in the drawing. 3b is not connected. That is, the auxiliary electrode 7 is formed over a range from the upper surface end of the overcoat layer 6 located directly above the second front electrode 3b to the connection portion of the first front electrode 3a.
第１端面電極９ａと第２端面電極９ｂはいずれも絶縁基板２の端面にＮｉ／Ｃｒ等をスパッタリングして形成されたものであり、補助電極７と第１裏電極８ａは第１端面電極９ａを介して導通され、第２表電極３ｂと第２裏電極８ｂは第２端面電極９ｂを介して導通されている。 The first end face electrode 9a and the second end face electrode 9b are both formed by sputtering Ni / Cr or the like on the end face of the insulating substrate 2, and the auxiliary electrode 7 and the first back face electrode 8a are formed by the first end face electrode 9a. And the second front electrode 3b and the second back electrode 8b are electrically connected via the second end face electrode 9b.
第１外部電極１０ａと第２外部電極１０ｂはいずれも、Ｎｉメッキからなる内部のバリア層とＣｕメッキからなる外表面の接続層とを有する２層構造となっており、後述するように、チップ抵抗器１が部品内蔵型回路基板の樹脂層に埋め込まれた際に、これら第１外部電極１０ａと第２外部電極１０ｂの接続層に対してビアホールが接続されるようになっている。 Each of the first external electrode 10a and the second external electrode 10b has a two-layer structure having an inner barrier layer made of Ni plating and a connection layer on the outer surface made of Cu plating. When the resistor 1 is embedded in the resin layer of the circuit board with a built-in component, via holes are connected to the connection layer between the first external electrode 10a and the second external electrode 10b.
次に、上述の如く構成されたチップ抵抗器１の製造方法について、図２と図３を参照しながら説明する。なお、図２（ａ）〜（ｆ）は大判基板を表面的に見た平面図、図３（ａ）〜（ｆ）は図２（ａ）〜（ｆ）のＸ１−Ｘ１線に沿う断面図をそれぞれ示している。 Next, a method of manufacturing the chip resistor 1 configured as described above will be described with reference to FIGS. 2 (a) to 2 (f) are plan views of the large-sized substrate as viewed from the surface, and FIGS. 3 (a) to 3 (f) are cross sections along the line X1-X1 in FIGS. 2 (a) to 2 (f). Each figure is shown.
まず、図２（ａ）と図３（ａ）に示すように、絶縁基板２が多数個取りされる大判基板２０を準備する。この大判基板２０の表裏両面には予め一次分割溝２１と二次分割溝２２が格子状に設けられており、両分割溝２１，２２によって区切られたマス目の１つ１つが１個分のチップ形成領域となる。なお、図２では複数個分のチップ形成領域が代表的に示されているが、実際は多数個分のチップ形成領域に相当する大判基板２０に対して以下に説明する各工程が一括して行われる。 First, as shown in FIGS. 2A and 3A, a large-sized substrate 20 from which a large number of insulating substrates 2 are taken is prepared. A primary division groove 21 and a secondary division groove 22 are previously provided in a grid pattern on both the front and back surfaces of the large-format substrate 20, and each of the squares divided by the two division grooves 21 and 22 corresponds to one cell. It becomes a chip formation area. In FIG. 2, a plurality of chip forming regions are representatively shown, but in practice, the following steps are collectively performed on a large-sized substrate 20 corresponding to a large number of chip forming regions. Will be
すなわち、図２（ｂ）と図３（ｂ）に示すように、大判基板２０の表面にＡｇ系ペーストを印刷して乾燥・焼成させることにより、大判基板２０の表面に一次分割溝２１に跨るように複数の表電極３を形成すると共に、それに前後して大判基板２０の裏面にＡｇ系ペーストをスクリーン印刷して乾燥・焼成させることにより、大判基板２０の裏面に一次分割溝２１に跨るように複数の裏電極８を形成する。 That is, as shown in FIG. 2B and FIG. 3B, the Ag-based paste is printed on the surface of the large-sized substrate 20 and dried and baked, so that the surface of the large-sized substrate 20 extends over the primary division grooves 21. The plurality of front electrodes 3 are formed as described above, and before and after the front electrodes 3, an Ag-based paste is screen-printed on the back surface of the large-sized substrate 20 and dried and fired, so that the front surface of the large-sized substrate 20 spans the primary division grooves 21. Then, a plurality of back electrodes 8 are formed.
次に、大判基板２０の表面に酸化ルテニウム等の抵抗体ペーストをスクリーン印刷した後、これを乾燥・焼成することにより、図２（ｃ）と図３（ｃ）に示すように、対をなす表電極３に接続する抵抗体４を形成する。 Next, after a resistor paste such as ruthenium oxide is screen-printed on the surface of the large-sized substrate 20, the paste is dried and fired to form a pair as shown in FIG. 2 (c) and FIG. 3 (c). The resistor 4 connected to the front electrode 3 is formed.
次に、大判基板２０の表面にガラスペーストをスクリーン印刷して乾燥・焼成することにより、図２（ｄ）と図３（ｄ）に示すように、抵抗体４を覆うアンダーコート層５を形成した後、このアンダーコート層５の上からトリミング溝（図示省略）を形成して抵抗値を調整する。 Next, as shown in FIG. 2D and FIG. 3D, an undercoat layer 5 covering the resistor 4 is formed by screen-printing a glass paste on the surface of the large-sized substrate 20 and drying and firing the paste. After that, a trimming groove (not shown) is formed from above the undercoat layer 5 to adjust the resistance value.
しかる後、アンダーコート層５を覆うようにエポキシ樹脂系ペーストをスクリーン印刷して加熱硬化することにより、図２（ｅ）と図３（ｅ）に示すように、アンダーコート層５とオーバーコート層６の２層構造からなる保護膜を形成する。その際、抵抗体４と接続している表電極３の端部はオーバーコート層６によって覆われるが、一次分割溝２１を跨ぐ位置近傍の表電極３はオーバーコート層６に覆われずに露出している。 Thereafter, an epoxy resin-based paste is screen-printed so as to cover the undercoat layer 5 and heat-cured, thereby forming the undercoat layer 5 and the overcoat layer as shown in FIGS. 2 (e) and 3 (e). 6, a protective film having a two-layer structure is formed. At this time, the end of the front electrode 3 connected to the resistor 4 is covered with the overcoat layer 6, but the front electrode 3 near the position across the primary division groove 21 is exposed without being covered by the overcoat layer 6. doing.
次に、オーバーコート層６の上からＡｇを含有する樹脂ペーストをスクリーン印刷して加熱硬化することにより、図２（ｆ）と図３（ｆ）に示すように、オーバーコート層６の一端部から他端側の表電極３まで覆う補助電極７を形成する。その結果、チップ形成領域内でオーバーコート層６を介して露出する一対の表電極３のうち、一方の表電極３とのみ接続してオーバーコート層６の大部分を覆う補助電極７が形成されるが、この補助電極７は他方の表電極３から離間して接続されていない。 Next, a resin paste containing Ag is screen-printed from above the overcoat layer 6 and heat-cured to form one end of the overcoat layer 6 as shown in FIGS. 2 (f) and 3 (f). The auxiliary electrode 7 is formed to cover from to the front electrode 3 on the other end side. As a result, among the pair of front electrodes 3 exposed through the overcoat layer 6 in the chip formation region, the auxiliary electrode 7 that is connected to only one of the front electrodes 3 and covers most of the overcoat layer 6 is formed. However, the auxiliary electrode 7 is not connected separately from the other front electrode 3.
以下、図示は省略するが、大判基板２０を一次分割溝２１に沿って短冊状に一次分割して短冊状基板を得ることにより、表電極３が第１表電極３ａと第２表電極３ｂに２分されると共に、裏電極８が第１裏電極８ａと第２裏電極８ｂに２分される。しかる後、この短冊状基板の両方の分割面にＮｉ／Ｃｒをスパッタリングすることにより、第１表電極３ａと第１裏電極８ａを導通する第１端面電極９ａと、第２表電極３ｂと第２裏電極８ｂを導通する第２端面電極９ｂをそれぞれ形成する。 Although not shown in the drawings, the large-sized substrate 20 is firstly divided into strips along the primary division grooves 21 to obtain a strip-shaped substrate, so that the front electrode 3 becomes the first front electrode 3a and the second front electrode 3b. At the same time, the back electrode 8 is divided into a first back electrode 8a and a second back electrode 8b. Thereafter, by sputtering Ni / Cr on both divided surfaces of the strip-shaped substrate, a first end surface electrode 9a for conducting the first front electrode 3a and the first back electrode 8a, a second front electrode 3b and the second front electrode 3b. A second end face electrode 9b for conducting the second back electrode 8b is formed.
次に、短冊状基板を二次分割溝２２に沿って二次分割してチップ抵抗器１と同等の大きさの個片（チップ単体）を得た後、各チップ単体の補助電極７と表電極３ａ，３ｂと端面電極９ａ，９ｂと裏電極８ａ，８ｂに対してＮｉメッキとＣｕメッキを順次施すことにより、第１外部電極１０ａと第２外部電極１０ｂを備えたチップ抵抗器１が完成する。 Next, the strip-shaped substrate is secondarily divided along the secondary division grooves 22 to obtain individual pieces (single chips) having the same size as the chip resistor 1. The chip resistor 1 having the first external electrode 10a and the second external electrode 10b is completed by sequentially performing Ni plating and Cu plating on the electrodes 3a and 3b, the end face electrodes 9a and 9b, and the back electrodes 8a and 8b. I do.
図４は上記のごとく構成されたチップ抵抗器１を内層した部品内蔵型回路基板の断面図であり、図１に対応する部分には同一符号を付してある。 FIG. 4 is a cross-sectional view of a component built-in type circuit board in which the chip resistor 1 configured as described above is layered, and portions corresponding to FIG. 1 are denoted by the same reference numerals.
図４に示すように、チップ抵抗器１は積層回路基板等のベース基板の樹脂層３０の内部に埋め込まれており、この樹脂層３０の上面と下面にはそれぞれ配線パターン３１，３２が設けられている。樹脂層３０には２つビアホール３３，３４が形成されており、一方のビアホール３３は第１外部電極１０ａの上面に達しており、他方のビアホール３４は第２外部電極１０ｂの下面に達している。 As shown in FIG. 4, the chip resistor 1 is embedded in a resin layer 30 of a base substrate such as a laminated circuit board. Wiring patterns 31 and 32 are provided on the upper and lower surfaces of the resin layer 30, respectively. ing. Two via holes 33, 34 are formed in the resin layer 30, one via hole 33 reaches the upper surface of the first external electrode 10a, and the other via hole 34 reaches the lower surface of the second external electrode 10b. .
これらビアホール３３，３４は、樹脂層３０にレーザ光を照射して第１および第２外部電極１０ａ，１０ｂに達する連通孔を形成した後、その連通孔の内部にＣｕメッキを施すことによって形成されたものであり、一方のビアホール３３を介して樹脂層３０の上面側の配線パターン３１とチップ抵抗器１の第１外部電極１０ａが接続され、他方のビアホール３４を介して樹脂層３０の下面側の配線パターン３２とチップ抵抗器１の第２外部電極１０ｂが接続されている。 The via holes 33 and 34 are formed by irradiating the resin layer 30 with a laser beam to form communication holes reaching the first and second external electrodes 10a and 10b, and then applying Cu plating to the inside of the communication holes. The wiring pattern 31 on the upper surface side of the resin layer 30 and the first external electrode 10a of the chip resistor 1 are connected via one via hole 33, and the lower surface side of the resin layer 30 via the other via hole 34. And the second external electrode 10b of the chip resistor 1 are connected.
以上説明したように、本実施形態例に係るチップ抵抗器１は、抵抗体４を覆う保護膜（アンダーコート層５とオーバーコート層６）の一端部を除く大部分に補助電極７が被着されており、この補助電極７が一対の表電極３ａ，３ｂの一方（第１表電極３ａ）とのみ接続されているため、補助電極７を覆う広くて平坦な第１外部電極１０ａを形成することができる。したがって、図４に示すように、積層回路基板等のベース基板の樹脂層３０の内部に埋め込んで使用する場合、広くて平坦な第１外部電極１０ａに対してビアホール３３を簡単かつ確実に接続させることができる。 As described above, in the chip resistor 1 according to the present embodiment, the auxiliary electrode 7 is attached to most of the protective film (the undercoat layer 5 and the overcoat layer 6) covering the resistor 4 except for one end. Since the auxiliary electrode 7 is connected to only one of the pair of front electrodes 3a and 3b (first front electrode 3a), a wide and flat first external electrode 10a covering the auxiliary electrode 7 is formed. be able to. Therefore, as shown in FIG. 4, when embedded and used in the resin layer 30 of the base substrate such as a laminated circuit board, the via hole 33 is easily and reliably connected to the wide and flat first external electrode 10a. be able to.
また、補助電極７はオーバーコート層６を覆って他方の第２表電極３ｂの近くまで延びており、トリミング溝Ｔから大きく離れたオーバーコート層６の一端部だけが補助電極７から露出した状態となっているため、外部電極１０ａ，１０ｂの表面に形成された酸化物を除去する洗浄処理が行われたとしても、抵抗体４を覆う樹脂製のオーバーコート層６が洗浄液によってダメージを受けにくくなり、オーバーコート層６の損傷に起因する耐湿性の劣化を防止することができる。さらに、電流印加時に抵抗体４から発生する熱が補助電極７によって放熱されるため、放熱性に優れたチップ抵抗器１を実現することができる。 In addition, the auxiliary electrode 7 covers the overcoat layer 6 and extends to the vicinity of the other second front electrode 3b, and only one end of the overcoat layer 6 far away from the trimming groove T is exposed from the auxiliary electrode 7. Therefore, even if a cleaning process for removing oxides formed on the surfaces of the external electrodes 10a and 10b is performed, the resin overcoat layer 6 covering the resistor 4 is hardly damaged by the cleaning liquid. Thus, it is possible to prevent deterioration of the moisture resistance due to the damage of the overcoat layer 6. Further, since the heat generated from the resistor 4 when the current is applied is radiated by the auxiliary electrode 7, the chip resistor 1 excellent in heat radiation can be realized.
また、保護膜の厚み相当分だけ、第１表電極３ａに接続された補助電極７を覆う第１外部電極１０ａと、第２表電極３ｂを覆う第２端面電極９ｂとに段差が形成されるため、ベース基板の樹脂層３０にレーザ光を照射して補助電極７上の第１外部電極１０ａに達するビアホール３３を形成する際に、レーザ光が絶縁基板２の表面側で隣接する第１外部電極１０ａと第２外部電極１０ｂの段差部分に照射されたとしても、これら第１外部電極１０ａと第２外部電極１０ｂがビアホール３３を介して導通されてしまうことを防止できる。 Also, a step is formed between the first external electrode 10a covering the auxiliary electrode 7 connected to the first front electrode 3a and the second end face electrode 9b covering the second front electrode 3b by an amount corresponding to the thickness of the protective film. Therefore, when irradiating the resin layer 30 of the base substrate with a laser beam to form the via hole 33 reaching the first external electrode 10 a on the auxiliary electrode 7, the laser beam is applied to the first external electrode adjacent to the surface side of the insulating substrate 2. Even if the irradiation is made to the step between the electrode 10a and the second external electrode 10b, it is possible to prevent the first external electrode 10a and the second external electrode 10b from being conducted through the via hole 33.
また、第１および第２外部電極１０ａ，１０ｂはＮｉメッキからなる内部のバリア層とＣｕメッキからなる外表面の接続層との２層構造となっており、このバリア層がレーザ光をブロックして補助電極７や第１および第２表電極３ａ，３ｂまで到達しないように阻止するため、ビアホールを介しての耐湿性の劣化を防止することができる。 Further, the first and second external electrodes 10a and 10b have a two-layer structure of an inner barrier layer made of Ni plating and a connection layer on the outer surface made of Cu plating, and this barrier layer blocks laser light. As a result, it is possible to prevent the auxiliary electrode 7 and the first and second front electrodes 3a and 3b from reaching the first and second front electrodes 3a and 3b.
また、本実施形態例に係る部品内蔵型回路基板では、ベース基板の樹脂層３０に埋め込まれたチップ抵抗器１が上記の如く構成されているため、樹脂層３０に内層されたチップ抵抗器１の広くて平坦な第１外部電極１０ａに対してビアホールを簡単かつ確実に接続させることができる。 In addition, in the circuit board with a built-in component according to the present embodiment, the chip resistor 1 embedded in the resin layer 30 of the base substrate is configured as described above. The via hole can be easily and reliably connected to the wide and flat first external electrode 10a.
なお、図４に示す部品内蔵型回路基板の場合、チップ抵抗器１の表裏両面に露出する第１外部電極１０ａと第２外部電極１０ｂに対してビアホールが接続されているが、図５に示す部品内蔵型回路基板のように、絶縁基板２の裏面側に露出する第１外部電極１０ａと第２外部電極１０ｂに対してビアホールを接続させることも可能である。すなわち、図５に示すように、チップ抵抗器１は樹脂層３０の内部に天地逆にした姿勢で埋め込まれており、一方のビアホール３３を介して樹脂層３０の上面側の配線パターン３１とチップ抵抗器１の第２外部電極１０ｂが接続され、他方のビアホール３４を介して樹脂層３０の上面側の配線パターン３２とチップ抵抗器１の第１外部電極１０ａが接続されている。 In the case of the component built-in type circuit board shown in FIG. 4, via holes are connected to the first external electrode 10a and the second external electrode 10b exposed on both front and back surfaces of the chip resistor 1, as shown in FIG. Like a component built-in type circuit board, a via hole can be connected to the first external electrode 10a and the second external electrode 10b exposed on the back surface side of the insulating substrate 2. That is, as shown in FIG. 5, the chip resistor 1 is embedded in the resin layer 30 in an upside down position, and is connected to the wiring pattern 31 on the upper surface side of the resin layer 30 through one via hole 33. The second external electrode 10b of the resistor 1 is connected, and the wiring pattern 32 on the upper surface side of the resin layer 30 and the first external electrode 10a of the chip resistor 1 are connected via the other via hole 34.
１ チップ抵抗器
２ 絶縁基板
３ 表電極
３ａ 第１表電極
３ｂ 第２表電極
４ 抵抗体
５ アンダーコート層（保護膜）
６ オーバーコート層（保護膜）
７ 補助電極
８ 裏電極
８ａ 第１裏電極
８ｂ 第２裏電極
９ａ 第１端面電極
９ｂ 第２端面電極
１０ａ 第１外部電極
１０ｂ 第２外部電極
２０ 大判基板
２１ 一次分割溝
２２ 二次分割溝
３０ 樹脂層
３１，３２ 配線パターン
３３，３４ ビアホール
Ｔ トリミング溝
DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulating substrate 3 Front electrode 3a First front electrode 3b Second front electrode 4 Resistor 5 Undercoat layer (protective film)
6 Overcoat layer (protective film)
Reference Signs List 7 auxiliary electrode 8 back electrode 8a first back electrode 8b second back electrode 9a first end surface electrode 9b second end surface electrode 10a first external electrode 10b second external electrode 20 large substrate 21 primary division groove 22 secondary division groove 30 resin Layer 31, 32 Wiring pattern 33, 34 Via hole T Trimming groove
Claims (3)
前記チップ抵抗器が、直方体形状の絶縁基板と、この絶縁基板の表面に所定間隔を存して設けられた一対の表電極と、前記絶縁基板の表面に設けられて一対の前記表電極を橋絡する抵抗体と、前記抵抗体を覆う絶縁性の保護膜と、一対の前記表電極の一方とのみ接続されると共に、他方の前記表電極寄りの一端部を除いた領域の前記保護膜を覆う補助電極と、前記絶縁基板の裏面における前記表電極と対応する位置に設けられた一対の裏電極と、前記絶縁基板の両端面に設けられて対応する前記表電極と前記裏電極を導通する一対の端面電極と、前記表電極と前記裏電極と前記端面電極および前記補助電極の外表面を覆う一対の外部電極とを備えると共に、
一対の前記外部電極のうちの一方のみが前記補助電極の外表面を覆っており、前記ベース基板に、いずれか一方面から前記補助電極を覆う前記外部電極に達するビアホールと、いずれか他方面から前記補助電極に導通しない方の前記裏電極を覆う前記外部電極に達するビアホールとが設けられていることを特徴とする部品内蔵型回路基板。 In a component built-in type circuit board in which a chip resistor is embedded in an inner layer of a base board made of an insulating resin layer,
The chip resistor includes a rectangular parallelepiped-shaped insulating substrate, a pair of front electrodes provided on the surface of the insulating substrate at a predetermined interval, and a pair of front electrodes provided on the surface of the insulating substrate. And the protective film covering the resistor, and the protective film in a region that is connected to only one of the pair of front electrodes and excludes one end near the other front electrode. Auxiliary electrodes to be covered, a pair of back electrodes provided at positions corresponding to the front electrodes on the back surface of the insulating substrate, and electrical connections between the corresponding front electrodes and the back electrodes provided at both end surfaces of the insulating substrate. A pair of end electrodes, and a pair of external electrodes covering the outer surface of the front electrode, the back electrode, the end electrodes and the auxiliary electrode, and
Only one of the pair of external electrodes covers the outer surface of the auxiliary electrode, and the base substrate has a via hole reaching the external electrode covering the auxiliary electrode from any one surface, and from the other surface. A component-embedded circuit board, comprising: a via hole that covers the back electrode that does not conduct to the auxiliary electrode and reaches the external electrode.
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| JP2016085997A JP6674833B2 (en) | 2016-04-22 | 2016-04-22 | Chip resistor and component built-in circuit board |
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| JP6674833B2 true JP6674833B2 (en) | 2020-04-01 |
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| JP3111823B2 (en) * | 1994-08-26 | 2000-11-27 | 松下電器産業株式会社 | Square chip resistor with circuit inspection terminal |
| JP2002353001A (en) * | 2001-05-25 | 2002-12-06 | Tateyama Kagaku Kogyo Kk | Thick film chip resistor |
| JP6285096B2 (en) * | 2011-12-26 | 2018-02-28 | ローム株式会社 | Chip resistor and electronic device |
| JP2014183104A (en) * | 2013-03-18 | 2014-09-29 | Ibiden Co Ltd | Electronic component and electronic component built-in wiring board |
| JP2015079872A (en) * | 2013-10-17 | 2015-04-23 | コーア株式会社 | Chip resistor |
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