JP6688025B2 - Chip resistor and method of manufacturing chip resistor - Google Patents

Chip resistor and method of manufacturing chip resistor Download PDF

Info

Publication number
JP6688025B2
JP6688025B2 JP2015167221A JP2015167221A JP6688025B2 JP 6688025 B2 JP6688025 B2 JP 6688025B2 JP 2015167221 A JP2015167221 A JP 2015167221A JP 2015167221 A JP2015167221 A JP 2015167221A JP 6688025 B2 JP6688025 B2 JP 6688025B2
Authority
JP
Japan
Prior art keywords
chip
resistor
insulating substrate
electrodes
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015167221A
Other languages
Japanese (ja)
Other versions
JP2017045861A (en
Inventor
松本 健太郎
健太郎 松本
伊藤 隆志
隆志 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP2015167221A priority Critical patent/JP6688025B2/en
Priority to PCT/JP2016/073847 priority patent/WO2017033793A1/en
Publication of JP2017045861A publication Critical patent/JP2017045861A/en
Application granted granted Critical
Publication of JP6688025B2 publication Critical patent/JP6688025B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/02Housing; Enclosing; Embedding; Filling the housing or enclosure
    • H01C1/034Housing; Enclosing; Embedding; Filling the housing or enclosure the housing or enclosure being formed as coating or mould without outer sheath
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/14Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material

Description

本発明は、回路基板上に半田付けによって面実装されるチップ抵抗器と、そのようなチップ抵抗器の製造方法に関するものである。   The present invention relates to a chip resistor surface-mounted on a circuit board by soldering, and a method for manufacturing such a chip resistor.

この種のチップ抵抗器は、セラミックスからなる直方体形状の絶縁基板と、絶縁基板の表面に所定間隔を存して対向配置された一対の表電極と、これら一対の表面電極に接続するように絶縁基板の表面に設けられた抵抗体と、抵抗体を覆うように設けられた樹脂からなる保護膜と、絶縁基板の裏面に所定間隔を存して対向配置された一対の裏電極と、表電極と裏電極を導通するように絶縁基板の両端面に設けられた一対の端面電極と、これら端面電極の外表面にめっき処理を施して形成された一対の外部電極とを備えている。   This type of chip resistor is composed of a rectangular parallelepiped insulating substrate made of ceramics, a pair of front electrodes facing each other at a predetermined interval on the surface of the insulating substrate, and insulating so as to be connected to the pair of surface electrodes. A resistor provided on the front surface of the substrate, a protective film made of resin provided so as to cover the resistor, a pair of back electrodes arranged to face the back surface of the insulating substrate with a predetermined gap, and a front electrode. And a pair of end face electrodes provided on both end faces of the insulating substrate so as to conduct the back electrode, and a pair of outer electrodes formed by plating the outer surfaces of these end face electrodes.

このように構成されたチップ抵抗器は、回路基板に設けられたランド上に半田ペーストを印刷した後、裏電極を下向きにして外部電極をランド上に搭載し、この状態で半田ペーストを溶融・固化することによって回路基板上に面実装されるようになっている。   The chip resistor configured in this way prints the solder paste on the land provided on the circuit board, mounts the external electrode on the land with the back electrode facing downward, and melts the solder paste in this state. By solidifying, it is surface-mounted on the circuit board.

一方、特許文献1に開示されているように、チップコンデンサ等のチップ状電子部品において、角柱状のチップ素体の長手方向両端部にキャップ状の端面電極を形成するという技術が知られている。かかるチップ状電子部品では、キャップ状の端面電極が角柱状のチップ素体の上面と下面および両側面まで延びているため、回路基板上に4面(上面と下面および両側面)いずれの姿勢でも搭載することができる。   On the other hand, as disclosed in Patent Document 1, in a chip-shaped electronic component such as a chip capacitor, a technique is known in which cap-shaped end face electrodes are formed at both longitudinal ends of a prismatic chip element body. . In such a chip-shaped electronic component, since the cap-shaped end surface electrodes extend to the upper surface and lower surface and both side surfaces of the prismatic chip element body, any of four positions (upper surface, lower surface and both side surfaces) on the circuit board Can be installed.

特許文献1にはチップ状電子部品の一例としてチップ抵抗器が挙げられており、チップ抵抗器においても、絶縁基板の両端部にキャップ状の端面電極を形成して、この端面電極を表電極に接続させるという構成にすれば、回路基板上に4面での搭載が可能となる。   Patent Document 1 discloses a chip resistor as an example of a chip-shaped electronic component. Also in the chip resistor, a cap-shaped end face electrode is formed at both ends of an insulating substrate, and this end face electrode is used as a front electrode. With the configuration of connection, it is possible to mount on four sides on the circuit board.

なお、特許文献1には端面電極を形成する具体的な方法について特に明記されていないが、例えば特許文献2に開示されているように、外周面に導電ペーストを塗布させたローラを回転させると共に、ローラの回転方向とほぼ同じ方向にチップ素体を移動させながら、ローラの外周面にチップ素体の一面を近接させて導電ペーストを塗布するという塗布方法を採用すれば、端面電極の寸法のバラツキを極力抑えることが可能となる。   Although Patent Document 1 does not specifically describe a specific method for forming the end face electrode, as disclosed in Patent Document 2, for example, while rotating a roller having a conductive paste applied to the outer peripheral surface, If the application method of applying the conductive paste by bringing one surface of the chip body close to the outer peripheral surface of the roller while moving the chip body in the almost same direction as the rotation direction of the roller is adopted, It is possible to suppress variations as much as possible.

特開昭61−183911号公報JP-A-61-183911 特開2003−264117号公報JP, 2003-264117, A

ところで通常のチップ抵抗器は、セラミックスからなる絶縁基板の表面に抵抗体を覆う保護膜が形成されているため、前述したように絶縁基板の両端部にキャップ状の端面電極を形成する場合、絶縁基板の表面全体に表電極と抵抗体を覆うように保護膜を形成した後、導電ペーストを絶縁基板の端面側から保護膜の上面と絶縁基板の裏面および両側面の途中位置まで回り込ます必要がある。   By the way, in a normal chip resistor, since a protective film covering the resistor is formed on the surface of an insulating substrate made of ceramics, when the cap-shaped end face electrodes are formed on both ends of the insulating substrate as described above, insulation is not required. After forming a protective film on the entire surface of the substrate so as to cover the front electrode and the resistor, it is necessary to wrap the conductive paste from the end surface side of the insulating substrate to the upper surface of the insulating film, the back surface of the insulating substrate, and intermediate positions on both side surfaces. is there.

しかしながら、樹脂からなる保護膜が形成された上面と、絶縁基板のセラミックス面が露出する裏面および両側面とでは、絶縁基板の端面側から塗布される導電ペーストの回り込み量に大きな差が生じてしまうため、端面電極のキャップ形状が不規則になってしまうという問題がある。すなわち、導電ペーストの回り込み量は、樹脂の露出する上面で滲みが大きく、セラミックス面の露出する裏面で滲みが少なくなるため、表裏面での電極寸法が相違してしまい、さらに、側面の電極形状が上面側(保護膜側)に引っ張られて斜めになってしまう。その結果、チップ抵抗器の側面を下向きにした姿勢で回路基板に搭載された場合、回路基板のランドに半田付けされる一対の端面電極が「ハの字」状に対向することになるため、半田ペーストを硬化させるときのセルフアライメント効果を発揮することができなくなってしまう。   However, there is a large difference in the amount of the conductive paste applied from the end surface side of the insulating substrate between the upper surface on which the protective film made of resin is formed and the back surface and both side surfaces where the ceramic surface of the insulating substrate is exposed. Therefore, there is a problem that the cap shape of the end face electrode becomes irregular. In other words, the wraparound amount of the conductive paste is large on the exposed upper surface of the resin and less on the exposed back surface of the ceramic surface, so the electrode dimensions on the front and back surfaces are different, and the electrode shape on the side surface is different. Is pulled to the upper surface side (protective film side) and becomes slanted. As a result, when the chip resistors are mounted on the circuit board with the side surface facing downward, the pair of end face electrodes soldered to the lands of the circuit board face each other in a “C” shape. It becomes impossible to exert the self-alignment effect when the solder paste is cured.

本発明は、上記した従来技術の実情に鑑みてなされたものであり、その第1の目的は、絶縁基板の両端部に寸法の安定したキャップ状端面電極を形成することができるチップ抵抗器を提供することにある。また、本発明の第2の目的は、このようなチップ抵抗器の製造方法を提供することにある。   The present invention has been made in view of the above-mentioned circumstances of the prior art. A first object of the present invention is to provide a chip resistor capable of forming cap-shaped end face electrodes having stable dimensions at both ends of an insulating substrate. To provide. A second object of the present invention is to provide a method of manufacturing such a chip resistor.

上記した第1の目的を達成するために、本発明のチップ抵抗器は、セラミックスからなる直方体形状の絶縁基板と、この絶縁基板の表面における長手方向両端部に設けられた一対の表電極と、これら両表電極間を接続する抵抗体と、この抵抗体と前記両表電極を含めて前記絶縁基板の表面全体を覆う樹脂からなる保護膜と、前記絶縁基板の裏面全体を覆う樹脂からなる補助膜と、前記絶縁基板の長手方向両端面に設けられて前記表電極に導通する一対の端面電極とを備え、前記端面電極が前記保護膜と前記補助膜および前記絶縁基板の両側面の長手方向両端部を覆っていると共に、前記保護膜と前記補助膜が同一の樹脂材料で形成されているという構成にした。 In order to achieve the above-mentioned first object, the chip resistor of the present invention comprises a rectangular parallelepiped insulating substrate made of ceramics, and a pair of front electrodes provided on both ends in the longitudinal direction on the surface of the insulating substrate, A resistor connecting the two front electrodes, a protective film made of a resin covering the entire front surface of the insulating substrate including the resistor and the both front electrodes, and an auxiliary resin made of a resin covering the entire back surface of the insulating substrate. A film, and a pair of end face electrodes provided on both end faces in the longitudinal direction of the insulating substrate and electrically connected to the front electrode, the end face electrodes being in the longitudinal direction of both side faces of the protective film, the auxiliary film and the insulating substrate. The both end portions are covered, and the protective film and the auxiliary film are made of the same resin material .

このように構成されたチップ抵抗器では、絶縁基板の表面全体を覆う保護膜と絶縁基板の裏面全体を覆う補助膜がいずれも同質の樹脂材料で形成されているため、絶縁基板の表面と裏面で端面電極の滲み量がほぼ同じになる。したがって、絶縁基板の両側面に露出するセラミックス面についても、端面電極が同質材料からなる保護膜と補助膜に同じように引っ張られるため、端面電極の寸法が直方体形状のチップ抵抗器の4面(上面と下面および両側面)において均一になり、寸法の安定したキャップ状の端面電極を形成することができる。しかも、保護膜と補助膜が同一の樹脂材料で形成されているため、端面電極の寸法をより安定させることができる。 In the chip resistor configured in this way, the protective film covering the entire front surface of the insulating substrate and the auxiliary film covering the entire rear surface of the insulating substrate are both formed of the same resin material, so Thus, the amount of bleeding on the end face electrodes becomes almost the same. Therefore, even with respect to the ceramic surfaces exposed on both sides of the insulating substrate, since the end face electrodes are pulled in the same manner by the protective film and the auxiliary film made of the same material, the size of the end face electrodes is four sides of the rectangular parallelepiped chip resistor ( It is possible to form a cap-shaped end surface electrode having a uniform size on the upper and lower surfaces and both side surfaces and having stable dimensions. Moreover, since the protective film and the auxiliary film are formed of the same resin material, the dimension of the end face electrode can be made more stable.

また、上記の構成において、端面電極の端面形状が縦横比を同じくする正方形であると、幅寸法と厚み寸法を等しくする角柱形状のチップ抵抗器となるため、回路基板上への搭載面がチップ抵抗器の4面で全て同じになって好ましい。   Further, in the above-mentioned configuration, when the end face shape of the end face electrode is a square having the same aspect ratio, it becomes a prismatic chip resistor having the same width and thickness dimensions, so that the mounting surface on the circuit board is a chip. It is preferable that all four sides of the resistor are the same.

上記した第2の目的を達成するために、本発明によるチップ抵抗器の製造方法は、セラミックスからなる大判基板の表面における複数のチップ形成領域にそれぞれ一対の表電極を形成する工程と、前記対をなす表電極間を接続するように抵抗体を形成する工程と、前記表電極と前記抵抗体を覆うように前記大判基板の表面における前記複数のチップ形成領域全体に樹脂からなる保護膜を形成する工程と、前記大判基板の裏面における複数のチップ形成領域全体に樹脂からなる補助膜を形成する工程と、前記大判基板を前記表電極の中央部を通って長手方向へ延びる1次分割ラインと、この1次分割ラインに直交する2次分割ラインとに沿ってダイシングブレードで切断して個々のチップ素子を形成する工程と、前記チップ素子の前記1次分割ラインに沿う切断面から前記2次分割ラインに沿う切断面の一部にかけて導電ペーストを塗布して端面電極を形成する工程と、含み、前記保護膜と前記補助膜が同一の樹脂材料で形成されていることを特徴としている。 In order to achieve the above-mentioned second object, a method of manufacturing a chip resistor according to the present invention comprises a step of forming a pair of front electrodes in a plurality of chip forming regions on the surface of a large-sized substrate made of ceramics, and the pair of front electrodes. Forming a resistor so as to connect between the front electrodes forming the substrate, and forming a protective film made of a resin over the plurality of chip forming regions on the surface of the large-sized substrate so as to cover the front electrode and the resistor. And a step of forming an auxiliary film made of resin on the entire plurality of chip formation regions on the back surface of the large-sized substrate, and a primary division line extending in the longitudinal direction through the large-sized substrate through the central portion of the front electrode. A step of forming individual chip elements by cutting with a dicing blade along a secondary division line orthogonal to the primary division line, and the primary division of the chip element. Forming an end surface electrode by applying a conductive paste from the cut surface along the in-subjected part of the cut surface along the secondary distribution lines, seen including, forming the auxiliary layer and the protective layer are the same resin material It is characterized by being.

このように大判基板の表面に多数個のチップ抵抗器に対応する表電極と抵抗体および保護膜を形成すると共に、大判基板の裏面に補助膜を形成した後、ダイシングによって大判基板を個々のチップ素子に分割してから、チップ素子の端面側に導電ペーストを塗布して端面電極を形成すると、セラミックスからなるチップ素子の表面全体を覆う保護膜と裏面全体を覆う補助膜がいずれも同質の樹脂材料からなるため、チップ素子の表面と裏面で端面電極の滲み量がほぼ同じになる。したがって、チップ素子の両側面に露出するセラミックス面についても、端面電極が同質材料からなる保護膜と補助膜に同じように引っ張られるため、端面電極の寸法が直方体形状のチップ抵抗器の4面(上面と下面および両側面)において均一になり、しかも、保護膜と補助膜が同一の樹脂材料で形成されているため、寸法の安定したキャップ状の端面電極を形成することができる。 In this way, the front electrode corresponding to many chip resistors, the resistors and the protective film are formed on the front surface of the large-sized substrate, and the auxiliary film is formed on the back surface of the large-sized substrate, and then the large-sized substrate is divided into individual chips by dicing. When the end face electrodes are formed by applying a conductive paste to the end face side of the chip element after dividing into elements, the protective film covering the entire front surface of the chip element made of ceramics and the auxiliary film covering the entire back surface are both made of the same resin. Since it is made of a material, the amount of bleeding of the end face electrode is almost the same on the front surface and the back surface of the chip element. Therefore, even with respect to the ceramic surfaces exposed on both side surfaces of the chip element, since the end surface electrodes are pulled in the same manner by the protective film and the auxiliary film made of the same material, the size of the end surface electrodes is four sides of the rectangular parallelepiped chip resistor ( Since the upper surface, the lower surface and both side surfaces are uniform and the protective film and the auxiliary film are made of the same resin material, a cap-shaped end surface electrode having a stable dimension can be formed.

本発明のチップ抵抗器とその製造方法によれば、絶縁基板の両端部に寸法の安定したキャップ状の端面電極を形成することができる。   According to the chip resistor and the method of manufacturing the same of the present invention, it is possible to form cap-shaped end face electrodes having stable dimensions on both ends of the insulating substrate.

本発明の実施形態例に係るチップ抵抗器の斜視図である。It is a perspective view of the chip resistor concerning the example of an embodiment of the present invention. 該チップ抵抗器の平面図である。It is a top view of this chip resistor. 図2のIII−III線に沿う断面図である。It is sectional drawing which follows the III-III line of FIG. 図2のIV−IV線に沿う断面図である。It is sectional drawing which follows the IV-IV line of FIG. 図2のV−V線に沿う断面図Sectional drawing which follows the VV line of FIG. 該チップ抵抗器の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of this chip resistor. 該チップ抵抗器の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of this chip resistor.

以下、発明の実施の形態について図面を参照しながら説明すると、本発明の実施形態例に係るチップ抵抗器は、図1〜図5に示すように、直方体形状の絶縁基板1と、絶縁基板1の表面における長手方向両端部に設けられた一対の表電極2と、これら表電極2に接続するように設けられた長方形状の抵抗体3と、両表電極2と抵抗体3を含めて絶縁基板1の表面全体を覆う樹脂からなる保護膜4と、絶縁基板1の裏面全体を覆う樹脂からなる補助膜5と、絶縁基板1の長手方向両端部に設けられた一対の端面電極6とによって主に構成されている。   BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described with reference to the drawings. A chip resistor according to an embodiment of the present invention includes a rectangular parallelepiped insulating substrate 1 and an insulating substrate 1 as shown in FIGS. A pair of front electrodes 2 provided at both ends in the longitudinal direction on the surface of the, a rectangular resistor 3 provided so as to be connected to these front electrodes 2, and insulation including both front electrodes 2 and the resistor 3. The protective film 4 made of a resin covering the entire front surface of the substrate 1, the auxiliary film 5 made of a resin covering the entire back surface of the insulating substrate 1, and the pair of end face electrodes 6 provided at both ends in the longitudinal direction of the insulating substrate 1. It is mainly composed.

絶縁基板1はセラミックスからなり、この絶縁基板1は後述する大判基板を縦横に延びる1次分割ラインと2次分割ラインに沿ってダイシングすることにより多数個取りされたものである。   The insulating substrate 1 is made of ceramics, and the insulating substrate 1 is obtained by dicing a large-sized substrate, which will be described later, along primary and secondary dividing lines extending vertically and horizontally.

一対の表電極2はAg系ペーストをスクリーン印刷して乾燥・焼成させたものであり、これら表電極2は絶縁基板1の短辺側と両長辺側の各端面から露出するように矩形状に形成されている。   The pair of front electrodes 2 is formed by screen-printing an Ag-based paste and then dried and fired. These front electrodes 2 are rectangular so as to be exposed from each end face of the insulating substrate 1 on the short side and both long sides. Is formed in.

抵抗体3は酸化ルテニウム等の抵抗ペーストをスクリーン印刷して乾燥・焼成させたものであり、この抵抗体3の長手方向の両端部はそれぞれ表電極2に重なっている。なお、図示省略されているが、抵抗体3には抵抗値を調整するためのトリミング溝が形成されている。   The resistor 3 is formed by screen-printing a resistance paste such as ruthenium oxide and drying and firing, and both ends of the resistor 3 in the longitudinal direction overlap the front electrode 2. Although not shown, the resistor 3 has a trimming groove for adjusting the resistance value.

保護膜4はエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させたオーバーコート層であり、図示省略されているが、保護膜4の下側には抵抗体3を覆うアンダーコート層が形成されている。なお、このアンダーコート層はガラスペーストをスクリーン印刷して乾燥・焼成させたものである。保護膜4は両表電極2と抵抗体3を含めて絶縁基板1の表面全体を覆うように形成されているため、図3中で左側に位置する表電極2の左端を含む3端面が絶縁基板1と保護膜4間から露出し、右側に位置する表電極2の右端を含む3端面が絶縁基板1と保護膜4間から露出している。   The protective film 4 is an overcoat layer obtained by screen-printing an epoxy resin paste and heating and curing it. Although not shown, an undercoat layer covering the resistor 3 is formed below the protective film 4. There is. The undercoat layer was formed by screen-printing a glass paste, followed by drying and firing. Since the protective film 4 is formed so as to cover the entire surface of the insulating substrate 1 including both the front electrodes 2 and the resistor 3, the three end surfaces including the left end of the front electrode 2 located on the left side in FIG. 3 are insulated. It is exposed between the substrate 1 and the protective film 4, and three end faces including the right end of the front electrode 2 located on the right side are exposed between the insulating substrate 1 and the protective film 4.

補助膜5はエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させたものであり、この補助膜5と前述した保護膜4は同一の樹脂材料を用いて形成されることが好ましい。   The auxiliary film 5 is formed by screen-printing an epoxy resin paste and heat-curing it. It is preferable that the auxiliary film 5 and the above-mentioned protective film 4 are formed of the same resin material.

一対の端面電極6はAgペーストやCuペーストをディップ塗布して加熱硬化させたものであり、これら端面電極6は絶縁基板1の両端面1aから保護膜4の上面と補助膜5の下面および絶縁基板1の両側面1bを覆うようにキャップ状に形成されている。これにより、図3中で左側に位置する端面電極6は、絶縁基板1と保護膜4間から露出する左側の表電極2の3端面と接続され、右側に位置する端面電極6は、絶縁基板1と保護膜4間から露出する右側の表電極2の3端面と接続されている。   The pair of end face electrodes 6 are formed by dip-coating Ag paste or Cu paste and heating and curing. The end face electrodes 6 are formed from both end faces 1a of the insulating substrate 1 to the upper face of the protective film 4 and the lower face of the auxiliary film 5 and the insulating film. It is formed in a cap shape so as to cover both side surfaces 1b of the substrate 1. As a result, the end face electrode 6 located on the left side in FIG. 3 is connected to the three end faces of the left front electrode 2 exposed between the insulating substrate 1 and the protective film 4, and the end face electrode 6 located on the right side is the insulating substrate. It is connected to the three end faces of the right front electrode 2 exposed from between 1 and the protective film 4.

図示省略されているが、一対の端面電極6は外部電極によって覆われており、これら外部電極は端面電極6の表面にNi,Sn等を電解メッキして形成されたものである。   Although not shown, the pair of end face electrodes 6 are covered with external electrodes, and these external electrodes are formed by electrolytically plating Ni, Sn, etc. on the surface of the end face electrodes 6.

以上説明したように、本実施形態例に係るチップ抵抗器では、絶縁基板1の表面全体を覆う保護膜4と絶縁基板1の裏面全体を覆う補助膜5がいずれもエポキシ系樹脂等からなる樹脂材料で形成されているため、絶縁基板1の長手方向両端部にキャップ状の端面電極6を塗布形成する際に、絶縁基板1の表面と裏面で端面電極6の滲み量がほぼ同じになる。したがって、絶縁基板1の両側面1bに露出するセラミックス面についても、端面電極6が同一材料からなる保護膜4と補助膜5に同じように引っ張られるため、端面電極6の寸法が直方体形状のチップ抵抗器の4面(上面と下面および両側面)において均一になり、寸法の安定したキャップ状の端面電極6を形成することができる。   As described above, in the chip resistor according to the present embodiment, the protective film 4 that covers the entire front surface of the insulating substrate 1 and the auxiliary film 5 that covers the entire rear surface of the insulating substrate 1 are both made of epoxy resin or the like. Since it is made of a material, when the cap-shaped end surface electrodes 6 are formed by coating on both ends of the insulating substrate 1 in the longitudinal direction, the amount of bleeding of the end surface electrodes 6 becomes substantially the same on the front surface and the back surface of the insulating substrate 1. Therefore, even on the ceramic surface exposed on both side surfaces 1b of the insulating substrate 1, since the end face electrode 6 is pulled in the same manner by the protective film 4 and the auxiliary film 5 made of the same material, the size of the end face electrode 6 is a rectangular chip. It is possible to form the cap-shaped end surface electrode 6 which is uniform on the four surfaces (upper surface and lower surface and both side surfaces) of the resistor and has stable dimensions.

ここで、本実施形態例に係るチップ抵抗器では、図1に示すように、端面電極6の端面形状が縦横比を同じくする正方形に設定されており、幅寸法Wと厚み寸法Tを等しくする角柱形状のチップ抵抗器(例えば、幅寸法W=0.1mm、厚み寸法T=0.1mm)となっている。これにより、チップ抵抗器の4面(上面と下面および両側面)に形成される端面電極6が面積の等しい同一形状となるため、このような形状のチップ抵抗器を回路基板上に搭載する場合、チップ抵抗器の4面(上面と下面および両側面)のいずれが搭載面になったとしても、全く同じようにセルフアライメント効果を発揮することができる。   Here, in the chip resistor according to the present embodiment, as shown in FIG. 1, the end face shape of the end face electrode 6 is set to a square having the same aspect ratio, and the width dimension W and the thickness dimension T are made equal. It is a prismatic chip resistor (for example, width dimension W = 0.1 mm, thickness dimension T = 0.1 mm). As a result, the end face electrodes 6 formed on the four faces (the upper face, the lower face, and both side faces) of the chip resistor have the same shape with the same area. Therefore, when mounting the chip resistor having such a shape on the circuit board, Even if any of the four surfaces (top surface, bottom surface, and both side surfaces) of the chip resistor is the mounting surface, the self-alignment effect can be exerted in exactly the same manner.

次に、上記の如く構成されたチップ抵抗器の製造方法について、図6と図7を参照しながら説明する。   Next, a method of manufacturing the chip resistor configured as described above will be described with reference to FIGS. 6 and 7.

まず、図6(a)と図7(a)に示すように、絶縁基板1が多数個取りされるセラミックスからなる大判基板10を準備する。この大判基板10に1次分割溝や2次分割溝は形成されていないが、図6(f)に示す後工程で大判基板10は縦横に延びる1次分割ラインL1と2次分割ラインL2に沿ってダイシングされ、これら両分割ラインL1,L2によって区切られたマス目の1つ1つが1個分のチップ形成領域となる。なお、図6は大判基板10を平面的に見た状態を示し(図6(e)だけは裏面図)、図7は図6中の1個分のチップ形成領域を断面した状態を示している。   First, as shown in FIGS. 6A and 7A, a large-sized substrate 10 made of ceramics in which a large number of insulating substrates 1 are taken is prepared. Although no primary dividing groove or secondary dividing groove is formed in this large-sized substrate 10, the large-sized substrate 10 is formed into a primary dividing line L1 and a secondary dividing line L2 that extend in the vertical and horizontal directions in the post process shown in FIG. 6 (f). Each of the cells, which are diced along with each other and are divided by the two dividing lines L1 and L2, serve as a chip forming region for one piece. 6 shows a state in which the large-sized substrate 10 is viewed in plan view (only FIG. 6 (e) is a rear view), and FIG. 7 shows a state in which a chip forming region for one in FIG. 6 is cross-sectioned. There is.

そして、このような大判基板10の表面にAg系ペーストを印刷して乾燥・焼成させることにより、図6(b)と図7(b)に示すように、大判基板10の表面に所定間隔を存して帯状に延びる複数対の表電極2を形成する。   Then, by printing an Ag-based paste on the surface of such a large-sized substrate 10 and drying and baking it, a predetermined interval is formed on the surface of the large-sized substrate 10 as shown in FIGS. 6 (b) and 7 (b). A plurality of pairs of front electrodes 2 that exist and extend in strips are formed.

次に、大判基板10の表面に酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して乾燥・焼成させることにより、図6(c)と図7(c)に示すように、対をなす表電極2間に跨る複数の抵抗体3を形成する。なお、表電極2と抵抗体3の形成順序は上記と逆であっても良い。   Next, a resistor paste such as ruthenium oxide is screen-printed on the surface of the large-sized substrate 10 and is dried and baked to form a pair of front electrodes 2 as shown in FIGS. 6 (c) and 7 (c). A plurality of resistor bodies 3 extending in between are formed. The order of forming the front electrode 2 and the resistor 3 may be reversed.

次に、トリミング溝形成時の抵抗体3へのダメージを軽減するものとして、ガラスペーストをスクリーン印刷して乾燥・焼成することにより、抵抗体3を覆う図示せぬアンダーコート層を形成した後、このアンダーコート層の上から抵抗体3にトリミング溝を形成して抵抗値を調整する。しかる後、アンダーコート層の上からエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させることにより、図6(d)と図7(d)に示すように、表電極2と抵抗体3を含めて大判基板10のチップ形成領域全体を覆う保護膜4を形成する。   Next, in order to reduce damage to the resistor 3 when forming the trimming groove, a glass paste is screen-printed, dried and baked to form an undercoat layer (not shown) covering the resistor 3, A trimming groove is formed in the resistor 3 on the undercoat layer to adjust the resistance value. Then, an epoxy resin paste is screen-printed on the undercoat layer and heat-cured to include the front electrode 2 and the resistor 3 as shown in FIGS. 6 (d) and 7 (d). A protective film 4 is formed to cover the entire chip formation area of the large-sized substrate 10.

次に、大判基板10の裏面にエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させることにより、図6(e)と図7(e)に示すように、大判基板10の裏面におけるチップ形成領域全体を覆う補助膜5を形成する。   Next, an epoxy resin paste is screen-printed on the back surface of the large-sized substrate 10 and heat-cured, so that the entire chip formation region on the back surface of the large-sized substrate 10 is formed as shown in FIGS. An auxiliary film 5 is formed to cover the.

しかる後、図6(f)に示すように、大判基板10を表電極2の幅方向中央部を通って長手方向へ延びる1次分割ラインL1と、この1次分割ラインL1に直交する2次分割ラインL2とに沿ってダイシングブレードで切断することにより、図6(g)に示すように、チップ抵抗器と外形をほぼ同じくする個々のチップ素子10Aを得る。なお、大判基板10の周辺部は各チップ形成領域を包囲するダミー領域となっており、このダミー領域はダイシング後に捨て基板10Bとして破棄される。また、これら1次分割ラインL1と2次分割ラインL2は大判基板10に対して設定された仮想線であり、前述したように大判基板10に分割ラインに対応する1次分割溝や2次分割溝は形成されていない。   After that, as shown in FIG. 6 (f), the large-sized substrate 10 passes through the central portion of the front electrode 2 in the width direction, and the primary dividing line L1 extends in the longitudinal direction. By cutting with a dicing blade along the division line L2, as shown in FIG. 6G, individual chip elements 10A having substantially the same outer shape as the chip resistor are obtained. The peripheral portion of the large-sized substrate 10 is a dummy region surrounding each chip formation region, and this dummy region is discarded as a discarded substrate 10B after dicing. The primary division line L1 and the secondary division line L2 are virtual lines set for the large-sized board 10, and as described above, the primary division groove and the secondary division corresponding to the division line are formed on the large-sized board 10. The groove is not formed.

次に、チップ素子10Aの端面にAgペーストやCuペースト等の導電ペーストをディップ塗布して加熱硬化させることにより、図7(f)に示すように、チップ素子10Aの長手方向両端面から短手方向両端面の所定位置まで回り込む端面電極6を形成する。その際、チップ素子10Aの相対向する2面を覆う保護膜4と補助膜5が同じ樹脂材料(エポキシ系樹脂)で形成されているため、これら保護膜4と補助膜5が形成されたチップ素子10Aの2面で端面電極6の滲み量がほぼ同じになる。したがって、チップ素子10Aの残り2面に露出するセラミックス面についても、端面電極6が同一材料からなる保護膜4と補助膜5に同じように引っ張られるため、直方体形状のチップ素子10Aの4面(上面と下面および両側面)に形成される端面電極6の寸法を均一にすることができる。   Next, a conductive paste such as Ag paste or Cu paste is dip-coated on the end surface of the chip element 10A and heat-cured, so that the chip element 10A is short-sided from both longitudinal end surfaces as shown in FIG. 7 (f). End face electrodes 6 are formed so as to wrap around to predetermined positions on both end faces in the direction. At this time, since the protective film 4 and the auxiliary film 5 covering the two opposite surfaces of the chip element 10A are formed of the same resin material (epoxy resin), the chip on which the protective film 4 and the auxiliary film 5 are formed The amount of bleeding of the end face electrode 6 is substantially the same on the two surfaces of the element 10A. Therefore, even with respect to the ceramic surfaces exposed on the remaining two surfaces of the chip element 10A, since the end face electrodes 6 are similarly pulled by the protective film 4 and the auxiliary film 5 made of the same material, the four surfaces of the rectangular parallelepiped chip element 10A ( It is possible to make the dimensions of the end face electrodes 6 formed on the upper and lower surfaces and both side surfaces uniform.

最後に、個々のチップ素子10Aに対してNi,Sn等の電解メッキを施すことにより、端面電極6を被覆する図示せぬ外部電極を形成し、図1に示すようなチップ抵抗器が完成する。   Finally, electrolytic plating of Ni, Sn or the like is applied to each chip element 10A to form an external electrode (not shown) covering the end surface electrode 6, and the chip resistor as shown in FIG. 1 is completed. .

以上説明したように、本実施形態例に係るチップ抵抗器の製造方法では、大判基板10の表面に多数個のチップ抵抗器に対応する表電極2と抵抗体3および保護膜4を形成すると共に、大判基板10の裏面に補助膜5を形成した後、ダイシングによって大判基板10を個々のチップ素子10Aに分割してから、チップ素子10Aの端面側にAgペースト等の導電ペーストをディップ塗布して端面電極6を形成するようにしているが、その際、セラミックスからなるチップ素子の相対向する2面を覆う保護膜4と補助膜5が同じ樹脂材料で形成されているため、これら保護膜4と補助膜5が形成されたチップ素子10Aの2面で端面電極6の滲み量がほぼ同じになる。したがって、チップ素子10Aの残り2面に露出するセラミックス面についても、端面電極6が同一材料からなる保護膜4と補助膜5に同じように引っ張られるため、直方体形状のチップ素子10Aの4面(上面と下面および両側面)において端面電極6の寸法が均一になり、寸法の安定したキャップ状の端面電極6を形成することができる。   As described above, in the chip resistor manufacturing method according to the present embodiment, the front electrode 2, the resistor 3 and the protective film 4 corresponding to a large number of chip resistors are formed on the surface of the large-sized substrate 10. After forming the auxiliary film 5 on the back surface of the large-sized substrate 10, the large-sized substrate 10 is divided into individual chip elements 10A by dicing, and then a conductive paste such as Ag paste is dip-coated on the end surface side of the chip elements 10A. The end face electrodes 6 are formed. At this time, since the protective film 4 and the auxiliary film 5 covering the two opposite surfaces of the chip element made of ceramics are formed of the same resin material, these protective films 4 are formed. And the amount of bleeding of the end face electrode 6 becomes substantially the same on the two surfaces of the chip element 10A on which the auxiliary film 5 is formed. Therefore, even with respect to the ceramic surfaces exposed on the remaining two surfaces of the chip element 10A, the end face electrodes 6 are similarly pulled by the protective film 4 and the auxiliary film 5 made of the same material, so that the four surfaces of the rectangular parallelepiped chip element 10A ( The size of the end surface electrode 6 is uniform on the upper surface, the lower surface, and both side surfaces, and the cap-shaped end surface electrode 6 having a stable size can be formed.

また、本実施形態例に係るチップ抵抗器の製造方法では、大判基板10に表電極2と抵抗体3および保護膜4や補助膜5を形成した後、大判基板10を1次分割ラインL1と2次分割ラインL2に沿ってダイシングしてチップ素子10Aを得るとき、帯状に形成された表電極2が長さ方向と幅方向にそれぞれ切断されるようになっているため、保護膜4によって覆われた表電極2の切断面がチップ素子10Aの端面と両側面からそれぞれ露出した状態となる。したがって、その後にチップ素子10Aの両端部に端面電極6を形成するとき、表電極2と端面電極6の接続箇所がチップ素子10Aの端面だけでなく両側面を含めた3面となり、端面電極6と表電極2との接続信頼性を非常に高めることができる。   Further, in the method of manufacturing the chip resistor according to the present embodiment example, after the front electrode 2, the resistor 3, the protective film 4 and the auxiliary film 5 are formed on the large-sized substrate 10, the large-sized substrate 10 is changed to the primary division line L1. When the chip element 10A is obtained by dicing along the secondary division line L2, the strip-shaped front electrodes 2 are cut in the length direction and the width direction, respectively, and thus are covered with the protective film 4. The cut surface of the exposed front electrode 2 is exposed from the end surface and both side surfaces of the chip element 10A. Therefore, when the end face electrodes 6 are formed on both ends of the chip element 10A after that, the connection points of the front electrode 2 and the end face electrode 6 become not only the end face of the chip element 10A but also three faces including both side faces, and the end face electrode 6 The connection reliability between the front electrode 2 and the front electrode 2 can be greatly improved.

1 絶縁基板
2 表電極
3 抵抗体
4 保護膜
5 補助膜
6 端面電極
10 大判基板
10A チップ素子
L1 1次分割ライン
L2 2次分割ライン
1 Insulating Substrate 2 Front Electrode 3 Resistor 4 Protective Film 5 Auxiliary Film 6 End Face Electrode 10 Large Format Substrate 10A Chip Element L1 Primary Dividing Line L2 Secondary Dividing Line

Claims (3)

セラミックスからなる直方体形状の絶縁基板と、この絶縁基板の表面における長手方向両端部に設けられた一対の表電極と、これら両表電極間を接続する抵抗体と、この抵抗体と前記両表電極を含めて前記絶縁基板の表面全体を覆う樹脂からなる保護膜と、前記絶縁基板の裏面全体を覆う樹脂からなる補助膜と、前記絶縁基板の長手方向両端面に設けられて前記表電極に導通する一対の端面電極とを備え、前記端面電極が前記保護膜と前記補助膜および前記絶縁基板の両側面の長手方向両端部を覆っていると共に、前記保護膜と前記補助膜が同一の樹脂材料で形成されていることを特徴とするチップ抵抗器。 A rectangular parallelepiped insulating substrate made of ceramics, a pair of front electrodes provided at both ends in the longitudinal direction on the surface of the insulating substrate, a resistor connecting the two front electrodes, and the resistor and the both front electrodes. And a protective film made of resin covering the entire front surface of the insulating substrate, an auxiliary film made of resin covering the entire back surface of the insulating substrate, and electrically connected to the front electrode provided on both end faces in the longitudinal direction of the insulating substrate. And a pair of end face electrodes, the end face electrodes covering both end portions in the longitudinal direction of both side faces of the protective film and the auxiliary film and the insulating substrate, and the protective film and the auxiliary film are the same resin material. A chip resistor characterized by being formed of . 請求項1の記載において、前記端面電極の端面形状が縦横比を同じくする正方形であることを特徴とするチップ抵抗器。 2. The chip resistor according to claim 1, wherein the end face shape of the end face electrode is a square having the same aspect ratio . セラミックスからなる大判基板の表面における複数のチップ形成領域にそれぞれ一対の表電極を形成する工程と、A step of forming a pair of front electrodes in a plurality of chip forming regions on the surface of a large-sized substrate made of ceramics,
前記対をなす表電極間を接続するように抵抗体を形成する工程と、  Forming a resistor so as to connect between the pair of front electrodes,
前記表電極と前記抵抗体を覆うように前記大判基板の表面における前記複数のチップ形成領域全体に樹脂からなる保護膜を形成する工程と、  A step of forming a protective film made of resin over the plurality of chip forming regions on the surface of the large-sized substrate so as to cover the front electrode and the resistor;
前記大判基板の裏面における複数のチップ形成領域全体に樹脂からなる補助膜を形成する工程と、  A step of forming an auxiliary film made of a resin on the entire plurality of chip forming regions on the back surface of the large-sized substrate,
前記大判基板を前記表電極の中央部を通って長手方向へ延びる1次分割ラインと、この1次分割ラインに直交する2次分割ラインとに沿ってダイシングブレードで切断して個々のチップ素子を形成する工程と、  The large-sized substrate is cut by a dicing blade along a primary dividing line extending in the longitudinal direction through the central portion of the front electrode, and a secondary dividing line orthogonal to the primary dividing line to cut individual chip elements. Forming process,
前記チップ素子の前記1次分割ラインに沿う切断面から前記2次分割ラインに沿う切断面の一部にかけて導電ペーストを塗布して端面電極を形成する工程と、  Forming an end face electrode by applying a conductive paste from a cut surface along the primary division line of the chip element to a part of the cut surface along the secondary division line;
を含み、前記保護膜と前記補助膜が同一の樹脂材料で形成されていることを特徴とするチップ抵抗器の製造方法。And the protective film and the auxiliary film are formed of the same resin material.
JP2015167221A 2015-08-26 2015-08-26 Chip resistor and method of manufacturing chip resistor Active JP6688025B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015167221A JP6688025B2 (en) 2015-08-26 2015-08-26 Chip resistor and method of manufacturing chip resistor
PCT/JP2016/073847 WO2017033793A1 (en) 2015-08-26 2016-08-15 Chip resistor and method for manufacturing chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015167221A JP6688025B2 (en) 2015-08-26 2015-08-26 Chip resistor and method of manufacturing chip resistor

Publications (2)

Publication Number Publication Date
JP2017045861A JP2017045861A (en) 2017-03-02
JP6688025B2 true JP6688025B2 (en) 2020-04-28

Family

ID=58100131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015167221A Active JP6688025B2 (en) 2015-08-26 2015-08-26 Chip resistor and method of manufacturing chip resistor

Country Status (2)

Country Link
JP (1) JP6688025B2 (en)
WO (1) WO2017033793A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7407132B2 (en) * 2019-02-07 2023-12-28 ローム株式会社 Resistor
JP2022189028A (en) 2021-06-10 2022-12-22 Koa株式会社 Chip component

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330802A (en) * 1996-06-07 1997-12-22 Matsushita Electric Ind Co Ltd Resistor and its manufacture
JP3466411B2 (en) * 1997-03-31 2003-11-10 太陽誘電株式会社 Chip resistor
JPH11283804A (en) * 1998-03-31 1999-10-15 Murata Mfg Co Ltd Resistor
JP2011165752A (en) * 2010-02-05 2011-08-25 Taiyosha Electric Co Ltd Chip resistor
JP6476417B2 (en) * 2013-08-07 2019-03-06 パナソニックIpマネジメント株式会社 Resistor manufacturing method
JP6499007B2 (en) * 2015-05-11 2019-04-10 Koa株式会社 Chip resistor

Also Published As

Publication number Publication date
JP2017045861A (en) 2017-03-02
WO2017033793A1 (en) 2017-03-02

Similar Documents

Publication Publication Date Title
CN101271750B (en) Electronic component and method for manufacturing the same
JP5115968B2 (en) Chip resistor manufacturing method and chip resistor
JP2007073693A (en) Chip resistor and method of manufacturing same
JP6181500B2 (en) Chip resistor and manufacturing method thereof
JP6688025B2 (en) Chip resistor and method of manufacturing chip resistor
US20180090247A1 (en) Chip Resistor
US8854175B2 (en) Chip resistor device and method for fabricating the same
WO2016167182A1 (en) Chip resistor and method for manufacturing same
WO2017057248A1 (en) Chip resistor
JP6170726B2 (en) Manufacturing method of chip resistor
JP2017228701A (en) Chip resistor and mounting structure of the same
JP6715002B2 (en) Chip resistor mounting structure
JP2017059597A (en) Chip resistor
JP6629013B2 (en) Chip resistor and method of manufacturing chip resistor
JP6577315B2 (en) Manufacturing method of chip resistor
JP6599759B2 (en) Chip resistor
JP6159286B2 (en) Chip resistor and manufacturing method of chip resistor
JP4504577B2 (en) Manufacturing method of chip resistor
JP2003272901A (en) Thick film resistor and its manufacturing method
JP6695415B2 (en) Chip resistor
KR101538416B1 (en) Chip resistor device and method for fabricating the same
JP6688035B2 (en) Chip resistor
JP5166685B2 (en) Chip resistor and its manufacturing method
KR101544393B1 (en) Chip resistor device and method for fabricating the same
JP2022159807A (en) chip resistor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180806

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190917

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191113

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200331

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200403

R150 Certificate of patent or registration of utility model

Ref document number: 6688025

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250