JP4504577B2 - Manufacturing method of chip resistor - Google Patents

Manufacturing method of chip resistor Download PDF

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Publication number
JP4504577B2
JP4504577B2 JP2001029323A JP2001029323A JP4504577B2 JP 4504577 B2 JP4504577 B2 JP 4504577B2 JP 2001029323 A JP2001029323 A JP 2001029323A JP 2001029323 A JP2001029323 A JP 2001029323A JP 4504577 B2 JP4504577 B2 JP 4504577B2
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film
electrode film
insulating substrate
upper layer
lower layer
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JP2002231503A (en
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英 遠山
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Kamaya Electric Co Ltd
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Kamaya Electric Co Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、抵抗体膜を配置した絶縁基板を分割して形成されるチップ形抵抗器およびそのチップ形抵抗器の製造方法に関するものである。
【0002】
【従来の技術】
昨今、携帯端末等の小形化と普及に伴って極小寸法を有するチップ形抵抗器の供給が要請されるようになった。そして、この極小寸法を有するチップ形抵抗器の、小形電子機器における回路基板への採用と実装に際しては、実装の効率化とはんだ接合の信頼性の確保に向けて、部品メーカおよび機器メーカが協力することが望まれる。
【0003】
一方、部品メーカ等における前記チップ形抵抗器の製造方法は、例えば下記の手順にて形成される。すなわち、まず、両面分割スリッ入りの絶縁基板を用意し、これにメタルグレーズ(AgまたはAg・Pd系グレーズ)の印刷を行って例えば約850℃で焼成し、膜厚が8〜12μmの裏面電極を形成する。この裏面電極は、一次方向分割スリッを跨ぎ、さらに二次方向分割スリッから離間して形成するか、または一次方向および二次方向の分割スリッを跨いでスクリーン印刷により形成する。
【0004】
次に、絶縁基板にメタルグレーズ(Ag・Pd系グレーズ)を印刷、例えば850℃で焼成し、膜層が8〜12μmの表電極膜下層を形成する。すなわち、表電極膜下層は一次方向分割スリッを跨ぎ、さらに二次方向分割スリッから離間して形成する。続いて、一対の表電極膜下層間にRuO2 系グレーズをスクリーン印刷し、これを850℃で焼成して抵抗体膜を形成し、その抵抗体膜上に硼珪酸鉛ガラスで二層化したコート膜を形成する。
【0005】
このコート膜は抵抗体膜を覆い、二次方向分割スリッを跨いで形成して600℃で焼成するアンダーコート膜と、このアンダーコート膜を覆い、二次方向分割スリッから離間して形成して600℃で焼成するオーバーコート膜とからなる。なお、レーザ工法による抵抗値調整のためのトリミング溝の刻設が、オーバーコート膜形成前のアンダーコート膜上から行われる。続いて、AgまたはAg・Pd系グレーズで一次方向および二次方向の分割スリッを跨いで、表電極膜下層上にスクリーン印刷をし、これを600℃で焼成して、約8〜12μmの膜厚の表電極膜上層を形成した、いわゆる表電極が二層化した構造に形成されている。
【0006】
短冊状に絶縁基板の分割基板に続き、AgまたはAg・Pd系グレーズで表電極膜上層および裏電極膜の一部に重畳するように印刷塗布し、約600℃で焼成して端面電極膜を形成し、この焼成後に個々のチップに分割を行って、Niめっき膜に続くSn系めっき膜又はSn・Pbめっき膜を電極めっき膜として形成する。
【0007】
図10はこのような従来のチップ形抵抗器の製造工程を示し、以下、これを説明する。このチップ形抵抗器は一次方向および二次方向に形成された分割スリットに絶縁基板を分割して、矩形のチップに形成される。図10(a)乃至図10(j)はそのチップ単位で見たチップ抵抗器の製造工程を示す。まず、図10(a)に示すように、矩形状に区画された絶縁基板1の裏側の左右両端部に位置するように、該絶縁基板1の左右の両端および前後両端までの領域、または図10(b)に示すように、この前後両端から所定距離だけ離間した領域に裏電極膜2を形成する。一方、前記絶縁基板1の表側の左右両端部に位置するように、該絶縁基板1の前後両端からそれぞれ所定距離離間した位置までの領域に、図10(c)に示すような表電極膜下層3を形成する。そして、図10(d)に示すように、前記の左右両端部の表電極膜下層3どうしをこれらの一部に重なるように抵抗体膜4により接続し、さらにその抵抗体膜4を前記絶縁基板1の前後両端までアンダーコート膜5にて、図10(e)に示すように覆う。また、このアンダーコート膜5の上から前記抵抗体膜4の抵抗値調整のために、図10(f)に示すようにトリミング溝6を刻設し、前記絶縁基板1の前後両端まで、図10(g)に示すように、前記アンダーコート膜5およびトリミング溝6をオーバーコート膜7により覆う。
【0008】
次に、図10(h)に示すように、前記絶縁基板1の左右両端および前後両端まで、前記表電極膜下層3を表電極膜上層8にて覆い、前記絶縁基板1の左右端面を覆うように、または、その左右端面を覆いかつ前記裏電極膜2および表電極膜上層8の一部とに重畳するように、図10(i)に示すような端面電極膜9を形成し、最後に、図10(j)に示すように、前記裏電極膜2、表電極膜上層8および端面電極膜9を電極めっき膜10にて覆い、チップ形抵抗器を形成する。図11はこのような工程を経て製造されたチップ抵抗器の図10(j)のA−A線における断面図であり、図12は図11のC−C線における断面図である。また、図13は、裏電極にあって、図10(b)の実施態様における図11のCーC線対応部位の断面図である。
【0009】
【発明が解決しようとする課題】
しかしながら、前記のような従来のチップ抵抗器の製造方法では、両面分割スリッ入り絶縁基板を採用して、図10(a)及び図10(h)に図示するようにメタルグレーズの表裏電極膜が分割スリッに表裏電極膜材料が入り込んだ状態で機械的応力で分割するので、分割面の仕上がり精度が得られず、また絶縁基板、表裏電極膜のバリ、欠けが発生し、仕上がり精度と寸法が厳密に要求される微小寸法を有するチップ形抵抗器の製造には適さないという問題があった。
【0010】
また、図10(b)のように裏電極膜の形成において、二次方向の分割スリッから離間して形成した実施態様もあるが、微小寸法のチップ形抵抗器にあっては、印刷の位置ズレが無視できず、確保すべき裏電極膜範囲にバラツキが生じ、回路基板取付ランドへのはんだ接合の際にセルフアライメント効果が希薄になり、回路基板ランド、取付ランドに対して位置ズレが生じた状態ではんだ結合されたり、はんだ結合強度の信頼性が低下したり、回路基板の実装における部品隣接間隔が十分に確保できないなどの不具合が生じていた。
【0011】
さらに、表裏電極膜の一部に重畳する所定の膜厚を有するグレーズ系の端面電極膜の形成によって、表裏電極上で不均一な段差を生じ、特に微小寸法を有するチップ形抵抗器にあっては、回路基板ランドとのはんだ溶融の際に、はんだの濡れ応力によって、ツームストン現象(チップ立ち)が生じる要因になるという問題があった。
【0012】
本発明は前記のような問題を解決するものであり、その目的とするところは、表側または裏側のいずれでも回路基板へ実装でき、すなわち、テーピング加工してまたはバルクによるいずれの方法による供給も可能にし、また、一次方向および二次方向の分割時に絶縁基板、表裏電極膜およびコート膜のバリや欠けの発生を抑制でき、しかも寸法(長さ方向および幅方向)の仕上がり精度が安定する、小型化が可能なチップ形抵抗器およびその製造方法を提供することにある。
【0013】
また、本発明の他の目的は、表裏電極膜範囲が均一に確保でき、セルフアライメント効果が発揮できるとともに、表裏電極面上の平坦性が確保されツームストン現象の発生を抑制でき、さらにチップ形抵抗器の各製造工程における供給シュートでの搬送を円滑にして製造効率を向上できるとともに、テーピング加工供給方式におけるキャビティからのチップ形抵抗器の、実装機ノズルによる吸着取り出しを容易にできるチップ形抵抗器およびその製造方法を提供することにある。
【0014】
【課題を解決する手段】
前記目的達成のため、請求項1の発明にかかるチップ形抵抗器の製造方法は、絶縁基板の表裏面に一次方向と二次方向の分割スリットを刻設したものを用いて矩形状のチップ形抵抗器を製造する方法において、前記絶縁基板の裏面と表面の長手方向両側に裏電極膜と表電極膜とを形成する裏及び表電極膜下層形成工程と、該表電極膜下層間に接続して抵抗体膜を形成する抵抗体膜形成工程と、該抵抗体膜を覆うようにアンダーコート膜を形成するアンダーコート膜形成工程と、該アンダーコート膜上からトリミング溝を刻設するトリミング溝刻設工程と、該アンダーコート膜と前記トリミング溝を覆うようにオーバーコート膜を形成するオーバーコート膜形成工程と、前記表電極膜下層を覆うように表面電極膜上層を形成する表電極膜上層形成工程と、前記絶縁基板の一次方向の分割スリットに沿って短冊状にブレークする絶縁基板分割工程と、前記絶縁基板の左右両端面を覆い、かつ前記裏電極膜及び表電極膜下層の一部を重畳するように端面電極膜を形成する端面電極膜形成工程と、前記絶縁基板を二次方向の分割スリットに沿って個々のチップ状に分割するチップ状分割工程と、前記裏電極膜、表電極膜上層、及び端面電極膜を覆うように電気めっき膜を形成する電極めっき膜形成工程とを含むチップ形抵抗器の製造方法であって、前記トリミング溝刻設工程前の表電極膜下層形成工程が、二次方向の分割スリットだけでなく一次方向の分割スリットに対しても所定距離離間した位置までの領域に形成しており、かつ前記裏電極膜形成と表電極膜上層形成の各工程では、一次方向と二次方向共に分割スリットを跨いで形成するとともに、その跨いで形成した裏電極膜と表電極膜上層を一次方向の分割スリットに沿って分断する分断工程を前記絶縁基板分割工程前に行うようにしたことを特徴とする。
【0017】
また、請求項の発明にかかるチップ形抵抗器の製造方法は、前記裏電極膜および表電極膜下層を導電性のメタルグレーズ系の膜とし、前記表電極膜上層を導電性レジン系の膜とし、前記アンダーコート膜をガラス系の膜とし、前記オーバーコート膜をレジン系の膜とし、前記裏電極膜、表電極膜下層、表電極膜上層、アンダーコート膜およびオーバーコート膜の各形成工程のいずれかに続いて、レーザ工法によって一次方向二次方向の分割スリッをなぞるように裏電極膜のみの分断を行うことを特徴とする。
【0018】
また、請求項の発明にかかるチップ形抵抗器の製造方法は、前記裏電極膜、表電極膜下層および表電極膜上層をメタルグレーズ系の膜とし、前記アンダーコート膜およびオーバーコート膜をガラス系の膜とし、前記オーバーコート膜の形成工程に続いて、レーザ工法によって一次方向二次方向の分割スリッをなぞるように前記裏面電極膜、表電極膜下層、表電極膜上層、アンダーコート膜およびオーバーコート膜の分断を行うことを特徴とする。
【0019】
【発明の実施の形態】
以下、本発明の実施の一形態を詳細に説明する。まず、本発明の抵抗チップの製造方法を概念的に述べる。まず、96%以上のアルミナを含有し、かつ表裏面に一次方向および二次方向の分割スリッが入った絶縁基板を用意し、これの裏面に、AgまたはAg・Pd系のグレーズで印刷をし、これを約850℃で焼成して8〜12μmの膜厚の裏面電極を形成する。ここでは、一次方向および二次方向の分割スリッを跨いで、スクリーン印刷を行う。次に、絶縁基板の表面にAg・Pd系グレーズで印刷を行い、約850℃で焼成して表電極膜下層を形成する。このとき、一次方向および二次方向の分割スリッから離間してスクリーン印刷を行う。
【0020】
次に、一対の表電極膜下層にRuO2 系グレーズにより抵抗体膜の両端をスクリーン印刷にて接続し、これを約850℃で焼成し、その抵抗体膜の上に、硼珪酸鉛ガラスを二次方向の分割スリッを跨いでスクリーン印刷して、アンダーコート膜としてこれを約600℃で焼成する。続いて、このアンダーコート膜上からレーザ工法により抵抗値調整のためのトリミングを行い、その上にエポキシ系樹脂塗料を二次方向の分割スリットから離間して、アンダーコート膜を覆うようにスクリーン印刷を行った後、約200℃で硬化させてオーバーコート膜とする。また、この外のオーバーコート膜として、硼珪酸鉛ガラスを二次方向の分割スリッの一部または全部を跨いで、アンダーコート膜を覆うようにスクリーン印刷して、約600℃で焼成したものとしてもよい。
【0021】
続いて、表電極膜下層に重なるように、フェノール系導電性樹脂塗料を一次方向および二次方向の分割スリッを跨いでスクリーン印刷し、約200℃で硬化させて表電極膜上層を形成する。なお、前記オーバーコート膜として前記硼珪酸ガラスを用いた場合には、この表電極膜上層をAg系またはAg・Pd系グレーズを用い、一次方向および二次方向の分割スリッを跨いで表電極膜下層上からスクリーン印刷をし、これを600℃で焼成して、膜厚8〜12μmの表電極膜上層を形成する。
【0022】
このような表電極膜上層の形成後は、レーザ工法によって絶縁基板の一次方向および二次方向の分割スリッをなぞるように裏電極膜を分断し、続いて、レーザ工法により前記一次方向および二次方向の分割スリッをなぞるように、前記アンダーコート膜およびオーバーコート膜、さらには表電極膜を分断する。そして、端面電極形成に伴う表電極膜上層および裏電極膜の一部重畳部分を確保するように、マスキングレジストを塗布した後、絶縁基板を一次方向の分割スリッに沿って短冊状にブレークする。そして、その上にスパッタ法によって、Cr薄膜およびNi膜を形成し、前記マスキングレジストを除去し、絶縁基板を二次方向の分割スリッでブレークして、個々のチップ状に分割し、最後にNiめっき膜とSn系めっきまたはSn・Pbめっき膜を電極めっき膜として施すことにより、チップ形抵抗器を得る。
【0023】
図4、図5および図6は前記裏電極膜の分断溝を示し、11は裏電極膜の一次方向の分割スリッに沿った分断溝、12は裏電極膜の二次方向の分割スリッに沿った分断溝、13は絶縁基板上の二次方向の分割スリッである。また、図7、図8および図9は前記表電極膜、アンダーコート膜、オーバーコート膜の分断した例を示し、14は一次方向の分割スリッに沿ったレーザ分断溝、15は二次方向の分割スリッに沿ったレーザ分断溝である。なお、前記分断を行うためのレーザ工法では、レーザトリマーやレーザスクライバのいずれを使用してもよい。裏電極膜の分断工程は、裏電極膜形成後、表電極膜下層形成後、抵抗体膜形成後、アンダーコート膜形成後、トリミング溝形成後、オーバーコート膜形成後および表電極膜上層形成後のいずれかに行うことができる。また、レーザー工法による膜の分断は、本実施の形態に示すように表電極上層膜とオーバコートの材料によって適宜選択できる。
【0024】
次に、チップ単位で見た本発明のチップ抵抗器およびその製造工程を、図1(a)〜(m)について説明する。まず、図1(a)に示すように、矩形状に区画された絶縁基板1の裏側の左右両端部に位置するように、該絶縁基板1の左右両端および前後両端までの領域に裏電極膜2を形成する。一方、前記絶縁基板1の表側の左右両端部に位置するように、該絶縁基板1の左右両端および前後両端からそれぞれ所定距離離間した位置までの領域に、図1(b)に示すような表電極膜下層3を形成する。そして、図1(c)に示すように、前記の左右両端部の表電極膜下層3どうしを、これらの一部に重なるように抵抗体膜4により接続し、さらにその抵抗体膜4を前記絶縁基板1の前後両端までアンダーコート膜5にて図1(d)に示すように覆う。また、このアンダーコート膜5の上から前記抵抗体膜4の抵抗値調整のために、図1(e)に示すようなトリミング溝6を刻設して、図1(f)に示すように前記絶縁基板1の前後両端まで、または図1(g)に示すように一部が前記絶縁基板1の前後両端に至るまで、前記アンダーコート膜5およびトリミング溝6をオーバーコート膜7aまたは7bにより覆う。
【0025】
さらに、図1(h)または(i)に示すように、前記絶縁基板1の左右両端および前後両端まで、前記表電極膜下層3を表電極膜上層8により覆い、前記絶縁基板1の左右端面を覆うように、または該左右端面を覆い、かつ前記裏電極膜2および表電極膜上層8の一部に重畳するように、図1(j)または図1(k)に示すようにスパッタ工法による端面電極膜9を形成し、最後に、図1(l)または(m)に示すように、前記裏電極膜2、表電極膜上層8および端面電極膜9を電極めっき膜10により覆うようにしてチップ抵抗器を形成する。図2および図3はこのような工程を経て製造されたチップ抵抗器の正面断面図および図2のDーD線における側面断面図であり、図2は図1(l)又は(m)のB−B線の断面図、図3は図2のD−D線の断面図である。
【0026】
従って、このようにして製造されるチップ形抵抗器は、裏電極膜2および表電極膜上層8の一部に重畳されたスパッタ膜としての端面電極膜9が、これらの各電極膜上で不均一な段差の発生を抑制し、特に微小寸法を有するチップ形抵抗器にあっては、回路基板1上のランドとのはんだ溶融の際に、はんだの濡れ応力によって生じるツームストン現象(チップ立ち)の発生を抑制することができる。
【0027】
また、表電極膜を表電極膜下層3と表電極膜上層8との二層とし、表電極膜下層3を一次方向および二次方向の分割スリッから離間して形成し、表電極膜上層8は一次方向および二次方向の分割スリッまで形成することによって、電気的接続の信頼性が確保される。裏電極膜2も一次方向および二次方向の分割スリッまで形成しているので、チップ形抵抗器の表裏面に拘らず実装に適し、広い範囲の表裏電極膜と表裏電極面上の平坦性を確保することができる。さらに、セルフアライメント効果にも寄与し、回路基板実装の際の位置ずれも抑制できる。
【0028】
さらに、レーザ工程工法による裏電極膜2または表電極膜3、8および各コート膜7a、7bの分断を採用することにより、一次方向および二次方向の分割スリッに沿った機械的応力による絶縁基板の分割時に、裏電極膜2または表電極膜3、8およびコート膜7a、7bにバリや欠けが発生するのを抑制でき、分割スリッに入り込んだ膜材を昇華させることで、機械的応力による絶縁基板1の分割の際に刻設された絶縁基板の分割スリッを有効に活用でき、絶縁基板1の良好な分割面の仕上がりおよび寸法精度の向上を確保できる。
【0029】
なお、前記導電性樹脂系塗料の表電極膜上層を二次方向の分割スリッの一部を跨ぎ、かつ一部から離間して形成する場合には、表電極膜3、8およびコート膜7a、7bのレーザによる分割が不要となり、工程の簡略化が可能となる。
【0030】
また、前記のような絶縁基板の良好な分割面の仕上がりおよび寸法精度の向上によって、チップ形抵抗器の各製造工程における供給シュートでの搬送が円滑になり、製造効率が向上するとともに、テーピング加工供給方式におけるキャビティからのチップ形抵抗器の実装機ノズルによる吸着取り出しが容易になる。
【0031】
【発明の効果】
以上のように、本発明によれば、チップ形抵抗器の表側または裏側のいずれも回路基板への実装が可能であり、テーピング加工およびバルクのいずれの方法による供給も可能になるほか、一次方向および二次方向のブレーク時における絶縁基板、表裏電極膜およびコート膜のバリや欠けが抑制され、かつ、チップ形抵抗器の長さ方向、幅方向の仕上がり精度が安定化し、小形化が可能になるという効果が得られる。
【0032】
また、表裏電極膜の領域の厚みの均一性が確保できて、セルフアライメント効果を発揮でき、また平坦性が確保されることで、ツームストン現象の発生を抑制できるという効果が得られる。さらに、各製造工程におけるチップ形抵抗器の供給シュートでの流れが円滑に進むとともに、テーピング加工供給方式でのキャビティからのチップ形抵器の実装器ノズルによる吸着取り出しが容易になるなどの効果が得られる。
【図面の簡単な説明】
【図1】本発明の実施の一形態によるチップ形抵抗器の製造工程を示す説明図である。
【図2】図1に示すチップ形抵抗器の縦断面図である。
【図3】図2のD−D線における断面図である。
【図4】本発明における絶縁基板上の裏電極膜の分断構造を示す要部の平面図である。
【図5】図4のE−E線における縦断面図である。
【図6】図4のF−F線における縦断面図である。
【図7】本発明における絶縁基板上の表電極膜およびコート膜の分断構造を示す要部の平面図である。
【図8】図7のH−H線における縦断面図である。
【図9】図7のJ−J線における縦断面図である。
【図10】従来のチップ形抵抗器の製造工程を示す説明図である。
【図11】従来のチップ形抵抗器を示す縦断面図である。
【図12】図11のC−C線における縦断面図である。
【図13】従来の他の例のチップ形抵抗器における前記C−C線対応部位での縦断面図である。
【符号の説明】
1 絶縁基板
2 裏電極膜
3 表電極膜下層
4 抵抗体膜
5 アンダーコート膜
6 トリミング溝
7 オーバーコート膜
8 表電極膜上層
9 端面電極膜
10 電極めっき膜
13 二次方向の分割スリッ
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip resistor formed by dividing an insulating substrate on which a resistor film is arranged, and a method for manufacturing the chip resistor.
[0002]
[Prior art]
In recent years, with the miniaturization and popularization of portable terminals and the like, the supply of chip resistors having extremely small dimensions has been requested. When chip resistors with these extremely small dimensions are used and mounted on circuit boards in small electronic devices, component manufacturers and device manufacturers cooperate to improve mounting efficiency and ensure solder joint reliability. It is desirable to do.
[0003]
On the other hand, a manufacturing method of the chip resistor in a component manufacturer or the like is formed by the following procedure, for example. That is, first, prepared insulating substrate duplex division slit DOO filled, this was calcined at go by for example about 850 ° C. The printing of metal glaze (Ag or Ag · Pd glaze), thickness of 8~12μm backside electrode that forms form the. The back electrode straddles the primary direction divides slit doo, further secondary direction dividing slit or formed apart from preparative, or formed by screen printing across the dividing slit bets primary direction and secondary direction.
[0004]
Next, a metal glaze (Ag / Pd-based glaze) is printed on the insulating substrate, for example, baked at 850 ° C. to form a surface electrode film lower layer having a film layer of 8 to 12 μm. That is, the front electrode film underlayer straddle the primary direction divides slit DOO, formed by spaced further apart from the secondary direction dividing slit and. Subsequently, a RuO2-based glaze was screen-printed between a pair of lower layers of the surface electrode film, and this was fired at 850 ° C. to form a resistor film, and the coat formed by forming a double layer of lead borosilicate glass on the resistor film A film is formed.
[0005]
The coated film covering the resistor film, the undercoat layer and baked at formed to 600 ° C. across secondary direction dividing slit preparative covers the undercoat film, formed spaced apart from the secondary direction dividing slit DOO And an overcoat film fired at 600 ° C. Note that the trimming grooves for adjusting the resistance value by the laser method are formed on the undercoat film before the overcoat film is formed. Then, across the dividing slit bets primary direction and the secondary direction of Ag or Ag · Pd glaze, the screen printed on the front electrode film lower layer on which was calcined at 600 ° C., about 8~12μm The surface electrode film upper layer having a film thickness is formed, and a so-called surface electrode is formed in a two-layer structure.
[0006]
Following the split substrate of the insulating substrate in the form of a strip, it is printed and coated with Ag or Ag / Pd-based glaze so as to overlap the upper electrode film upper layer and part of the back electrode film, and fired at about 600 ° C. to form the end face electrode film After the firing, the chip is divided into individual chips, and an Sn plating film or an Sn / Pb plating film following the Ni plating film is formed as an electrode plating film.
[0007]
FIG. 10 shows a manufacturing process of such a conventional chip resistor, which will be described below. This chip resistor is formed in a rectangular chip by dividing an insulating substrate into divided slits formed in a primary direction and a secondary direction. FIG. 10A to FIG. 10J show the manufacturing process of the chip resistor as seen in the chip unit. First, as shown to Fig.10 (a), the area | region to the both right and left ends and front-and-rear both ends of this insulated substrate 1 so that it may be located in the right and left both ends of the back side of the insulated substrate 1 divided into the rectangle shape, or figure As shown in FIG. 10B, the back electrode film 2 is formed in a region separated from the both front and rear ends by a predetermined distance. On the other hand, the lower layer of the surface electrode film as shown in FIG. 10 (c) is located in a region from the front and rear ends of the insulating substrate 1 to a position separated by a predetermined distance so as to be positioned at both left and right end portions on the front side of the insulating substrate 1. 3 is formed. Then, as shown in FIG. 10 (d), the surface electrode film lower layers 3 at the left and right end portions are connected to each other by a resistor film 4 so as to overlap a part thereof, and the resistor film 4 is further insulated. The front and rear ends of the substrate 1 are covered with an undercoat film 5 as shown in FIG. Further, in order to adjust the resistance value of the resistor film 4 from above the undercoat film 5, a trimming groove 6 is formed as shown in FIG. As shown in FIG. 10G, the undercoat film 5 and the trimming groove 6 are covered with an overcoat film 7.
[0008]
Next, as shown in FIG. 10 (h), the surface electrode film lower layer 3 is covered with the surface electrode film upper layer 8 to the left and right ends and the front and rear ends of the insulating substrate 1, and the left and right end surfaces of the insulating substrate 1 are covered. Or an end face electrode film 9 as shown in FIG. 10 (i) is formed so as to cover the left and right end faces and to overlap with the back electrode film 2 and a part of the front electrode film upper layer 8. Further, as shown in FIG. 10 (j), the back electrode film 2, the front electrode film upper layer 8 and the end face electrode film 9 are covered with an electrode plating film 10 to form a chip-type resistor. FIG. 11 is a cross-sectional view taken along the line AA of FIG. 10J of the chip resistor manufactured through such a process, and FIG. 12 is a cross-sectional view taken along the line CC of FIG. FIG. 13 is a cross-sectional view of a portion corresponding to the CC line of FIG. 11 in the embodiment of FIG. 10B in the back electrode.
[0009]
[Problems to be solved by the invention]
However, the conventional chip resistor manufacturing method described, employs a double-sided division slit preparative containing insulating substrate, front and back electrode film of metal glaze, as shown in FIGS. 10 (a) and 10 (h) since but split by a mechanical stress in a state that has entered the front and back electrode film material in the divided slit DOO, not obtained finishing accuracy of divided surface, also the insulating substrate, the front and back electrode film burrs, chipping is generated, and finish accuracy There is a problem that it is not suitable for the manufacture of a chip resistor having a minute dimension that is strictly required.
[0010]
Further, in the formation of the back electrode film as in FIG. 10 (b), there is also an embodiment which is spaced apart from the secondary direction of division slit bets, in the Chip Resistors critical dimension, the printing Misalignment is not negligible, variation occurs in the back electrode film area to be secured, the self-alignment effect is diminished when soldering to the circuit board mounting land, and the position misalignment with respect to the circuit board land and mounting land There have been problems such as solder bonding in the generated state, reliability of the solder bonding strength is reduced, and a sufficient distance between adjacent components in mounting the circuit board cannot be secured.
[0011]
Furthermore, the formation of a glaze-based end face electrode film having a predetermined film thickness that overlaps a part of the front and back electrode films results in uneven steps on the front and back electrodes, particularly in chip resistors having minute dimensions. However, there is a problem that a tombstone phenomenon (chip standing) occurs due to the solder wetting stress when the solder melts with the circuit board land.
[0012]
The present invention solves the above-described problems, and the object of the present invention is that it can be mounted on a circuit board on either the front side or the back side, that is, it can be supplied by any method by taping or bulk. In addition, it is possible to suppress the generation of burrs and chips on the insulating substrate, front and back electrode films and coat film when dividing in the primary and secondary directions, and the finished accuracy of dimensions (length direction and width direction) is stable. An object of the present invention is to provide a chip resistor that can be manufactured and a method of manufacturing the same.
[0013]
Another object of the present invention is that the front and back electrode film ranges can be ensured uniformly, the self-alignment effect can be exhibited, the flatness on the front and back electrode surfaces is ensured, and the occurrence of tombstone phenomenon can be suppressed, and the chip-type resistor Chip resistors that can improve the efficiency of production by smoothing the feeding chute in each manufacturing process and can easily remove the chip resistors from the cavities in the taping supply system using the mounting machine nozzle And providing a manufacturing method thereof.
[0014]
[Means for solving the problems]
In order to achieve the above object, a chip resistor manufacturing method according to the invention of claim 1 is a rectangular chip shape using a slit in which primary and secondary slits are engraved on the front and back surfaces of an insulating substrate. In the method of manufacturing a resistor, a back and front electrode film lower layer forming step of forming a back electrode film and a front electrode film on both sides in the longitudinal direction of the back surface and the front surface of the insulating substrate, and a connection between the lower surface electrode film lower layer Forming a resistor film, forming an undercoat film so as to cover the resistor film, and forming a trimming groove on the undercoat film. An overcoat film forming step for forming an overcoat film so as to cover the undercoat film and the trimming groove; and a surface electrode film upper layer type for forming a surface electrode film upper layer so as to cover the surface electrode film lower layer A step of dividing the insulating substrate into strips along the primary direction dividing slit; covering both left and right end surfaces of the insulating substrate; and part of the back electrode film and the lower layer of the front electrode film. An end face electrode film forming step for forming end face electrode films so as to overlap, a chip-like division step for dividing the insulating substrate into individual chips along a secondary direction division slit, the back electrode film, and the front electrode A chip-type resistor manufacturing method including an electrode plating film forming step of forming an electroplating film so as to cover the film upper layer and the end face electrode film, wherein the surface electrode film lower layer forming step before the trimming groove engraving step Is formed in a region up to a position separated by a predetermined distance not only in the secondary direction split slit but also in the primary direction split slit, and in each step of the back electrode film formation and the front electrode film upper layer formation ,once Before the insulating substrate dividing step, the dividing step of dividing the back electrode film and the front electrode film upper layer formed across the dividing slit in the primary direction and the secondary direction along the dividing slit in the primary direction is performed. characterized in that way the.
[0017]
According to a second aspect of the present invention, there is provided a chip resistor manufacturing method in which the back electrode film and the lower layer of the front electrode film are conductive metal glaze films, and the upper layer of the front electrode film is a conductive resin film. The undercoat film is a glass film, the overcoat film is a resin film, and each of the back electrode film, the surface electrode film lower layer, the surface electrode film upper layer, the undercoat film and the overcoat film is formed. following either, and performs cutting of only the back electrode film to trace the division slit bets primary direction secondary direction by the laser method.
[0018]
According to a third aspect of the present invention, there is provided a chip resistor manufacturing method, wherein the back electrode film, the front electrode film lower layer, and the front electrode film upper layer are metal glaze-based films, and the undercoat film and overcoat film are made of glass. a membrane system, following the step of forming the overcoat layer, the back electrode layer so as to trace the division slit bets primary direction secondary direction by the laser method, the front electrode film lower layer, the front electrode film layer, the undercoat layer And the overcoat film is divided.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail. First, a method for manufacturing a resistor chip according to the present invention will be conceptually described. First, containing more than 96% of alumina, and was prepared insulating substrate containing the division slit bets primary direction and the secondary direction on the front and back surfaces, the back surface of this, the printing with Ag or Ag · Pd-based glaze Then, this is baked at about 850 ° C. to form a back electrode having a thickness of 8 to 12 μm. Here, across the dividing slit bets primary direction and the secondary direction, performs screen printing. Next, printing is performed on the surface of the insulating substrate with Ag / Pd-based glaze, and baking is performed at about 850 ° C. to form a surface electrode film lower layer. At this time, it performs screen printing apart from the dividing slit preparative primary direction and secondary direction.
[0020]
Next, both ends of the resistor film are connected to the lower layer of the pair of surface electrode films by RuO2 glaze by screen printing, and this is baked at about 850 ° C. The lead borosilicate glass is bisected on the resistor film. It was screen-printed across the next direction of division slit bets and calcined at about 600 ° C. it as undercoat films. Subsequently, trimming for adjusting the resistance value is performed from above the undercoat film by a laser method, and then the epoxy resin paint is separated from the dividing slit in the secondary direction and screen printed so as to cover the undercoat film. Then, it is cured at about 200 ° C. to form an overcoat film. Further, as the outer overcoat film, which straddles a part or all of the lead borosilicate glass of the secondary oriented split slit bets, by screen printing so as to cover the undercoat layer and baked at about 600 ° C. It is good.
[0021]
Then, so as to overlap the front electrode film lower layer, a phenol-based electrically conductive resin coating material was screen printed across the dividing slit bets primary direction and the secondary direction to form a front electrode film upper layer is cured at about 200 ° C. . In the case of using the borosilicate glass as the overcoat film, the front electrode film upper layer using Ag-based or Ag · Pd glaze, front electrode across the dividing slit bets primary direction and the secondary direction Screen printing is performed from above the film lower layer, and this is baked at 600 ° C. to form a surface electrode film upper layer having a film thickness of 8 to 12 μm.
[0022]
Such front electrode film after the upper layer of the formation, by laser method to divide the back electrode film to trace the division slit bets primary direction and the secondary direction of the insulating substrate, followed by the a laser method primary direction and the secondary so as to trace the next direction of division slit bets, the undercoat layer and the overcoat film, and further to divide the front electrode film. Then, to ensure a portion overlapping portion of the front electrode film layer and the back electrode film due to edge electrode formation, after applying the masking resist, to break the strip along the insulating substrate to the division slit preparative primary direction . Then, by sputtering thereon, to form a Cr thin film and Ni film, the masking resist is removed, and break the insulating substrate in a secondary direction of division slit bets, divided into individual chip-shaped at the end A chip resistor is obtained by applying a Ni plating film and a Sn-based plating or Sn / Pb plating film as an electrode plating film.
[0023]
4, 5 and 6 show the dividing grooves of the back electrode film, 11 dividing grooves along the division slit bets primary direction of the back electrode film, 12 is divided slit bets secondary direction of the back electrode film dividing grooves along, 13 is divided slit preparative secondary direction on the insulating substrate. Further, FIGS. 7, 8 and 9 show an example of a partitioned the table electrode film, the undercoat film, overcoat film, laser cutting grooves along the division slit preparative primary direction 14, 15 secondary direction a laser cutting grooves along the division slit bets. In the laser method for performing the division, either a laser trimmer or a laser scriber may be used. After the back electrode film is formed, the surface electrode film lower layer is formed, the resistor film is formed, the undercoat film is formed, the trimming groove is formed, the overcoat film is formed, and the surface electrode film upper layer is formed. Can be done either. Moreover, the division | segmentation of the film | membrane by a laser construction method can be suitably selected by the material of a surface electrode upper layer film | membrane and an overcoat as shown to this Embodiment.
[0024]
Next, the chip resistor of the present invention viewed from the chip unit and the manufacturing process thereof will be described with reference to FIGS. First, as shown in FIG. 1 (a), the back electrode film is formed in the regions up to the left and right ends and the front and rear ends of the insulating substrate 1 so as to be positioned at the left and right ends on the back side of the insulating substrate 1 partitioned in a rectangular shape. 2 is formed. On the other hand, a table as shown in FIG. 1 (b) is formed in the region from the left and right ends and the front and rear ends of the insulating substrate 1 to a position separated by a predetermined distance so as to be positioned at the left and right ends on the front side of the insulating substrate 1. An electrode film lower layer 3 is formed. And as shown in FIG.1 (c), the surface electrode film lower layer 3 of the said right-and-left both ends is connected by the resistor film 4 so that these may be overlapped, and also the resistor film 4 is made into the said The both ends of the insulating substrate 1 are covered with an undercoat film 5 as shown in FIG. Further, in order to adjust the resistance value of the resistor film 4 from above the undercoat film 5, a trimming groove 6 as shown in FIG. 1 (e) is formed, as shown in FIG. 1 (f). The undercoat film 5 and the trimming groove 6 are formed by the overcoat film 7a or 7b up to both front and rear ends of the insulating substrate 1 or until a part reaches the front and rear ends of the insulating substrate 1 as shown in FIG. cover.
[0025]
Further, as shown in FIG. 1 (h) or (i), the surface electrode film lower layer 3 is covered with a surface electrode film upper layer 8 to both the left and right ends and the front and rear ends of the insulating substrate 1. As shown in FIG. 1 (j) or FIG. 1 (k), the sputtering method is applied so as to cover the left and right end surfaces and to overlap with part of the back electrode film 2 and the front electrode film upper layer 8. The end face electrode film 9 is formed, and finally, the back electrode film 2, the front electrode film upper layer 8 and the end face electrode film 9 are covered with the electrode plating film 10 as shown in FIG. Thus, a chip resistor is formed. 2 and 3 are a front sectional view and a side sectional view taken along the line DD of FIG. 2, respectively, of the chip resistor manufactured through such a process. FIG. 2 is a plan view of FIG. 1 (l) or (m). FIG. 3 is a cross-sectional view taken along line B-B, and FIG. 3 is a cross-sectional view taken along line D-D in FIG.
[0026]
Therefore, in the chip resistor manufactured in this way, the end face electrode film 9 as a sputtered film superimposed on a part of the back electrode film 2 and the front electrode film upper layer 8 is not formed on each of these electrode films. In the case of a chip-type resistor that suppresses the occurrence of a uniform step and has a particularly small dimension, when the solder melts with the land on the circuit board 1, the tombstone phenomenon (chip standing) caused by the solder wetting stress occurs. Occurrence can be suppressed.
[0027]
Also, the front electrode film and two layers of the front electrode film lower layer 3 and the front electrode film layer 8, formed by separating the front electrode film lower layer 3 from the dividing slit preparative primary direction and the secondary direction, the front electrode film layer 8 by forming to divide slit preparative primary direction and the secondary direction, the reliability of the electrical connection is ensured. Because the back electrode film 2 is also formed to divide slit preparative primary direction and the secondary direction, suitable regardless mounted on front and rear surfaces of the chip-type resistor, a wide range of front and back electrode film and the flatness of the front and back electrode surface Can be secured. Furthermore, it contributes to the self-alignment effect, and the positional deviation during circuit board mounting can be suppressed.
[0028]
Further, by employing a laser process method according to the back electrode film 2 or Table electrode film 3, 8 and the coat film 7a, a division of 7b, insulation due to mechanical stress along the division slit bets primary direction and the secondary direction time division of a substrate, the back electrode film 2 or Table electrode film 3, 8 and coat film 7a, burrs and chips can be prevented from occurring 7b, by sublimating intruded film material in the divided slit DOO, mechanical stress due to effective use of engraved has been insulated split slit bets substrate during the divided insulating substrate 1, it can be secured to improve the finishing and dimensional accuracy of better split surface of the insulating substrate 1.
[0029]
Incidentally, the table electrode film layer of conductive resin paint straddle a part of the secondary oriented split slit bets, and in the case of forming spaced apart from a portion, the front electrode film 3, 8 and coat film 7a , 7b is not required to be divided by the laser, and the process can be simplified.
[0030]
In addition, the finish of the insulating substrate as described above and the improvement of the dimensional accuracy facilitate the conveyance with the supply chute in each manufacturing process of the chip resistor, thereby improving the manufacturing efficiency and the taping process. It becomes easy to take out the chip resistor from the cavity in the supply system by the mounting machine nozzle.
[0031]
【The invention's effect】
As described above, according to the present invention, either the front side or the back side of the chip-type resistor can be mounted on the circuit board, and can be supplied by any of taping and bulk methods. In addition, burrs and chipping of the insulating substrate, front and back electrode films, and coat film during a break in the secondary direction are suppressed, and the finish accuracy in the length and width directions of the chip resistor is stabilized, enabling downsizing. The effect of becoming is obtained.
[0032]
In addition, the uniformity of the thicknesses of the front and back electrode film regions can be ensured, the self-alignment effect can be exhibited, and the flatness can be ensured, thereby suppressing the occurrence of the tombstone phenomenon. Furthermore, the flow at the supply chute of the chip resistor in each manufacturing process proceeds smoothly, and the suction of the chip resistor from the cavity by the mounting nozzle of the taping supply method is facilitated. can get.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a manufacturing process of a chip resistor according to an embodiment of the present invention.
2 is a longitudinal sectional view of the chip resistor shown in FIG. 1. FIG.
3 is a cross-sectional view taken along the line DD in FIG.
FIG. 4 is a plan view of a main part showing a dividing structure of a back electrode film on an insulating substrate in the present invention.
5 is a longitudinal sectional view taken along line EE in FIG. 4. FIG.
6 is a longitudinal sectional view taken along line FF in FIG. 4;
FIG. 7 is a plan view of a main part showing a divided structure of a surface electrode film and a coat film on an insulating substrate in the present invention.
8 is a longitudinal sectional view taken along line HH in FIG. 7;
9 is a longitudinal sectional view taken along line JJ in FIG.
FIG. 10 is an explanatory view showing a manufacturing process of a conventional chip resistor.
FIG. 11 is a longitudinal sectional view showing a conventional chip resistor.
12 is a longitudinal sectional view taken along line CC in FIG. 11. FIG.
FIG. 13 is a longitudinal sectional view taken along the line CC in a conventional chip resistor according to another example.
[Explanation of symbols]
1 insulating substrate 2 of the back electrode film 3 Table electrode film lower layer 4 resistor film 5 undercoat film 6 trimming groove 7 overcoat film 8 Table electrode film layer 9 end face electrode film 10 electrode plating film 13 secondary direction dividing slit DOO

Claims (3)

絶縁基板の表裏面に一次方向と二次方向の分割スリットを刻設したものを用いて矩形状のチップ形抵抗器を製造する方法において、In a method of manufacturing a rectangular chip resistor using a slit in which primary and secondary split slits are engraved on the front and back surfaces of an insulating substrate,
前記絶縁基板の裏面と表面の長手方向両側に裏電極膜と表電極膜とを形成する裏及び表電極膜下層形成工程と、該表電極膜下層間に接続して抵抗体膜を形成する抵抗体膜形成工程と、該抵抗体膜を覆うようにアンダーコート膜を形成するアンダーコート膜形成工程と、該アンダーコート膜上からトリミング溝を刻設するトリミング溝刻設工程と、該アンダーコート膜と前記トリミング溝を覆うようにオーバーコート膜を形成するオーバーコート膜形成工程と、前記表電極膜下層を覆うように表面電極膜上層を形成する表電極膜上層形成工程と、前記絶縁基板の一次方向の分割スリットに沿って短冊状にブレークする絶縁基板分割工程と、前記絶縁基板の左右両端面を覆い、かつ前記裏電極膜及び表電極膜下層の一部を重畳するように端面電極膜を形成する端面電極膜形成工程と、前記絶縁基板を二次方向の分割スリットに沿って個々のチップ状に分割するチップ状分割工程と、前記裏電極膜、表電極膜上層、及び端面電極膜を覆うように電気めっき膜を形成する電極めっき膜形成工程とを含むチップ形抵抗器の製造方法であって、A back and front electrode film lower layer forming step for forming a back electrode film and a front electrode film on both sides in the longitudinal direction of the back surface and the front surface of the insulating substrate, and a resistor for forming a resistor film by connecting between the front electrode film lower layer A body film forming step, an undercoat film forming step for forming an undercoat film so as to cover the resistor film, a trimming groove engraving step for engraving a trimming groove on the undercoat film, and the undercoat film And an overcoat film forming step of forming an overcoat film so as to cover the trimming groove, a surface electrode film upper layer forming step of forming a surface electrode film upper layer so as to cover the surface electrode film lower layer, and a primary of the insulating substrate An insulating substrate dividing step for breaking in a strip shape along the direction dividing slit, and an end face electrode so as to cover both left and right end faces of the insulating substrate and to overlap a part of the back electrode film and the lower layer of the front electrode film An end face electrode film forming step, a tip-like splitting step for splitting the insulating substrate into individual chips along secondary-direction split slits, the back electrode film, the top electrode film upper layer, and the end face electrode film An electrode plating film forming step of forming an electroplating film so as to cover the chip resistor,
前記トリミング溝刻設工程前の表電極膜下層形成工程が、二次方向の分割スリットだけでなく一次方向の分割スリットに対しても所定距離離間した位置までの領域に形成しており、かつ前記裏電極膜形成と表電極膜上層形成の各工程では、一次方向と二次方向共に分割スリットを跨いで形成するとともに、その跨いで形成した裏電極膜と表電極膜上層を一次方向の分割スリットに沿って分断する分断工程を前記絶縁基板分割工程前に行うようにしたことを特徴とするチップ形抵抗器の製造方法。The surface electrode film lower layer forming step before the trimming groove engraving step is formed in a region up to a position separated by a predetermined distance not only in the secondary direction split slit but also in the primary direction split slit, and In each step of the back electrode film formation and the front electrode film upper layer formation, both the primary direction and the secondary direction are formed across the split slit, and the back electrode film and the upper layer of the front electrode film formed across the split slit are formed in the primary direction. A method of manufacturing a chip resistor, characterized in that a dividing step of dividing along the insulating substrate is performed before the insulating substrate dividing step.
前記裏電極膜および表電極膜下層を導電性のメタルグレーズ系の膜とし、前記表電極膜上層を導電性レジン系の膜とし、前記アンダーコート膜をガラス系の膜とし、前記オーバーコート膜をレジン系の膜とし、前記裏電極膜、表電極膜下層、表電極膜上層、アンダーコート膜およびオーバーコート膜の各形成工程のいずれかに続いて、レーザ工法による裏電極膜のみの分断を行うことを特徴とする請求項に記載のチップ形抵抗器の製造方法。The back electrode film and the lower layer of the front electrode film are conductive metal glaze films, the upper layer of the front electrode film is a conductive resin film, the undercoat film is a glass film, and the overcoat film is The resin-based film is used, and after the back electrode film, the surface electrode film lower layer, the surface electrode film upper layer, the undercoat film, and the overcoat film are formed, only the back electrode film is divided by a laser method. The method of manufacturing a chip resistor according to claim 1 . 前記裏電極膜、表電極膜下層および表電極膜上層をメタルグレーズ系の膜とし、前記アンダーコート膜およびオーバーコート膜をガラス系の膜とし、前記オーバーコート膜の形成工程に続いて、レーザ工法による前記裏面電極膜、表電極膜下層、表電極膜上層、アンダーコート膜およびオーバーコート膜の分断を行うことを特徴とする請求項に記載のチップ形抵抗器の製造方法。The back electrode film, the lower layer of the front electrode film and the upper layer of the front electrode film are metal glaze-based films, the undercoat film and the overcoat film are glass-based films, and following the formation process of the overcoat film, a laser method 2. The method of manufacturing a chip resistor according to claim 1 , wherein the back electrode film, the surface electrode film lower layer, the surface electrode film upper layer, the undercoat film, and the overcoat film are divided by the step.
JP2001029323A 2001-02-06 2001-02-06 Manufacturing method of chip resistor Expired - Lifetime JP4504577B2 (en)

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Publication number Priority date Publication date Assignee Title
CN110600216A (en) * 2019-07-19 2019-12-20 丽智电子(南通)有限公司 Method for manufacturing thick film resistor

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JP5481675B2 (en) * 2009-10-21 2014-04-23 コーア株式会社 Chip resistor for built-in substrate and manufacturing method thereof
JP7117114B2 (en) * 2018-03-05 2022-08-12 ローム株式会社 chip resistor

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JPH04144203A (en) * 1990-10-05 1992-05-18 Aoi Denshi Kk Manufacture of chip resistor
JPH0774007A (en) * 1993-06-29 1995-03-17 Kyocera Corp Manufacture of fixed resistor
JPH08236325A (en) * 1996-01-16 1996-09-13 Hokuriku Electric Ind Co Ltd Chip resistor manufacturing method
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JPH04144203A (en) * 1990-10-05 1992-05-18 Aoi Denshi Kk Manufacture of chip resistor
JPH0774007A (en) * 1993-06-29 1995-03-17 Kyocera Corp Manufacture of fixed resistor
JPH08236325A (en) * 1996-01-16 1996-09-13 Hokuriku Electric Ind Co Ltd Chip resistor manufacturing method
JP2000269010A (en) * 1999-03-15 2000-09-29 Kamaya Denki Kk Manufacture of chip resistor, and the chip resistor

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Publication number Priority date Publication date Assignee Title
CN110600216A (en) * 2019-07-19 2019-12-20 丽智电子(南通)有限公司 Method for manufacturing thick film resistor

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