WO2016031441A1

WO2016031441A1 - Board internal layer chip component and embedded circuit board

Info

Publication number: WO2016031441A1
Application number: PCT/JP2015/070870
Authority: WO
Inventors: 松本　健太郎; 秀和唐澤
Original assignee: Koa株式会社
Priority date: 2014-08-26
Filing date: 2015-07-22
Publication date: 2016-03-03
Also published as: JP2016046460A

Abstract

Provided are an inexpensive board internal layer chip component having a simple structure and an embedded circuit board allowing a via hole to reliably make contact with an electrode of the chip component and suitable for a high-density mounting. In the embedded circuit board of the present invention, a chip component (1) buried in the resin layer (10) of a base board is equipped with: an upper surface connection portion (3) formed as one continuous plane accounting for 80 % or more of the upper surface of a substrate (2); a lower surface connection portion (4) formed as one continuous plane accounting for 80 % or more of the lower surface of the substrate (2); and a conduction portion (5) for conducting the upper surface connection portion (3) and the lower surface connection portion (4). A wiring pattern (11) provided on the upper surface of the resin layer (10) is conducted through a connection via (13) to an upper external electrode (6) covering the upper surface connection portion (3), and a wiring pattern (12) provided on the lower surface of the resin layer (10) is conducted through a connection via (14) to a lower external electrode (6) covering the lower surface connection portion (4).

Description

Chip component for inner layer of substrate and circuit board with built-in component

The present invention relates to a chip component for a substrate inner layer used by being embedded in a laminated circuit board or the like, and a component built-in circuit substrate in which such a chip component is embedded in an insulating resin layer.

In recent years, as electronic devices have become smaller and lighter and the circuit configuration has become more complex, chip components such as chip resistors are mounted not only on the surface of the circuit board but also on the inner layer to increase the component mounting density. Molded circuit boards are in practical use.

In this type of component-embedded circuit board, a chip component is usually embedded in a base substrate made of an insulating resin layer, and then a laser beam is irradiated to the resin layer to form a via hole, and a copper hole is formed in the via hole. By forming a connection via made of a plating process or the like, the connection via is connected to the electrode of the chip component formed in the inner layer.

Conventionally, external electrodes having a large area are formed on the front and back surfaces of a chip resistor that is a chip component for an inner layer of a substrate, and via holes are formed toward the external electrodes on the front and back surfaces to form an inner layer. A component-embedded circuit board has been proposed in which electrical connection is made between upper and lower wiring patterns of a base substrate via a chip component (see, for example, Patent Document 1).

FIG. 10 is a cross-sectional view of the chip resistor (chip component for substrate inner layer) disclosed in Patent Document 1, and as shown in FIG. 10, this chip resistor 100 includes a rectangular parallelepiped insulating substrate 101, A pair of first internal electrodes 102 formed at both ends in the longitudinal direction on the surface of the insulating substrate 101, a resistance film 103 formed so as to straddle the first internal electrodes 102, and a part of the first internal electrodes 102 And a protective film 104 formed so as to cover the entire resistance film 103, a second internal electrode 105 formed so as to cover the exposed portion of the first internal electrode 102 and the end of the protective film 104, An end surface of the insulating substrate 101 so that the pair of third internal electrodes 106 formed at both ends in the longitudinal direction on the back surface of the insulating substrate 101 and the first to third

internal electrodes

102, 105, 106 communicate with each other. A pair of end faces conductive layer 107 formed, is constituted by a U-shaped cross-section of the external electrodes 108 to continuously cover the second internal electrode 105 and the end surface conductive layer 107 and the third internal electrode 106.

The first internal electrode 102 is made of an Ag—Pd-based conductor, and the resistance film 103 is made of a thick film resistor whose main component is RuO ₂ or the like. The protective film 104 is an insulating layer such as glass or resin. Since the protective film 104 is formed so as to cover the resistance film 103 with a part of the first internal electrode 102 exposed, the first internal electrode There is a step between the exposed portion of 102 and the end face of the protective film 104. The second internal electrode 105 is made of an Ag-based conductor, and the first internal electrode 102 and the second internal electrode 105 form a surface-side internal electrode having a two-layer structure. Since the second internal electrode 105 covers the exposed portion of the first internal electrode 102 and the end portion of the protective film 104, the surface of the second internal electrode 105 is a wide flat surface. The third internal electrode 106 is made of an Ag-based conductor, and the third internal electrode 106 is formed in the same size at a position corresponding to the second internal electrode 105. The end face conductive layer 107 is made of a Ni—Cr thin film formed by sputtering, and the external electrode 108 is made of a single layer of Cu plating layer or a stacked Ni plating layer and Cu plating layer.

FIG. 11 is a cross-sectional view of a component-embedded circuit board having the chip resistor 100 configured as described above as an inner layer. The chip resistor 100 includes first to third

internal electrodes

102, 105, 106 inside the external electrode 108. Etc. are schematically drawn with omission of etc.

As shown in FIG. 11A, the chip resistor 100 is embedded in an insulating layer 200 of a base substrate such as a laminated circuit board, and

wiring patterns

201 and 202 are formed on the upper and lower surfaces of the insulating layer 200, respectively. Is provided. Of the pair of external electrodes 108 formed on the chip resistor 100, the surface of the external electrode 108 on the left side in the drawing and the wiring pattern 201 on the upper surface side are electrically connected via the connection via 203. The wiring pattern 202 on the back surface and the bottom surface is electrically connected through the connection via 204. These

connection vias

203 and 204 are formed by irradiating the insulating layer 200 with laser light to form via holes, and then performing copper plating or the like in the via holes.

In the component-embedded circuit board configured as described above, electrodes (external electrodes 108) that are electrically connected to the

connection vias

203 and 204 are formed on both front and back surfaces of the chip resistor 100, and the wiring of the insulating layer 200 is formed from these electrodes. Since direct connection to the

patterns

201 and 202 is possible, high-density mounting can be realized as compared with the case where the upper and

lower wiring patterns

201 and 202 are made conductive by connection vias penetrating the insulating layer 200. In addition, since the pair of external electrodes 108 provided in the chip resistor 100 are formed as wide electrodes having the same size on both the front and back surfaces, when forming the via hole by irradiating the insulating layer 200 with laser light, Even if the formation position is slightly deviated from the normal position, the electrode of the chip resistor 100 and the via hole can be reliably connected.

International Publication No. 2013/137338

As described above, the chip resistor (chip component for substrate inner layer) 100 disclosed in Patent Document 1 includes the external electrodes 108 connected to the

connection vias

203 and 204 on both the front surface and the back surface. In order to ensure that the via hole is in contact with the external electrode 108, the external electrode 108 needs to be a flat surface having a large area. For this reason, the surface-side internal electrode has a two-layer structure of the first internal electrode 102 and the second internal electrode 105 to form a flat external electrode 108 that is wide and has no step, but the structure is complicated. As a result, there was a problem that the manufacturing cost also increased.

In the component built-in circuit board disclosed in Patent Document 1, as shown in FIG. 11A, the connection via 203 connected to the wiring pattern 201 on the upper surface side of the insulating layer 200 and the wiring pattern 202 on the lower surface side are provided. The connection via 204 to be connected is connected to the separate external electrodes 108 of the chip resistor 100 and arranged in parallel. As shown in FIG. 11B, either of these

connection vias

203 and 204 is selected. It is also conceivable to connect to one external electrode 108 and arrange it on a straight line. In that case, the other external electrode 108 becomes an unnecessary region that is not involved in the connection of the via hole. However, since the entire chip resistor 100 including the region is embedded in the insulating layer 200, the mounting region is greatly reduced. Will be hindered.

The present invention has been made in view of the situation of the prior art as described above, and a first object thereof is to provide an inexpensive and simple structure chip component for an inner layer of a substrate, and a second object is to provide a chip. It is an object of the present invention to provide a component-embedded circuit board suitable for high-density mounting, in which via holes can be reliably brought into contact with component electrodes.

In order to achieve the first object, a chip component for an inner layer of a substrate according to the present invention is provided on a base body having upper and lower flat surfaces, an upper surface connecting portion provided on the upper surface of the base body, and a lower surface of the base body. The lower surface connecting portion, and the upper surface connecting portion and a conductive portion that conducts the lower surface connecting portion, and the upper surface connecting portion is formed as one continuous plane that occupies 80% or more of the upper surface of the base body, and The lower surface connecting portion is formed as one continuous plane that occupies 80% or more of the lower surface of the base.

In the chip component for the inner layer of the substrate thus configured, one continuous plane in which the upper surface connecting portion existing on the upper surface of the substrate and the lower surface connecting portion existing on the lower surface occupy 80% or more of the plane (upper surface or lower surface) of the substrate. Therefore, when a via hole is formed by embedding the chip component in a resin layer such as a laminated circuit board, the via hole is easily and reliably formed in the wide and flat upper surface connection portion and lower surface connection portion. Can be contacted. In addition, since the substrate inner layer chip component has a simple structure in which the upper surface connection portion and the lower surface connection portion provided on both surfaces of the base body are electrically connected by the conductive portion, the manufacturing process is simplified and the chip for the substrate inner layer is inexpensive. Parts can be realized.

In the above configuration, it is possible to use a conductive plate such as copper or nichrome as the base. However, if a ceramic substrate is used as the base, an upper surface connection portion, a lower surface connection portion, etc. Can be formed at once, and a chip component for an inner layer of a substrate excellent in mass productivity can be realized.

In this case, the upper surface connecting portion, the lower surface connecting portion, and the conducting portion are formed by printing and baking a conductive paste, and the conducting portion is filled in a through-hole or notch formed in the ceramic substrate. Since all of the connecting portion, the lower surface connecting portion, and the conducting portion can be formed in a thick film, it is not necessary to form the conducting portion by sputtering, and the manufacturing process can be simplified.

In order to achieve the second object, the component-embedded circuit board according to the present invention includes a component-embedded circuit board in which a chip component is embedded in an inner layer of a base substrate made of an insulating resin layer. The chip component has an upper surface connection portion and a lower surface connection portion that occupy 80% or more of the planar shape of the base, a via hole reaching the upper surface connection portion from a wiring pattern on the upper surface side, and a lower surface side Via holes reaching the lower surface connection portion from the wiring pattern are formed, and connection vias are filled in the via holes.

In the component-embedded circuit board configured in this way, the chip component embedded in the resin layer of the base substrate has an upper surface connection portion and a lower surface connection portion that occupy 80% or more of the planar shape of the base body. When forming a via hole by irradiating the resin layer with laser light, even if the via hole formation position slightly deviates from the normal position, the via hole can be easily formed on the wide and flat upper surface connection portion and lower surface connection portion. And it can contact reliably. In addition, since the chip components that are the inner layer have electrodes (upper surface connection portion and lower surface connection portion) on almost the entire upper surface and lower surface of the substrate, there is almost no unnecessary area that is not involved in via hole connection, and the mounting area Can be greatly reduced.

According to the present invention, a chip component for an inner layer of a substrate having a simple structure can be provided at low cost, and a via hole can be reliably brought into contact with an electrode of the chip component and is suitable for high-density mounting. A substrate can be provided.

It is a top view of the chip | tip component for board | substrate inner layers which concerns on the example of 1st Embodiment of this invention. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. It is explanatory drawing which shows the manufacturing process of this chip component. It is sectional drawing of the component built-in type circuit board by which this chip component was layered. It is a top view of the chip component for board inner layers concerning the example of a 2nd embodiment of the present invention. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. It is a top view of the chip component for board inner layers concerning the example of a 3rd embodiment of the present invention. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. FIG. 8 is a sectional view taken along line IX-IX in FIG. 7. It is sectional drawing of the chip component for board | substrate inner layers which concerns on a prior art example. It is sectional drawing of the component built-in type circuit board by which this chip component was layered.

Embodiments of the invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, a chip component for an inner substrate (hereinafter referred to as a chip component) 1 according to a first embodiment of the present invention includes a rectangular parallelepiped base 2 having a flat top and bottom, and a base 2, an upper surface connection portion 3 provided on the upper surface of the substrate 2, a lower surface connection portion 4 provided on the lower surface of the base 2, a conduction portion 5 that bridges the upper surface connection portion 3 and the lower surface connection portion 4, and these upper surface connection portions 3. And an external electrode 6 that covers the lower surface connection portion 4 and the conduction portion 5.

The substrate 2 is made of a ceramic substrate, and the substrate (ceramic substrate) 2 is obtained by dividing a large-size substrate, which will be described later, along a primary dividing groove and a secondary dividing groove extending vertically and horizontally.

Each of the upper surface connection portion 3 and the lower surface connection portion 4 is obtained by screen-printing an Ag-based paste, and drying and firing. The upper surface connection portion 3 is one piece that occupies almost the entire area (80% or more) of the upper surface of the base 2. It is formed as a continuous plane. The lower surface connecting portion 4 is formed as one continuous plane that occupies almost the entire area (80% or more) of the lower surface of the base 2, and the upper surface connecting portion 3 and the lower surface connecting portion 4 are opposed to each other with the base 2 interposed therebetween.

The conducting portion 5 is formed by sputtering Ni / Cr or the like on both end surfaces along the longitudinal direction of the base 2, and the upper surface connecting portion 3 and the lower surface connecting portion 4 are electrically connected by the conducting portion 5. The external electrode 6 is formed by applying Cu plating, Au plating or the like on the surfaces of the upper surface connection portion 3, the lower surface connection portion 4, and the conduction portion 5, and most of the outer surface of the chip component 1 is formed by the external electrode 6. Covered.

Next, a manufacturing method of the chip part 1 configured as described above will be described with reference to FIG. 3A to 3D are plan views in the respective steps, and the right portion is a cross-sectional view corresponding thereto.

First, as shown in FIG. 3A, a large substrate 1A having a primary division groove and a secondary division groove extending in a lattice shape is prepared. The front and back surfaces of the large-sized substrate 1A are partitioned into a large number of chip formation regions by these primary division grooves and secondary division grooves, and each chip formation region becomes a substrate (ceramic substrate) 2 for one piece. FIG. 3 representatively shows one chip formation region, but actually, such chip formation regions are arranged in a lattice pattern. In FIG. 3, both the left and right short sides of the large substrate (chip forming region) 1A are located on the primary divided groove, and the upper and lower long sides are located on the secondary divided groove.

Next, as shown in FIG. 3B, a rectangular upper surface connection portion 3 is formed on the upper surface of the large-sized substrate 1A by screen-printing Ag paste on the upper and lower surfaces of the large-sized substrate 1A, and drying and firing the paste. At the same time, a rectangular lower surface connection portion 4 is formed on the lower surface of the large substrate 1A. The upper surface connection portion 3 and the lower surface connection portion 4 extend to the primary division grooves (the left and right short sides) of the large-sized substrate 1A in order to ensure connection with the conduction portion 5 described later. In order to facilitate the dividing operation, the secondary dividing groove (upper and lower long sides) is not reached. As a result, there are non-connected regions where the upper surface connection portion 3 and the lower surface connection portion 4 are not formed on both the upper and lower surfaces of the large-sized substrate 1A. And the lower surface connecting portion 4 may be formed as one continuous plane that occupies 80% or more of the planar shape of the base 2.

Thereafter, the large substrate 1A is primarily divided into strips along the primary dividing grooves to obtain a strip-shaped substrate having a width dimension between the left and right short sides of the chip formation region. In the next step, Ni / Cr or the like is sputtered onto the divided surface of the strip-shaped substrate 2B, thereby connecting the upper surface connection portion 3 and the lower surface connection portion 4 as shown in FIG. 3C. Part 5 is formed.

Next, the strip-shaped substrate 2B is secondarily divided along the second divided grooves to obtain individual pieces (chips) having the same size as the chip component 1. As described above, at this time, each chip formation region of the large-sized substrate 1 </ b> A becomes one substrate 2. Finally, by applying Cu plating, Au plating, or the like to the upper surface connection portion 3, the lower surface connection portion 4, and the conduction portion 5 of each chip alone, as shown in FIG. The chip component 1 having the external electrode 6 on the end face is completed. As described above, since the upper surface connection portion 3 and the lower surface connection portion 4 are formed as one continuous plane that occupies 80% or more of the planar shape of the base 2, the external electrode 6 is formed on the upper surface and the lower surface of the chip component 1. Each of them has a size that occupies 80% or more.

FIG. 4 is a cross-sectional view of a component-embedded circuit board in which the chip component 1 configured as described above is formed as an inner layer. The chip component 1 omits the upper surface connection portion 3 and the lower surface connection portion 4 inside the external electrode 6. It is drawn schematically.

As shown in FIG. 4, the chip component 1 is embedded in an insulating layer 10 of a base substrate such as a laminated circuit board, and

wiring patterns

11 and 12 are provided on the upper surface and the lower surface of the insulating layer 10, respectively. Yes. The wiring pattern 11 on the upper surface side is electrically connected to the upper external electrode 6 that covers the upper surface connection portion 3 via the connection via 13, and the lower wiring pattern 12 covers the lower surface connection portion 4 via the connection via 14. The external electrode 6 is electrically connected. These connection vias 13 and 14 are formed by irradiating the insulating layer 10 with laser light to form via holes and then performing copper plating or the like in the via holes.

In the component-embedded circuit board configured as described above, the chip component 1 embedded in the resin layer 10 of the base substrate has the external electrode 6 having a size that occupies 80% or more of the upper surface and the lower surface. Even when the via hole is formed by irradiating the resin layer 10 with laser light, even if the formation position of the via hole is slightly deviated from the regular position, the wide and flat external formed on the upper surface and the lower surface of the chip part 1 The via hole can be easily and reliably brought into contact with the electrode 6. In addition, since the inner layer of the chip component 1 has the outer electrode 6 in almost the entire upper and lower surfaces, there is almost no unnecessary region not involved in the connection of the via hole, and the mounting region is greatly reduced. be able to.

As described above, in the chip component (chip component for substrate inner layer) 1 according to the first embodiment, the upper surface connecting portion 3 existing on the upper surface of the base body 2 and the lower surface connecting portion 4 existing on the lower surface of the base body 2 respectively. Since it is formed as one continuous plane that occupies 80% or more of the plane (upper surface or lower surface), when the chip component 1 is embedded in the resin layer 10 such as a laminated circuit board to form a via hole, the upper surface connection The via hole can be easily and reliably brought into contact with the wide and flat external electrode 6 covering the portion 3 and the lower surface connecting portion 4. In addition, since the chip component 1 has a simple structure in which the upper surface connection portion 3 and the lower surface connection portion 4 provided on the upper and lower surfaces of the base 2 are bridged by the conductive portion 5, the manufacturing process is simplified and the cost is low. The chip component 1 can be realized.

Further, in the chip component 1 according to the first embodiment, a ceramic substrate is used as the base 2, and after the upper surface connection portion 3 and the lower surface connection portion 4 are collectively formed on the large substrate 1A made of a ceramic substrate, Since the conductive portion 5 is formed on the dividing surface of the strip-shaped substrate 2B obtained by first dividing the large-sized substrate 1A, and then a large number of strip-shaped substrates 2B can be obtained by secondary division, mass production. It is possible to realize a chip component 1 having excellent performance.

FIG. 5 is a plan view of a chip component (chip component for a substrate inner layer) 20 according to a second embodiment of the present invention, and FIG. 6 is a cross-sectional view of the chip component 20, in a portion corresponding to FIGS. 1 and 2. Are given the same reference numerals.

The second embodiment is different from the first embodiment described above in that a through hole 2a in which a conducting portion 5 that bridges the upper surface connecting portion 3 and the lower surface connecting portion 4 is formed in the central portion of the base 2 is provided. The rest of the configuration is basically the same. That is, a through hole 2a is formed in the central portion of the substrate 2 made of a ceramic substrate, and when the upper surface connection portion 3 and the lower surface connection portion 4 are formed by screen printing Ag-based paste on the upper and lower surfaces of the substrate 2. Then, by filling the inside of the through hole 2 a with the Ag-based paste to form the conduction part 5, the upper surface connection part 3 and the lower surface connection part 4 are made conductive by the conduction part 5. Note that the Ag-based paste that forms the conductive portion 5 does not necessarily fill the entire inside of the through-hole 2a. In order to reduce the material of the Ag-based paste, the Ag-based paste is applied to the inner side surface of the through-hole 2a. It is also possible to form the conductive portion 5 by adhering.

In the chip component 20 according to the second embodiment configured as described above, all of the upper surface connection portion 3, the lower surface connection portion 4, and the conduction portion 5 are thick in addition to the operational effects of the first embodiment described above. Since it can be formed, there is no need to form the conductive portion 5 by sputtering, and the manufacturing process can be further simplified.

FIG. 7 is a plan view of a chip component (chip component for a substrate inner layer) 30 according to a third embodiment of the present invention, and FIGS. 8 and 9 are cross-sectional views of the chip component 30, corresponding to FIGS. The same reference numerals are given to the parts to be performed.

This third embodiment is different from the first embodiment described above in that a notch 2b in which a conducting portion 5 that bridges the upper surface connecting portion 3 and the lower surface connecting portion 4 is provided in the vicinity of the end surface of the base 2 is provided. The other components are basically the same except that they are formed inside. That is, semicircular cutouts 2b are provided at both longitudinal ends of the substrate 2 made of a ceramic substrate, and Ag-based paste is screen-printed on both the upper and lower surfaces of the substrate 2 to connect the upper surface connection portion 3 and the lower surface connection portion. 4, the Ag-based paste is attached to the inner side surface of the notch 2 b to form the conductive portion 5, whereby the upper surface connecting portion 3 and the lower surface connecting portion 4 are made conductive by the conductive portion 5. ing.

In the chip component 30 according to the third embodiment configured as described above, in addition to the operation and effect of the second embodiment described above, when the chip component is sucked (pickup) when the component is mounted, the through hole is formed in the suction portion. Since it becomes easy to form a continuous plane, the chip component can be picked up reliably. Further, since the notch 2b is formed at a position straddling the primary dividing groove of the large substrate 1A, the breaking stress when the large substrate 1A is divided along the primary dividing groove is reduced, and the primary dividing operation is easily performed. There is an additional effect of being able to.

In each of the above embodiments, the case where the upper surface connection portion 3 and the lower surface connection portion 4 are formed thick on the upper and lower surfaces of the substrate 2 made of a ceramic substrate has been described. However, the substrate 2 is made of Nichrome with a copper plate or Cu plating. It is also possible to use a conductive plate material such as a plate. In this case, the upper and lower surfaces of the base body are the upper surface connection portion and the lower surface connection portion, and the base body itself functions as a conduction portion. Therefore, each of the upper surface connection portion and the lower surface connection portion is one continuous plane that occupies 100% of the base surface. Will be formed.

DESCRIPTION OF

SYMBOLS

1,20,30 Chip component for board | substrate inner layer 2 Base | substrate 2a Through- hole 2b Notch 2A Large format board 2B Strip board 3 Upper surface connection part 4 Lower surface connection part 5 Conductive part 6 External electrode 10 Insulating

layer

11, 12

Wiring pattern

13, 14 Connecting via

Claims

A base body having a flat top and bottom, an upper surface connection portion provided on the upper surface of the base body, a lower surface connection portion provided on the lower surface of the base body, and a conduction portion that conducts the upper surface connection portion and the lower surface connection portion. With
The upper surface connection portion is formed as one continuous plane that occupies 80% or more of the upper surface of the substrate, and the lower surface connection portion is formed as one continuous plane that occupies 80% or more of the lower surface of the substrate. A chip component for an inner layer of a substrate.
2. The method according to claim 1, wherein the base is made of a ceramic substrate, and the upper surface connection portion, the lower surface connection portion, and the conductive portion are formed by printing and baking a conductive paste, and the conductive portion is formed on the ceramic substrate. A chip component for an inner layer of a substrate, which is filled in a formed through hole or notch.
In a component-embedded circuit board in which chip components are embedded in the inner layer of a base substrate made of an insulating resin layer,
The chip component has an upper surface connection portion and a lower surface connection portion that occupy 80% or more of the planar shape of the base, a via hole reaching the upper surface connection portion from a wiring pattern on the upper surface side, and a lower surface A circuit board with a built-in component, wherein via holes reaching the lower surface connection portion from the wiring pattern on the side are formed, and connection vias are filled in the via holes.