JP6693133B2 - 成膜シミュレーション方法、プログラム、および半導体加工システム - Google Patents

成膜シミュレーション方法、プログラム、および半導体加工システム Download PDF

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Publication number
JP6693133B2
JP6693133B2 JP2016004259A JP2016004259A JP6693133B2 JP 6693133 B2 JP6693133 B2 JP 6693133B2 JP 2016004259 A JP2016004259 A JP 2016004259A JP 2016004259 A JP2016004259 A JP 2016004259A JP 6693133 B2 JP6693133 B2 JP 6693133B2
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Prior art keywords
film
raw material
material particles
film formation
migration
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JP2016004259A
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Japanese (ja)
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JP2017126632A5 (enExample
JP2017126632A (ja
Inventor
信行 久保井
信行 久保井
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Sony Corp
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Sony Corp
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Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2016004259A priority Critical patent/JP6693133B2/ja
Priority to US16/067,754 priority patent/US10929579B2/en
Priority to KR1020187017536A priority patent/KR102671517B1/ko
Priority to PCT/JP2016/080993 priority patent/WO2017122404A1/ja
Publication of JP2017126632A publication Critical patent/JP2017126632A/ja
Publication of JP2017126632A5 publication Critical patent/JP2017126632A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Vapour Deposition (AREA)
  • Physical Vapour Deposition (AREA)
JP2016004259A 2016-01-13 2016-01-13 成膜シミュレーション方法、プログラム、および半導体加工システム Active JP6693133B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2016004259A JP6693133B2 (ja) 2016-01-13 2016-01-13 成膜シミュレーション方法、プログラム、および半導体加工システム
US16/067,754 US10929579B2 (en) 2016-01-13 2016-10-19 Film formation simulation method, program, and semiconductor processing system
KR1020187017536A KR102671517B1 (ko) 2016-01-13 2016-10-19 성막 시뮬레이션 방법, 프로그램 및 반도체 가공 시스템
PCT/JP2016/080993 WO2017122404A1 (ja) 2016-01-13 2016-10-19 成膜シミュレーション方法、プログラム、および半導体加工システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016004259A JP6693133B2 (ja) 2016-01-13 2016-01-13 成膜シミュレーション方法、プログラム、および半導体加工システム

Publications (3)

Publication Number Publication Date
JP2017126632A JP2017126632A (ja) 2017-07-20
JP2017126632A5 JP2017126632A5 (enExample) 2019-02-14
JP6693133B2 true JP6693133B2 (ja) 2020-05-13

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Family Applications (1)

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JP2016004259A Active JP6693133B2 (ja) 2016-01-13 2016-01-13 成膜シミュレーション方法、プログラム、および半導体加工システム

Country Status (4)

Country Link
US (1) US10929579B2 (enExample)
JP (1) JP6693133B2 (enExample)
KR (1) KR102671517B1 (enExample)
WO (1) WO2017122404A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12557601B2 (en) 2019-05-07 2026-02-17 Sony Semiconductor Solutions Corporation Defect density calculation method, defect-density calculation program, defect-density calculation apparatus, heat treatment control system and machining control system
JP2023180839A (ja) * 2022-06-10 2023-12-21 ソニーセミコンダクタソリューションズ株式会社 成膜シミュレーション方法、成膜シミュレーションプログラム、成膜シミュレータおよび成膜装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2658840B2 (ja) * 1993-12-01 1997-09-30 日本電気株式会社 プロセスシミュレータおよびこれを用いたｃｖｄ装置およびプロセスシミュレーション方法
JP2000195766A (ja) * 1998-12-25 2000-07-14 Toshiba Corp シミュレ―ション装置、シミュレ―ション方法、シミュレ―ションプログラムを格納した記録媒体および固体電子装置の製造方法
JP4928694B2 (ja) * 2001-09-18 2012-05-09 三菱重工業株式会社 薄膜多結晶の膜構造同定方法
JP5428450B2 (ja) * 2009-03-30 2014-02-26 ソニー株式会社 イオン照射ダメージの予測方法とイオン照射ダメージのシミュレータ、およびイオン照射装置とイオン照射方法

Also Published As

Publication number Publication date
KR20180102551A (ko) 2018-09-17
US20190005170A1 (en) 2019-01-03
KR102671517B1 (ko) 2024-06-04
JP2017126632A (ja) 2017-07-20
US10929579B2 (en) 2021-02-23
WO2017122404A1 (ja) 2017-07-20

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