JP6674699B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP6674699B2
JP6674699B2 JP2015168893A JP2015168893A JP6674699B2 JP 6674699 B2 JP6674699 B2 JP 6674699B2 JP 2015168893 A JP2015168893 A JP 2015168893A JP 2015168893 A JP2015168893 A JP 2015168893A JP 6674699 B2 JP6674699 B2 JP 6674699B2
Authority
JP
Japan
Prior art keywords
functional module
node
power switch
leak
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015168893A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017046276A5 (enExample
JP2017046276A (ja
Inventor
竹内　幹
幹 竹内
満彦 五十嵐
満彦 五十嵐
小笠原　誠
誠 小笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2015168893A priority Critical patent/JP6674699B2/ja
Priority to US15/216,883 priority patent/US10211620B2/en
Publication of JP2017046276A publication Critical patent/JP2017046276A/ja
Publication of JP2017046276A5 publication Critical patent/JP2017046276A5/ja
Application granted granted Critical
Publication of JP6674699B2 publication Critical patent/JP6674699B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/16—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to fault current to earth, frame or mass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/04—Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2015168893A 2015-08-28 2015-08-28 半導体装置 Active JP6674699B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015168893A JP6674699B2 (ja) 2015-08-28 2015-08-28 半導体装置
US15/216,883 US10211620B2 (en) 2015-08-28 2016-07-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015168893A JP6674699B2 (ja) 2015-08-28 2015-08-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2017046276A JP2017046276A (ja) 2017-03-02
JP2017046276A5 JP2017046276A5 (enExample) 2018-07-05
JP6674699B2 true JP6674699B2 (ja) 2020-04-01

Family

ID=58096960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015168893A Active JP6674699B2 (ja) 2015-08-28 2015-08-28 半導体装置

Country Status (2)

Country Link
US (1) US10211620B2 (enExample)
JP (1) JP6674699B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6674699B2 (ja) * 2015-08-28 2020-04-01 ルネサスエレクトロニクス株式会社 半導体装置
JP6712811B2 (ja) * 2015-09-28 2020-06-24 パナソニックＩｐマネジメント株式会社 検出回路、及び管理装置
KR102336181B1 (ko) * 2017-06-07 2021-12-07 삼성전자주식회사 누설 전류 측정 회로, 이를 포함하는 집적 회로 및 시스템
JP2019003588A (ja) * 2017-06-12 2019-01-10 正仁 櫨田 Ｃｐｕチップ上のコア・ブロックの１個が動作していなかったり、コア・ブロック内のトランジスターが熱崩壊をして異常な消費電流値を示してコア・ブロックが熱破壊した場合等に、ｃｐｕのコア・ブロックの今現在の全部の状態をレジスター群に保存してｃｐｕのコア・ブロック自体へのシステム・クロックの供給や電力供給を停止してｃｐｕ自体の発熱や消費電力を抑え、ｃｐｕの動作を元の状態に復元してプログラムを再実行する時には、外部割込みに依り、ｃｐｕのコア・ブロックにシステム・クロックを再供給してレジスター群から情報を読み込んでｃｐｕの状態を戻して、システム・クロックに従ってプログラム・カウンターの値から、メモリー上のプログラムを再起動する方法。
US10215795B1 (en) * 2018-04-13 2019-02-26 Infineon Technologies Ag Three level gate monitoring
CN111506180A (zh) * 2020-03-16 2020-08-07 广州视源电子科技股份有限公司 电源控制方法、装置、存储介质以及终端
CN113268132B (zh) * 2021-05-19 2024-09-20 维沃移动通信有限公司 供电控制方法、装置和电子设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4434510B2 (ja) 2001-03-16 2010-03-17 株式会社東芝 絶縁ゲート型半導体素子の故障検出方法および故障検出装置
JP6674699B2 (ja) * 2015-08-28 2020-04-01 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US10211620B2 (en) 2019-02-19
US20170063075A1 (en) 2017-03-02
JP2017046276A (ja) 2017-03-02

Similar Documents

Publication Publication Date Title
JP6674699B2 (ja) 半導体装置
US6603328B2 (en) Semiconductor integrated circuit
JP5761764B2 (ja) ブラウンアウト検出回路を有するデータ処理システム
US8525549B1 (en) Physical unclonable function cell and array
US11929131B2 (en) Memory device degradation monitoring
US20080034337A1 (en) integrated circuit design closure method for selective voltage binning
US11152038B2 (en) Testing one-time programmable (OTP) memory with data input capture through sense amplifier circuit
US9471120B1 (en) Power management controller for integrated circuit
Mukhopadhyay et al. Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring
WO2000011486A1 (en) Semiconductor integrated circuit
Ahmed et al. Online measurement of degradation due to bias temperature instability in SRAMs
JP2011041280A (ja) 電子回路の作動の監視
US6972999B2 (en) Semiconductor integrated circuit
US8042404B2 (en) Stress detection circuit and semiconductor chip including same
Vazquez et al. Predictive error detection by on-line aging monitoring
JP6222660B2 (ja) 論理回路
JP6735177B2 (ja) 半導体装置およびヒューズ状態検出方法
CN105895158A (zh) 芯片中的die id的读取电路以及芯片
US10054634B2 (en) Test device
US8988957B2 (en) Sense amplifier soft-fail detection circuit
JP5391955B2 (ja) 半導体装置
Ramana Kumari et al. Testing of neighborhood pattern-sensitive faults for memory
CN108320775B (zh) Sram单元及其检测方法、sram单元的检测系统和sram器件
Saha et al. High speed hardware for March C
US20200381995A1 (en) Voltage supply device and operation method thereof

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160203

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180514

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180514

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20181226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190307

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190927

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200204

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200305

R150 Certificate of patent or registration of utility model

Ref document number: 6674699

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150