JP6586152B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a resistance circuit used in a semiconductor device.

  Resistors used in a semiconductor device or a semiconductor integrated circuit include a diffused resistor in which an impurity having a conductivity type opposite to that of a semiconductor substrate is implanted into a single crystal silicon semiconductor substrate, and a polycrystalline silicon resistor made of polycrystalline silicon in which an impurity is implanted. .

2A is a plan view of a resistance circuit in which resistance elements made of conventional polycrystalline silicon are arranged in a plane, and FIG. 2B is a cross-sectional view taken along the line AA ′ in FIG. Represents.
A high concentration impurity region 6 and a low concentration impurity region 7 are formed in the polycrystalline silicon film constituting the resistance element. The resistance value of the resistance element is determined by the resistivity determined by the impurity concentration of the low-concentration impurity region 7 that has a high resistance, and its length and width, and the high-concentration impurity region 6 is used for establishing an ohmic connection with the metal wiring.

  An intermediate insulating film 8 is formed on the resistance element, and each resistance element is electrically connected by a metal wiring 10 through a contact hole 9. The resistor circuit used in the semiconductor integrated circuit is formed on the same substrate surface as shown in FIG. 3, for example, by connecting a plurality of resistor elements shown in FIG. 2 in series or in parallel via metal wiring.

  The intermediate insulating film 8 formed on the resistance element contains boron or phosphorus and is flattened through a heat treatment at 850 ° C. or higher, thereby reducing the height difference due to the film pattern in the semiconductor integrated circuit. Further, after the metal wiring is formed, a film 11 such as a silicon nitride film is provided thereon as a protective film.

  The resistive elements constituting the resistive circuit are all laid out in the same planar shape such as width and length. By doing so, each resistance element is equally subjected to the shape variation during the etching process for determining the shape, and the resistance ratio between the resistance elements can be kept constant.

  At this time, in order to change the resistance value of the resistance element and the ratio between the resistance elements according to the requirement of the resistance circuit, the resistance elements having the same shape are connected in parallel or in series as shown in FIG. Here, in order to realize a resistance circuit having resistance values of 4R, 2R, 1R, and 1 / 2R (R is the resistance value of one resistance element) in FIG. Connecting two elements in series, one resistance element, and two resistance elements in parallel are connected to each other, and a resistance circuit is formed by adjusting resistance values by using resistance groups 201 to 204 including a plurality of resistance elements. Thus, both a desired resistance ratio and high accuracy of the resistance ratio are achieved.

  In addition, in order to increase the accuracy of the resistance value, it is necessary to reduce and stabilize the influence of the ambient voltage in addition to making the machining shape uniform. This is because the polycrystalline silicon thin film is a semiconductor, and the resistance value changes due to the depletion / accumulation phenomenon caused by the surrounding potential. The solution is also included in FIG.

  First, in FIG. 2A, a metal wiring is formed on each resistance group of the resistance circuit, and a constant voltage is applied to stabilize the voltage around the resistance element, and the degree of depletion / accumulation of the resistance element. Is fixed to a constant value. Further, as shown in FIG. 2B, the metal wiring on the resistance element is formed on each resistance element group so as to cover the resistance element via the intermediate insulating film 8.

  Next, by applying a potential from one terminal of each resistance group to the potential of the metal wiring on the resistance element, a potential close to that of the resistance group is applied to minimize the influence of the ambient voltage and the degree of depletion / accumulation Is minimized.

  On the other hand, in this figure, no special measures are taken on the lower side of the resistance element group and in the semiconductor substrate, but a well region or a polycrystalline silicon electrode is formed on the lower side for each resistance group, and the potential is set to each resistance. There is a case where a method of giving from one terminal of the element group is used. This technique has a higher accuracy maintaining effect as the voltage applied to the resistance circuit is larger. (For example, see Patent Document 1)

JP 09-32229 A

The creation of the resistance element in the conventional semiconductor device has the following problems.
A metal wiring formed on a resistance element made of polycrystalline silicon has a film stress determined by a specific linear expansion coefficient and a forming temperature . Therefore, when a metal wiring is formed for each resistance element group, the stress corresponding to the area is applied to the lower resistance element group, and the polycrystalline silicon resistance value changes due to the piezoresistance effect. As a result, the resistance of each resistance element group The value deviates from a desired design value, and the balance of the resistance ratio of the resistor circuit is lost.

This stress varies depending on the type of metal, and the above-described effect becomes remarkable when a film that is easily shrunk by heat such as a refractory metal is employed.
Therefore, the conventional resistance circuit in which different metal films are formed for each resistance group has a problem that it is difficult to increase the accuracy of the resistance ratio.

In order to solve the above-described problems, the present invention has the following configuration. That is,
A low-concentration impurity region and a high-concentration impurity comprising a semiconductor substrate, a first insulating film made of a silicon oxide film formed on the semiconductor substrate, and a polycrystalline silicon thin film formed on the first insulating film A plurality of resistive elements having regions, a high-stress insulating film covering and contacting the surfaces of the plurality of resistive elements, a second insulating film covering the periphery of the high-stress insulating film, and a low concentration of the plurality of resistive elements And a plurality of metal wirings, one end of which is electrically connected to one end of the plurality of resistance elements, and the high-stress insulating film includes the plurality of resistance elements. The semiconductor device is characterized in that it is formed in a wider area than the plurality of metal wirings and has a higher compressive or tensile stress than the plurality of metal wirings.

Further, the semiconductor device is characterized by having the high-stress insulating film having a compressive or tensile stress of 500 MPa or more.
Further, the semiconductor device is characterized in that the high-stress insulating film is formed of a single layer film made of any one of SiC, SiON, and SiCN, or a multilayer film formed by combining different films.

Further, the semiconductor device is characterized in that the high-stress insulating film is a silicon nitride film formed by a low pressure CVD method.
Further, the semiconductor device is characterized in that the thickness of the high stress insulating film is 0.15 μm or more.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor integrated circuit which incorporated the highly accurate resistive element which is not influenced by the stress of metal wiring can be provided.

FIG. 2 is a schematic plan view and a schematic cross-sectional view showing a resistance circuit according to a first embodiment of the present invention. It is the model top view and schematic cross section which show the conventional resistance circuit. It is an example of the circuit diagram of a resistance circuit. It is the model top view and schematic cross section which show the resistance circuit of the 2nd Example of this invention. It is process flow sectional drawing for creating the resistance circuit of the 1st Example of this invention. FIG. 6 is a process flow cross-sectional view for creating the resistance circuit according to the first embodiment of the present invention, following FIG. 5; It is process flow sectional drawing for creating the resistance circuit of the 2nd Example of this invention. FIG. 8 is a process flow cross-sectional view for creating a resistance circuit according to a second embodiment of the present invention, following FIG. 7.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a plan view of a resistor circuit in which resistor elements that are semiconductor devices made of polycrystalline silicon according to the present invention are arranged in a plane, and FIG. 1B is a cross-sectional view taken along line BB ′ in FIG. FIG.

The electrical connection of the resistance elements constituting this resistance circuit is as shown in the circuit diagram of FIG. For example, four resistance elements are connected in series between the terminal 101 and the terminal 102.
As shown in FIG. 1 (b), the resistance element constituting this resistance circuit is formed of a polycrystalline silicon film deposited on a flat thick oxide film 2 on a semiconductor substrate 1. Further, a high stress insulating film 12 is deposited so as to sufficiently cover the upper surface and side surfaces of the resistance element.

  The polycrystalline silicon constituting the resistance element is formed with a high concentration impurity region 6 and a low concentration impurity region 7, and the resistance value of the resistance element is set to the impurity concentration of the low concentration impurity region 7 and the length thereof. It is determined by the size of the width, and the high-concentration impurity region 6 is used for ohmic connection with the metal wiring 10 as in the conventional case.

  An intermediate insulating film 8 is formed on the resistance element and the insulating film 12, and electrical connection is performed by the metal wiring 10 through the contact hole 9. At this time, although not shown, this contact hole penetrates both the intermediate insulating film 8 and the high stress insulating film 12 on the resistance element, reaches the polycrystalline silicon constituting the resistance element, and obtains electrical connection.

  A part of the metal wiring 10 is separately formed so as to cover the low-concentration impurity region 7 that determines the resistance value of the resistance element with respect to the plurality of resistance groups 201 to 204 including a plurality of resistance elements, and in the vicinity of the resistance group. As in the prior art, the voltage around the resistance element is stabilized by connecting to the terminal of the resistor, and the resistance ratio of the resistance element is increased in accuracy.

By the way, when the film constituting the metal wiring is Al-Si containing Si, although it depends on the forming method, it has a film stress derived from the forming temperature and the linear expansion coefficient, and the value is generally about 100 MPa. is there. In the absence of the high-stress insulating film 12, this stress affects the lower resistance element group via the intermediate insulating film 8 and causes resistance value fluctuations due to the piezoresistance effect. Therefore, since the metal wiring is formed in different areas for each resistance group as described above, the stress value varies depending on the area, and the resistance ratio of the resistance group deviates from a predetermined design value, leading to deterioration of resistance circuit accuracy. .

  Furthermore, in the case of a fine process, a refractory metal film such as a Ti-based material having a barrier effect is generally laminated on the base of an Al-based wiring. It has a film stress of about 200 to 500 MPa. In that case, the piezoresistive effect is more intense and acts to increase the deviation of the resistance ratio of each resistance group, causing further deterioration of the resistance circuit accuracy.

  In order to solve the problem, in the present invention, the high stress insulating film 12 having a film stress value higher than that of the metal wiring is formed so as to cover all the resistance elements. While eliminating this, both the stabilization of the ambient voltage of the resistance element is achieved and a highly accurate resistance circuit is realized.

The high-stress insulating film 12 preferably has a film stress of several hundred MPa or more, and examples thereof include films made of materials such as Si ₃ N ₄ , SiC, SiON, and SiCN. A single layer film using one of these films may be used, or a multilayer film including a plurality of films may be used. In particular, Si ₃ N ₄ produced by the low pressure CVD method has a high density, and when it is deposited to 0.15 μm, a film stress of about 1000 MPa can be realized, which is preferable for the present invention from the viewpoint of ease of formation and affinity for semiconductor processes. Although the thermal nitride film can be formed more densely, it is not preferable for the present invention because there is a limit to the formation of a thick film for obtaining a high stress.

Next, a method for manufacturing the structure of the resistor circuit of FIG. 1 according to the present invention will be described with reference to FIGS.
First, a semiconductor substrate 1 is prepared, and an insulating film 2 such as a thermal oxide film by LOCOS oxidation is formed on the semiconductor substrate 1 (FIG. 5A).

Next, a polycrystalline silicon thin film constituting the resistance element is deposited, and impurity implantation for setting the resistivity of the resistance element is performed on the entire surface of the polycrystalline silicon film on the semiconductor substrate. The resistivity of the resistance element is adjusted by this impurity implantation amount. Impurities are N-type phosphorus or arsenic, P-type boron or BF ₂ , and the impurity implantation amount is set to 1 × 10 ¹⁵ to 5 × 10 ¹⁹ atoms / cm ³ depending on the desired resistivity.

  Next, the polycrystalline silicon thin film is processed by a dry etching method or the like to determine the shape of the resistance element 7. At this time, by setting each resistive element to the same shape and the same interval, even if there are variations in photo patterning and fluctuations in plasma conditions during etching, each resistive element is affected in the same way and the resistance ratio varies. Can be suppressed (FIG. 5B).

Next, a thin film having a high stress compared with the metal film, for example, a high stress insulating film 12 made of Si ₃ N ₄ , SiC, SiON, SiCN, or the like, which is unique to the present invention, is resisted by an arbitrary method such as LPCVD or sputtering. A single layer film or a multilayer film is deposited on the semiconductor substrate including the element, and portions other than the resistance element are removed by etching (FIG. 5C). By this method, the high-stress insulating film 12 is brought into close contact with the upper surface and the side surface excluding the semiconductor substrate side of the resistance element.

Next, although not shown, a high-concentration impurity region 6 is formed in part of the polycrystalline silicon by ion implantation through another photomask process.
Next, an intermediate insulating film 8 is formed on the semiconductor substrate (FIG. 6A). As a formation method, after depositing an oxide film containing phosphorus or boron, the insulating film deposited using an etch back method, a CMP method, or the like is planarized, including a reflow method in which planarization is performed by heat treatment at 850 ° C. or higher.

Next, although not shown, a contact hole is formed by dry etching through the high stress thin film through the terminal portion of the resistance element until reaching the resistance element through a photomask process.
Next, a metal film is deposited. As the metal film, AlSi containing Al as a main component, Si containing Al, Cu containing AlCu, AlSiCu, or the like is selected as necessary. Further, a Ti-based refractory metal thin film is formed on the base of the metal thin film as necessary. Thereafter, a metal wiring 10 is formed through a photomask process (FIG. 6B).

Finally, a resistance circuit including the resistance element of the present invention is completed by depositing and patterning a passivation film 11 as a final protective film (FIG. 6C).
4A is a plan view of a resistor circuit in which resistor elements made of polycrystalline silicon are arranged in a plane according to another embodiment of the present invention, and FIG. 4B is a diagram of C in FIG. 4A. It represents a cross-sectional view along -C ′.
The electrical connections of the resistance elements constituting this resistance circuit are as shown in FIG.

  In the embodiment of FIG. 4, an insulating film 12 having a higher film stress value than the metal wiring is provided between the flat thick oxide film 2 on the semiconductor substrate 1 and the polycrystalline silicon film forming the resistance element. Arranged in the same shape as the element. Further, an insulating film 12 having a higher film stress value than the metal wiring similar to the above is formed on the resistance element so as to cover all the resistance elements. By doing so, a high-stress insulating film is arranged so as to wrap all the top, bottom, left and right directions of each resistance element, and the stress state between the films on all surfaces of the resistance element is uniformly and stabilized. I can do it. By doing so, it is possible to suppress not only the metal thin film but also the influence of external stress application other than that, and the resistance fluctuation due to the piezoresistance effect is reduced.

  Furthermore, compared with FIG. 1, the change in stress above and below the resistance element due to temperature fluctuations can be suppressed, and the reliability against physical fluctuations such as peeling and cracking due to the stress difference between the upper surface and the bottom surface of the resistance element is enhanced.

Next, a method for manufacturing the structure of the resistor circuit of FIG. 4 according to the present invention will be described with reference to FIGS. 7A to 8E.
As in FIG. 1, a semiconductor substrate 1 is first prepared, and an insulating film 2 such as a thermal oxide film by LOCOS oxidation is formed on the semiconductor substrate 1 (FIG. 7A).

Next, a thin film having a higher stress than the metal film, for example, a thin film 12 made of Si ₃ N ₄ , SiC, SiON, SiCN, etc., is deposited by an arbitrary method, and then becomes a resistance element later. A polycrystalline silicon film 14 is deposited, and then impurity implantation for setting the resistivity of the resistance element is performed on the entire surface of the polycrystalline silicon film on the semiconductor substrate. The resistivity of the resistance element is adjusted by this impurity implantation amount. The type and amount of implanted impurities are arbitrarily set as necessary (FIG. 7B), as described with reference to FIG. 5B.

Next, the shape of the resistance element 7 is processed and formed by a dry etching method or the like. At this time, the high-stress insulating film under the resistance element is simultaneously etched in a self-aligned manner (FIG. 7C).
Next, a thin film having a stress higher than that of the metal film, for example, a deposited thin film 12 made of Si ₃ N ₄ , SiC, SiON, SiCN, or the like peculiar to the present invention is applied to a semiconductor substrate including a resistance element by an arbitrary method. Then, the portion other than the resistance element is deposited by etching (FIG. 8A).

Next, although not shown, a high concentration impurity region 6 is formed in the polycrystalline silicon by ion implantation through another photomask process.
Next, although not described in detail, the intermediate insulating film 8, the contact holes, and the metal wiring 10 are formed, and the passivation film 11 that is the final protective film is deposited and patterned in the same manner as in general semiconductor manufacturing. A resistance circuit including the resistance element is completed (FIG. 8B).

  In addition, the film constituting the resistance element in the present invention is not limited to the polycrystalline silicon film, and it is needless to say that the film can be applied to other semiconductor thin films and thin film metal resistors.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Oxide film 3 Gate insulating film 4 Source / drain region 5 Gate electrode 6 Polycrystalline silicon high concentration impurity region 7 Polycrystalline silicon low concentration impurity region 8 Intermediate insulating film 9 Contact hole 10 Metal wiring 11 Passivation film 12 High stress Insulating film 13 Via hole 14 Polycrystalline silicon thin film 15 Interlayer insulating films 101 to 105 Each terminal 201 to 204 that draws an arbitrary potential from a resistor circuit

Claims (5)

A semiconductor substrate;
A first insulating film made of a silicon oxide film formed on the semiconductor substrate;
A plurality of resistance elements having a low concentration impurity region and a high concentration impurity region, each of which is formed of a polycrystalline silicon thin film formed on the first insulating film;
A high-stress insulating film that covers and covers the top and side surfaces of the plurality of resistance elements;
A second insulating film covering and covering the upper surface of the high-stress insulating film;
A plurality of metal wirings having different areas in which one end thereof is electrically connected to one end of the plurality of resistance elements;
Have
The high-stress insulating film is formed in a region wider than the plurality of metal wirings having different areas in the region where the plurality of resistance elements are disposed, and the absolute stress of the compressive stress of the plurality of metal wirings having different areas is determined. characterized in that it has a value or tensile absolute value larger compressive stress is an absolute value or absolute value or tensile absolute value is greater tensile stress than the absolute values of the stress of the compressive stress of the plurality of metal wires having the different areas, the stress Semiconductor device.   The semiconductor device according to claim 1, comprising the high-stress insulating film having a compressive stress of 500 MPa or more or a tensile stress of 500 MPa or more.   3. The semiconductor device according to claim 2, wherein the high-stress insulating film is formed of a single layer film made of any one of SiC, SiON, and SiCN, or a multilayer film formed by combining different films.   3. The semiconductor device according to claim 2, wherein the high-stress insulating film is a silicon nitride film formed by a low pressure CVD method.   The semiconductor device according to claim 4, wherein the high-stress insulating film has a thickness of 0.15 μm or more.

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