JP2008235749A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a resistor so that it cannot be affected by an electric field from a semiconductor substrate or wiring not connected to the resistor in a semiconductor device having a circuit where wires are connected by the resistor on the semiconductor substrate. <P>SOLUTION: The semiconductor device has a circuit, where first wiring 10 and second wiring 20a are connected by the resistor 14, on an n substrate (semiconductor substrate) 1. The first wiring 10 and the second wiring 20a are formed in a layer while sandwiching an insulation film 12, and the resistor 14 is formed in a via hole 13 formed in the insulation film 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a semiconductor device having a circuit in which wirings are connected by resistors on a semiconductor substrate.

Conventionally, a semiconductor device having a circuit in which wirings are connected by resistors on a semiconductor substrate is, for example,
It is manufactured by the following method. First, a resistor made of polysilicon is formed on a silicon oxide film (LOCOS film) for element isolation formed on a silicon substrate, an insulating layer is formed thereon, and the resistor and each wiring are connected to this insulating layer. A contact hole for connection is formed. next,
Each contact hole is filled with a conductive material, and a thin film made of a conductive material is formed on the insulating layer. Next, this thin film is patterned to form each wiring.

However, in the semiconductor device obtained by this method, the resistance is easily affected by the electric field from the silicon substrate, and the wiring not connected to the resistance is formed above the resistance via the insulating layer. In some cases, this resistance is easily affected by the electric field from the wiring. As a result, the resistance value of the resistor changes according to the potential of the silicon substrate and the wiring, and thus there is a problem that a stable resistance value cannot be obtained.

Patent Document 1 relates to a semiconductor device in which a resistor made of polysilicon and a wiring layer connected to the resistor are formed on a silicon substrate via a silicon oxide film in order to reduce the parasitic capacitance. It describes that a silicon nitride film is provided in a lower region of the resistance and wiring layer between the silicon oxide film and the silicon substrate.
In Patent Document 2 below, the first wiring and the second wiring are formed in layers with an insulating film interposed therebetween, and tungsten, tungsten alloy, aluminum, aluminum are formed in the via hole formed in the insulating film. A semiconductor device in which an arbitrary material selected from the group consisting of an alloy, copper, and a copper alloy is filled as a conductive plug is disclosed.
JP 2001-102532 A WO99 / 36954

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a circuit in which wirings are connected to each other by a resistor on a semiconductor substrate, so that the resistance is affected by an electric field from the semiconductor substrate or a wiring not connected to the resistor. It is to make it difficult to receive.

In order to solve the above-described problem, a semiconductor device according to a first aspect of the present invention is a semiconductor device having a circuit in which wirings are connected by resistors on a semiconductor substrate, and the first wiring and the second wiring sandwich an insulating film. And the resistor is formed in a via hole formed in the insulating film.
The invention 2 is the invention 1 characterized in that the resistor is made of amorphous silicon.

A third aspect of the present invention is characterized in that in the first or second aspect, the number of via holes is equal to a resistance value.
According to the semiconductor device of the first aspect of the present invention, since the resistor that connects the first wiring and the second wiring is formed in the via hole and is sandwiched between the two wirings, the wiring that is not connected by this resistance Is not formed at a position adjacent to this resistor in the vertical direction via the insulating layer, and this resistor is not formed immediately above the insulating layer formed immediately above the semiconductor substrate. Therefore, the resistance connecting the wiring formed on the semiconductor substrate is hardly affected by the electric field from the semiconductor substrate or the wiring not connected to the resistance, so that a stable resistance value can be obtained.

In addition, by forming a resistance in the insulating film (interlayer insulating film) between the first wiring and the second wiring,
Since it is not necessary to secure an area for forming a resistor in the substrate surface, the semiconductor device can be miniaturized.
According to the semiconductor device of the present invention, since the resistance is made of amorphous silicon, an extremely high resistance value can be realized as compared with polysilicon when not doped with impurities, and a desired resistance value can be obtained by changing the impurity concentration. realizable.

In the semiconductor device of the first aspect, the connection resistance value between the wirings is inversely proportional to the planar area of the via hole when the resistance is formed by filling the via hole with a material having the same resistance value. Therefore, for example, when n via holes having a planar area S are formed and wirings are connected by resistances in the n via holes, one via hole having a planar area S is formed. 1 / n of the case. In the semiconductor device of the invention 3, the connection resistance value between the wirings is controlled based on this idea.

Hereinafter, embodiments of the present invention will be described.
The semiconductor device according to the embodiment of the present invention can be manufactured by the following method.
This method will be described with reference to FIGS.
First, a p-well 2 is formed on an n-substrate (a silicon substrate doped with n-type impurities) 1, and a p-type diffusion layer 3 for preventing inversion is formed in the p-well 2. Next, a silicon oxide film (LOCOS film) 4 and a gate oxide film 5 for element isolation are formed. Next, after forming a gate electrode 6 made of polysilicon, an n + diffusion layer 7 and a p + diffusion layer 8 are formed. This
A CMOS composed of an nMOS on the p-well 2 and a pMOS on the n-substrate 1 is formed. FIG.
(A) shows this state.

Next, an insulating film 9 is formed on the n substrate 1 in the state of FIG.
S source / drain region (n + diffusion layer) 7 and pMOS source / drain region (p +)
A contact hole 91 for the n + diffusion layer 7 a between the diffusion layer 8 and the LOCOS film 4 is formed. Next, by depositing an AlSiCu alloy, the AlSiCu alloy is filled in the contact hole 91 and an AlSiCu alloy thin film is formed on the insulating film 9.
Next, a TiN film 11 having a thickness of about 1000 mm is formed on the alloy thin film, and these films are patterned to form the first wiring 10 having the TiN film 11 on the upper side.
FIG. 1B shows this state.

Next, an insulating film 12 is formed on the n substrate 1 in the state of FIG. 1B, and a via hole 13 for forming a resistance is formed in the insulating film 12. The via hole 13 has a constant planar shape in the depth direction in order to prevent variation in resistance value. FIG. 1 (c) shows this state.
Next, as shown in FIG. 2A, amorphous silicon is deposited in both via holes 13 by a plasma CVD method or the like and filled until the via holes 13 are almost filled. In this example, amorphous silicon is deposited in the range of room temperature to 450 ° C. The first wiring 10
And a barrier layer provided between the n + diffusion layer 7a, the temperature can be increased up to 500 ° C. The amorphous silicon filled in the via hole 13 forms the resistor 14.

Next, as shown in FIG. 2B, via holes 15 for simply connecting the upper and lower wirings are formed in the insulating film 12. The via hole 15 is filled with a wiring forming material at the same time when the upper wiring layer is formed. In order to make this material easy to fill, wet and dry combined etching is performed to taper the upper portion of the via hole 15.
Next, a TiN film 16 having a thickness of about 500 mm is formed on the n substrate 1 in the state shown in FIG. 2B, and then a resist film is formed. The resist film is formed on the via hole 13 and its peripheral portion with a resist 1
Patterning is performed so that 7 remains. FIG. 2 (c) shows this state. Etching through this resist pattern results in a portion of the TiN film 1 not covered with the resist 17.
6 is removed.

As a result, as shown in FIG. 3A, Ti is formed only on the via hole 13 and its peripheral portion.
The TiN film 16 and the TiN film 1, which have been left doubly at the bottom of the via hole 15, remain in the N film 16.
1 is also removed by etching, and the first wiring (AlSiCu alloy thin film) 10 is exposed at the bottom of the via hole 15.
Next, a TiN film 19 is formed to a thickness of about 500 mm on the n substrate 1 in the state of FIG.
As a result, the TiN film 19 is also formed on the bottom and side walls of the via hole 15, and the two layers of TiN films 16 and 19 exist on the via hole 13 and the upper part of the periphery thereof. Next, Al
A Cu alloy thin film 20 is formed, and a TiN film 21 is formed thereon. FIG. 3B shows this state.

Next, the alloy thin film 20 and the TiN films 21, 19, 16 are patterned to form the second wiring 20 a having the TiN film 21 on the upper side and the TiN film 19 on the lower side.
In the via hole 13 and the surrounding area, double TiN is formed below the second wiring 20a.
Films 16 and 19 are formed. Next, a passivation film 22 is formed on the entire surface to complete the semiconductor device. FIG. 3C shows this state.

FIG. 3C is a cross-sectional view showing the semiconductor device of this embodiment. In this semiconductor device, a first wiring 10 and a second wiring 20a are provided on an n substrate (semiconductor substrate) 1 and an insulating film 12 between the two wirings.
And a circuit connected by a resistor 14 in a via hole 13 formed in the circuit.
According to this semiconductor device, the resistor 14 that connects the first wiring 10 and the second wiring 20a includes:
Since it is formed in the via hole 13 and is sandwiched between the wirings 10 and 20a, it is difficult to be affected by the electric field from the n substrate 1, so that the resistance value of the resistor 14 is stabilized. Also, the second wiring 20
Even if the wiring on the a is not connected to the resistor 14 via an insulating film is formed, it becomes hardly affected by the electric field from the wiring, the resistance value of the resistor 14 is stabilized. Furthermore, since it is not necessary to secure an area for forming the resistor 14 in the surface of the semiconductor substrate 1, the semiconductor device can be reduced in size.

In addition, according to this semiconductor device, the TiN film 11 having a thickness of about 1000 mm is formed between the first wiring 10 and the resistor 14, and the total thickness of about 1000 mm is formed between the second wiring 20 a and the resistance 14.
Since the iN films 16 and 19 are formed, the amorphous silicon forming the resistor 14 and the wiring 1
The reaction of aluminum alloy forming 0, 20a does not occur. That is, the TiN film 11 and T
The iN films 16 and 19 function as a barrier metal layer between the wirings 10 and 20 a and the resistor 14.
Further, in this embodiment, as shown in FIG. 3B, the AlCu alloy thin film 2 is formed in a state in which only one layer of the TiN film 19 having a thickness of about 500 mm is formed on the bottom surface and the wall surface of the via hole 15.
0 is formed. Thereby, while making the adhesiveness of the AlCu alloy thin film 20 with respect to the via hole 15 favorable, the raise of the connection resistance in this part can be suppressed.

As a method of controlling the resistance value of the resistor 14 formed in the via hole 13, a method of depositing doped amorphous silicon having an impurity concentration corresponding to the resistance value, a method of changing the deposition thickness of amorphous silicon, and the number of via holes There is a way to change. Among these methods, the method of changing the number of via holes allows different resistance values at each position when the wiring is connected by resistors at a plurality of positions in the circuit. However, in the case where via holes having the same plane area are formed, the control is performed in units of “1/1 of the number of via holes”.

In addition, before forming the passivation film 22 in FIG. 3C, an insulating layer is formed on the TiN film 21, a via hole is formed in the insulating layer, and amorphous silicon is deposited on the via hole to form a resistance. Further, the resistance value can be doubled by forming a wiring layer on the TiN film with two layers thereon. Moreover, the resistance value can be increased by a factor of n by performing this step n times.
Note that the resistance material formed in the via hole is not limited to amorphous silicon, and polysilicon may be used.

Sectional drawing explaining the method to manufacture the semiconductor device of this invention. Sectional drawing explaining the method to manufacture the semiconductor device of this invention. Sectional drawing explaining the semiconductor device (c) of this invention, and its manufacturing method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... n substrate (silicon substrate doped with n-type impurity), 2 ... p well, 3 ... p diffusion layer, 4 ... silicon oxide film (LOCOS film) for element isolation, 5 ... gate oxide film, 6 ... gate Electrode, 7 ... n + diffusion layer, 8 ... p + diffusion layer, 9 ... insulating film, 91 ... contact hole,
DESCRIPTION OF SYMBOLS 10 ... 1st wiring (AlSiCu alloy thin film), 11 ... TiN film, 12 ... Insulating film, 13 ... Via hole for resistance formation, 14 ... Resistance, 15 ... Via hole, 16 ... TiN film, 17 ... Resist, 19 ... TiN film, 20 ... AlCu alloy thin film, 20a ... second wiring, 21 ... TiN
Membrane 22 ... Passivation membrane.

Claims (3)

A semiconductor device having on a semiconductor substrate a circuit in which wirings are connected by resistors,
A semiconductor device, wherein the first wiring and the second wiring are formed in layers with an insulating film interposed therebetween, and the resistor is formed in a via hole formed in the insulating film.   The semiconductor device according to claim 1, wherein the resistor is made of amorphous silicon. The semiconductor device according to claim 1, wherein the number of via holes is equal to the number corresponding to a resistance value.

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