JP6101162B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a MIM (Metal-Insulator-Metal) capacitive element.

  Conventionally, in an analog integrated circuit, compared to a MOS type capacitive element, since the capacitance is less dependent on the bias voltage and is not easily affected by noise from the substrate, an MIM capacitive element formed on a multilayer wiring is not suitable. It is used.

  The performance required for the MIM capacitive element includes (1) a large capacity per unit area, (2) sufficient reliability for a desired power supply voltage and operating environment, 3) There is little absolute capacitance variation between wafers or within a wafer surface, and (4) there is little relative variation between two or more adjacent MIM capacitor elements.

  In order to increase the capacitance per unit area, it is common to reduce the thickness of the capacitive insulating film, but this involves a decrease in reliability. Furthermore, since the thickness of the capacitor insulating film is small, the film thickness variation during the formation of the capacitor insulating film becomes large, and it is easily affected by the interface between the electrode and the insulating film. Or increase. As a result, the capacitance variation and the relative variation between elements also increase.

  Since the capacitor insulating film used for the MIM capacitor element is formed on an aluminum alloy or copper wiring, it is formed of a silicon oxide film or a silicon nitride film formed by plasma CVD that can be processed at a temperature of 400 ° C. or lower. Often done. However, since the deposition rate is high in this method, when the thickness of the capacitive insulating film is 50 nm or less, the processing time is short, and the adjustment range for adjusting the thickness may become rough.

  As a method for solving the above problem, an MIM capacitor having a structure shown in FIG. In the MIM capacitor element shown in FIG. 9, capacitor insulating films 302 and 305 are formed on the insulating film 300 between the lower electrode 301 and the intermediate electrode 304 and between the upper electrode 307 and the intermediate electrode 304, respectively. And the upper electrode 307 are electrically connected.

  In this method, the capacity per unit area can be doubled at the maximum while maintaining the breakdown voltage, leakage characteristics, and deposition conditions during manufacturing.

JP 2004-200640 A

  However, in the method described in Patent Document 1, the processing of the intermediate electrode 304 is necessary, and the capacitive insulating film 305 is used as an etching stop film when the upper electrode 307 is processed, which complicates the process. Further, damage to the surface of the capacitor insulating film 305 can occur. As a result, there are problems in that the types of capacitive insulating films are limited, and the breakdown voltage and leakage current characteristics are deteriorated.

  On the other hand, to increase the breakdown voltage, by increasing the film thickness of the capacitive insulating film, it is possible to improve the maximum twice as much while maintaining the capacity per unit area equivalent to that formed by one layer. Not too much. For this reason, for example, in an integrated circuit in which a 1.8V system circuit and a 20V system circuit are mixedly mounted, it is difficult to realize an MIM capacitor that satisfies the requirements of both circuits.

  In view of the above situation, the present invention allows a high-capacity density MIM capacitive element and a high-capacity-accuracy or high-withstand-voltage MIM capacitive element to be mounted on the same substrate only by adding an easy and low-cost process. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

In order to achieve the above object, a semiconductor device according to the present invention is provided with at least two types of MIM capacitor elements having different thicknesses of capacitor insulating films sandwiched between an upper electrode and a lower electrode on a semiconductor substrate. A semiconductor device comprising:
A first MIM capacitor element in which the capacitive insulating film is formed of a thick film of a first insulating film and a second insulating film formed above the first insulating film;
The capacitive insulating film comprises a second MIM capacitive element composed of only the second insulating film;
The upper electrodes of the first MIM capacitive element and the second MIM capacitive element are respectively formed in the same layer, and the lower electrodes of the first MIM capacitive element and the second MIM capacitive element are respectively in the same layer. The first feature is that it is formed by.

The semiconductor device according to the first aspect of the present invention further includes:
A third MIM capacitor including a thick film portion in which the capacitive insulating film is composed of the first and second insulating films, and a thin film portion in which the capacitive insulating film is composed only of the second insulating film. With elements,
The upper electrodes of the first MIM capacitive element, the second MIM capacitive element, and the third MIM capacitive element are formed in the same layer, respectively, and the first MIM capacitive element and the second MIM capacitive element A second feature is that the capacitive element and the lower electrode of the third MIM capacitive element are formed in the same layer.

  In the semiconductor device according to the second aspect of the present invention, in the third MIM capacitor, the thick film portion of the capacitor insulating film is closer to the first MIM capacitor element than the thin film portion. A third feature is that the first MIM capacitor element is formed in an annular shape so as to surround it.

  In the semiconductor device according to the second or third feature of the present invention, the fourth MIM capacitor element is further formed in an annular shape at a position surrounding the first MIM capacitor element. Features.

  Here, the third MIM capacitor element (capacitor insulating film) is formed in an annular shape. However, if the third MIM capacitor element (capacitor insulating film) is formed so as to have a closed loop, it is limited to an annular shape or a rectangular shape. It is not a thing.

  In the semiconductor device according to the fourth aspect of the present invention, the lower electrode of the third MIM capacitive element and the lower electrode of the first MIM capacitive element are formed continuously. can do.

  The semiconductor device according to the fourth aspect of the present invention is configured such that the lower electrode of the third MIM capacitor and the lower electrode of the first MIM capacitor are separately formed. Can do.

  The semiconductor device according to the second to fourth aspects of the present invention is further characterized in that the upper electrode of the third MIM capacitor element is a dummy electrode to which no voltage is applied. To do.

  The semiconductor device according to the present invention having any one of the first to fifth characteristics is further provided on the lower electrode below the outer peripheral side portion of the upper electrode constituting the first MIM capacitor element. It is preferable that one insulating film is formed.

  In the semiconductor device according to the present invention having any one of the first to fifth features, at least one of a film material and a film thickness of the first insulating film is different from that of the second insulating film. May be.

  In the semiconductor device according to the present invention having any one of the first to fifth features, at least one of the first insulating film and the second insulating film is formed of two or more kinds of stacked films. May be.

  In the semiconductor device according to the first to fifth features of the present invention, at least one of the lower electrode and the upper electrode is a metal film, a semiconductor film, or a laminated film of these films. It may be formed.

A method of manufacturing a semiconductor device according to the present invention for achieving the above object is a method of manufacturing a semiconductor device according to the present invention having any one of the first to fifth features,
Depositing an interlayer insulating film and a first conductive layer on the semiconductor substrate;
Depositing a first insulating film;
Patterning the first insulating film using a predetermined resist pattern covering at least the entire surface of the first formation region and opening the second formation region;
Depositing a second insulating film and a second conductive layer;
The second insulating film and the second conductive layer are processed using a predetermined resist pattern that covers at least the entire surfaces of the first formation region and the second formation region, and the second conductive layer is patterned. Separating the upper electrode for each of the first and second formation regions;
Processing the first conductive layer using a predetermined resist pattern covering at least a region where the upper electrode is formed, and forming a lower electrode in which the first conductive layer is patterned;
A first MIM capacitor element having the first insulating film and the second insulating film as a capacitive insulating film in the first forming region, and the second insulating film in the second forming region. The first feature is that the second MIM capacitor elements each having only a capacitor insulating film are formed.

The method for manufacturing a semiconductor device according to the first aspect of the present invention further comprises:
The step of patterning the first insulating film covers a whole surface of the first formation region and covers a part of a third formation region that is adjacent to the first formation region beyond the first formation region. Patterning the first insulating film using a pattern;
The processing of the second insulating film and the second conductive layer is performed by the second conductive layer and the second conductive layer formed on the periphery of the first insulating film remaining in the third formation region. By being performed with a predetermined resist pattern covering the step portion of the insulating film, the upper electrode on which the second conductive layer is patterned is separately formed for each of the first to third formation regions,
In the third formation region, a thick film capacitive insulating film having the first and second insulating films as a capacitive insulating film and a thin film capacitive insulating film having only the second insulating film as a capacitive insulating film are provided. A second feature is to form a third MIM capacitor element.

  In the method for manufacturing a semiconductor device according to the second aspect of the present invention, it is preferable that the third formation region is an annular region surrounding the entire outer periphery of the first formation region. Here, the third forming region being an annular region means that the third forming region has a closed loop, and is not limited to an annular shape or a rectangular shape.

  In the method for manufacturing a semiconductor device according to the second aspect of the present invention, in the step of forming the lower electrode, the first conductive layer on the first formation region and the third formation region on the first formation region The first conductive layer may be patterned so that the first conductive layer is divided.

The method for manufacturing a semiconductor device according to the first or second feature of the present invention further comprises:
Measuring the film thickness of the first insulating film remaining in the first formation region after depositing the first insulating film and before depositing the second insulating film;
A third feature is the step of setting the thickness of the second insulating film to be deposited in the step of depositing the second insulating film in accordance with the measured value of the thickness of the first insulating film. And

  According to the present invention, the first MIM capacitor element is formed with a thick insulating film, and the influence of the film thickness variation and the electrode interface during the formation of the insulating film is reduced. . On the other hand, the second MIM capacitor element has a thin insulating film and a high capacity density. The two types of capacitive elements can easily produce desired characteristics according to the circuit.

  At this time, a third MIM capacitor can be formed in the vicinity of the first MIM capacitor. The third MIM capacitor element is formed at a step portion generated when the second insulating film is deposited on the patterned first insulating film.

  In one embodiment, the third MIM capacitor element is formed as a result of leaving the upper electrode of the stepped portion without removing it. The third MIM capacitor element is a dummy element and is not used as an MIM capacitor element.

  However, since the upper electrode in the step portion is not removed but left unintentionally, the problem of etching residue generated when the upper electrode in the step portion is removed by etching and the problem of damage to the capacitor insulating film can be avoided. As a result, the first and second MIM capacitive elements are highly reliable elements with little variation. A high-performance semiconductor device can be realized by properly using two types of MIM capacitor elements according to the application on the circuit.

Schematic sectional view showing the device structure of a semiconductor device according to an embodiment of the present invention 1 is a layout diagram showing a planar layout of a semiconductor device according to an embodiment of the present invention. Schematic process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention Schematic process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention Process sectional drawing which shows a problem in the case of not forming the 3rd MIM capacity element in the manufacturing method of the semiconductor device concerning one embodiment of the present invention Schematic sectional view showing the device structure of a semiconductor device according to an embodiment of the present invention 1 is a layout diagram showing a planar layout of a semiconductor device according to an embodiment of the present invention. 1 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Structural sectional view showing an example of the structure of a conventional MIM capacitor

<First Embodiment>
Hereinafter, a configuration of a semiconductor device according to an embodiment of the present invention (hereinafter, appropriately referred to as “present invention device 1”) and a manufacturing method thereof will be described in detail with reference to the drawings. In FIG. 1, the schematic diagram of the cross-sectional structure of this invention apparatus 1 is shown. FIG. 2 shows a plan layout view of the device 1 of the present invention. 1 is a structural cross-sectional view in the XX ′ direction of FIG. In addition, in the structural cross-sectional view shown in FIG. 1 and the layout diagram shown in FIG. 2, the main parts are appropriately emphasized and displayed, and the scale of each component in the drawing and the actual scale It does not necessarily match. The same applies to the subsequent structural sectional views and layout diagrams.

  1 and 2, the first MIM capacitor C1 in the first formation region A1 (region surrounded by the dotted line in FIG. 2), the second MIM capacitor C2 in the second formation region A2, the third The third MIM capacitor element C3 is formed on the insulating film 102 formed on the surface of the semiconductor substrate 101 in the formation region A3 (region outside the dotted line in FIG. 2). Each of the first to third MIM capacitive elements C1 to C3 has a structure in which a capacitive insulating film is sandwiched between the upper electrode 107 and the lower electrode 103, and the first to third MIM capacitive elements C1. The upper electrode 107 of .about.C3 is formed of the same layer. Similarly, the lower electrodes 103 of the first to third MIM capacitive elements C1 to C3 are formed of the same layer.

  The first MIM capacitor element C1 is a high-capacity precision or high breakdown voltage element in which a capacitor insulating film is formed thick, and the first capacitor insulating film 104 and the second capacitor are interposed between the upper electrode 107 and the lower electrode 103. The insulating film 106 is sandwiched. A first capacitor insulating film 104 is formed on the lower electrode 103, and a second capacitor insulating film 106 is formed on the first capacitor insulating film 104. Therefore, the capacitor insulating film constituting the first MIM capacitor element C1 is formed of a thick film including the first capacitor insulating film 104 and the second capacitor insulating film 106.

  On the other hand, the second MIM capacitive element C2 is a high-capacity-density element in which the capacitive insulating film is thinly formed, and the second capacitive insulating film 106 is sandwiched between the upper electrode 107 and the lower electrode 103. . Therefore, the second capacitor insulating film 106 is the only capacitor insulating film constituting the second MIM capacitor element C2.

  A third MIM capacitor element C3 is arranged at a position surrounding the first MIM capacitor element C1. The third formation region A3 where the third MIM capacitive element C3 is formed is adjacent to the first formation region A1 where the first MIM capacitive element C1 is formed and surrounds the entire outer periphery of the first formation region A1. In addition, it is an annular closed region. The capacitive insulating film constituting the third MIM capacitive element C3 is a ring-shaped annular film located near the first MIM capacitive element C1 made of a thick film composed of the first capacitive insulating film 104 and the second capacitive insulating film 106. It consists of a thick film portion and a thin film portion composed only of the second capacitive insulating film 106. That is, as shown in FIGS. 1 and 2, the thick film portion of the capacitive insulating film is formed on the inner peripheral side (first formation region A1 side) of the annular third formation region A3, and the thin film portion is annular. Is formed on the outer peripheral side of the third formation region A3.

  The lower electrode 103 of the first and second MIM capacitive elements C1 and C2 and the upper electrode 107 of the first and second MIM capacitive elements C1 and C2 respectively have contact plugs 111 penetrating the interlayer insulating film 109. To the upper wiring 112. On the other hand, in the present embodiment, the third MIM capacitive element is a dummy capacitive element and is not used as a capacitive element. Therefore, the upper electrode 107 of the third MIM capacitive element C3 is not connected to the upper layer wiring 112, and the voltage Is in a floating state where no voltage is applied.

  In addition, the first capacitor insulating film 104 remains on the lower electrode 103 below the outer peripheral side portion of the upper electrode 107 constituting the first MIM capacitor element C1, but the second capacitor insulating film 106 is left. There is a region where is not formed.

  Below, the manufacturing method of the device 1 of the present invention shown in FIG. 1 will be described with reference to the drawings. 3 and 4 show schematic process cross-sectional views of the manufacturing process showing the manufacturing method of the device 1 of the present invention.

  First, as shown in FIG. 3A, an insulating film 102 is deposited on the entire surface of the first to third formation regions A1 to A3 on the surface of the semiconductor substrate 101, and further, for example, by a PVD (Physical Vapor Deposition) method. A lower electrode film (first conductive layer) 103 composed of a laminated film of TiN / Ti / AlCu / TiN / Ti is deposited on the entire surface of the first to third formation regions A1 to A3. Although not shown, normally, elements such as transistors and wirings are formed on the semiconductor substrate 101 and below the insulating film 102.

  Next, as shown in FIG. 3B, the first capacitive insulating film 104 is deposited on the entire surface of the first to third formation regions A1 to A3, for example, by plasma CVD (Chemical Vapor Deposition). Here, the first capacitor insulating film 104 is a silicon oxide film, and its film thickness is about 20 nm. The first capacitor insulating film 104 may be a single layer film or a stacked film in which two or more types of insulating film materials are stacked.

  Next, the entire surface of the first to third formation regions A1 to A3 is covered with a photoresist 105. Then, a part of the third formation region A3 that covers the entire surface of the first formation region A1, opens the entire surface of the second formation region A2, and is adjacent to the first formation region A1 beyond the first formation region A1. The photoresist 105 is patterned using a known photolithography technique and etching technique so as to cover it. Using the resist pattern thus formed, as shown in FIG. 3C, the first capacitor insulating film 104 is removed by dry etching, and the surface of the lower electrode film 103 is exposed. On the other hand, the first capacitor insulating film 104 is left on the entire surface of the first formation region A1 and the inner peripheral portion adjacent to the first formation region A1 in a part of the third formation region A3. Thus, the first capacitor insulating film 104 is patterned and formed in the region surrounded by the broken line in FIG.

  Thereafter, as shown in FIG. 4A, after removing the photoresist 105, a second capacitive insulating film 106 is deposited on the entire surface of the first to third formation regions A1 to A3 by plasma CVD. Here, the second capacitor insulating film 106 is a silicon oxide film, and the thickness thereof is about 20 nm. The second capacitor insulating film 106 may be a single layer film or a laminated film in which two or more kinds of insulating film materials are laminated. Furthermore, an upper electrode film (second conductive layer) 107 composed of a laminated film of TiN / Ti / AlCu / TiN / Ti from the upper layer is formed on the second capacitor insulating film 106 in the first to third formation regions A1. Deposited on the entire surface of .about.A3.

  At this time, the first capacitor insulating film 104 is formed in all of the first formation region A1 and part of the third formation region A3, so that the first capacitor insulation film in the third formation region A3 is formed. On the periphery of 104 (broken line portion in FIG. 2), a step is generated in the second capacitor insulating film 106 and the upper electrode film 107.

  Next, the entire surface of the first to third formation regions A1 to A3 is covered with a photoresist 108. Then, the photoresist 108 is patterned using a known photolithography technique and etching technique so as to form a predetermined pattern. Using the resist pattern thus formed, as shown in FIG. 4B, the upper electrode film 107 is exposed until the lower electrode film 103 in the region where the first capacitor insulating film 104 is not formed is exposed. The second capacitor insulating film 106 is removed by a dry etching method. At this time, a part or all of the film thickness of the first capacitor insulating film 104 may be over-etched in the region where the first capacitor insulating film 104 is formed.

  Thereby, the upper electrode film 107 and the second capacitor insulating film 106 are separately formed for each of the first to third formation regions A1 to A3. The upper electrode film (second conductive layer) 107 becomes the patterned upper electrode 107.

  Then, after removing the photoresist 108, the entire surface of the first to third formation regions A1 to A3 is covered with the photoresist 109. Then, the photoresist 109 is patterned using a known photolithography technique and etching technique so as to form a predetermined pattern covering the formation region of the upper electrode 107. Using the resist pattern formed in this way, as shown in FIG. 4C, the lower electrode film 103 is removed by a dry etching method, and the lower electrode film (first conductive layer) 103 is patterned. Here, since the lower electrode film 103 can also be used as wiring in other circuit portions, patterning is performed at the same time when it is also used as wiring.

  Thereafter, an interlayer insulating film 110 is further deposited on the entire surface after removing the photoresist 109.

  Thereafter, a contact hole 111 penetrating through the interlayer insulating film 110 and connected to the lower electrode 103 or the upper electrode 107, and an upper layer wiring 112 are formed on the contact hole 111, and the device 1 of the present invention shown in FIG. 1 is manufactured.

  In the manufacturing method of the device 1 of the present invention, the second capacitor insulating film 106 and the upper part are formed using the photoresist 108 that covers the step portion of the second capacitor insulating film 106 and the upper electrode film 107 in the third formation region A3. Since the electrode film 107 is processed, even after the step shown in FIG. 4B, the second capacitor insulating film 106 and the upper electrode film 107 at the stepped portion remain without being removed by etching, and as a result. A third MIM capacitor element is formed.

  On the other hand, when the second capacitor insulating film 106 and the upper electrode film 107 in the step portion are removed by etching, a third formation region A3 as shown in FIG. 5A is formed after FIG. The step portion is etched using the pattern of the photoresist 108 that opens.

  However, the upper electrode film 107 in the step portion is formed to have a greater thickness in the vertical direction than the flat portion. For this reason, if the upper electrode film 107 is etched under the condition of etching the portion corresponding to the thickness of the planar portion, the residue 120 of the upper electrode film 107 remains in the stepped portion. This situation is shown in FIG. In particular, since the etching of the upper electrode film 107 is performed by anisotropic etching, the residue 120 tends to remain in the stepped portion.

  If the etching is continued to completely remove the residue 120, the photoresist 108 serving as a mask may be lost or lost as shown in FIG. 5C, or a base film (in this case, the second capacitive insulating film 106). As a result, the characteristics and reliability of the first and second MIM capacitor elements to be formed are deteriorated, and there is a problem that variations between the elements are increased.

  However, in the device 1 of the present invention, since the upper electrode film 107 at the step portion is not removed in the etching process of the second capacitor insulating film 106 and the upper electrode film 107, a third MIM capacitor element is separately formed. However, as the first and second MIM capacitor elements, highly reliable elements with little variation can be realized.

Second Embodiment
Hereinafter, a configuration of a semiconductor device according to an embodiment of the present invention (hereinafter, referred to as “the inventive device 2” as appropriate) and a manufacturing method thereof will be described in detail with reference to the drawings. In FIG. 6, the schematic diagram of the cross-section of this invention apparatus 2 is shown. FIG. 7 shows a plan layout view of the device 2 of the present invention. 7 is a structural cross-sectional view in the XX ′ direction of FIG.

  The device 2 of the present invention uses the lower electrode 103 that is continuously formed integrally between the first MIM capacitor C1 and the third MIM capacitor C3 in the device 1 of the present invention, as the first MIM capacitor C1 and the first MIM capacitor C1. The three MIM capacitive elements C3 are separated from each other, and the other features are substantially the same as those of the device 1 of the present invention.

  As shown in FIGS. 6 and 7, the first MIM capacitor C1 in the first formation region A1, the second MIM capacitor C2 in the second formation region A2, and the third MIM in the third formation region A3. The MIM capacitor element C3 is formed on the insulating film 102 formed on the surface of the semiconductor substrate 101, respectively. Each of the first to third MIM capacitive elements C1 to C3 has a structure in which a capacitive insulating film is sandwiched between the upper electrode 107 and the lower electrode 103. The structure of the insulating film is different. The capacitive insulating film constituting the first MIM capacitive element C1 is formed of a thick film composed of the first capacitive insulating film 104 and the second capacitive insulating film 106. On the other hand, the second capacitor insulating film 106 is the only capacitor insulating film constituting the second MIM capacitor element C2. The capacitive insulating film constituting the third MIM capacitive element C3 disposed so as to surround the first MIM capacitive element C1 is formed of a thick film made up of the first capacitive insulating film 104 and the second capacitive insulating film 106. The annular thick film portion located closer to the first MIM capacitive element C1 (inner peripheral side) and the outer peripheral thin film portion constituted only by the second capacitive insulating film 106.

  In the device 2 of the present invention, since the lower electrode 103 is separately formed between the first MIM capacitor element C1 and the third MIM capacitor element C3, the first MIM capacitor element C1 has the third MIM capacitor element C1. It is not affected by the parasitic capacitance due to the element C3. For this reason, the first MIM capacitive element C1 with less parasitic capacitance and higher capacitance accuracy than the device 1 of the present invention can be realized. However, a space (isolation region 121 in FIG. 7) for separating the lower electrode 103 is required between the first MIM capacitive element C1 and the third MIM capacitive element C3, which is disadvantageous in terms of area. .

  On the other hand, in the device 1 of the present invention, the first MIM capacitor element C1 is affected by the parasitic capacitance due to the third MIM capacitor element C3. This is advantageous in terms of occupied area. Therefore, for the first MIM capacitor element C1, it is possible to use either the configuration of the inventive device 1 or the configuration of the inventive device 2 depending on the application.

  In the manufacturing method of the device 2 of the present invention, in FIG. 4C, the photoresist 109 is patterned so as to have an opening on the boundary line between the first formation region A1 and the third formation region A3, and the lower electrode film 103 is etched. Except for this, it is almost the same as the manufacturing method of the device 1 of the present invention described above, and a detailed description is omitted.

<Third Embodiment>
Below, one Embodiment of the manufacturing method of this invention apparatus 1 or 2 is described in detail. FIG. 8 is a flowchart showing the process sequence of the method for manufacturing the device 1 or 2 of the present invention in the present embodiment. The manufacturing method shown in FIG. 8 is the same as the manufacturing method shown in FIGS. 3 and 4 except that the thickness of the first capacitor insulating film 104 formed after the processing of the first capacitor insulating film 104 is measured. Steps (steps S206 and S207) for adjusting the film thickness of the second capacitor insulating film 106 to be deposited according to the film thickness are added. Hereinafter, the manufacturing method of this embodiment will be described with reference to the process diagrams of FIGS. 3 and 4 as well as FIG.

  First, the insulating film 102 is deposited on the entire surface of the first to third formation regions A1 to A3 on the surface of the semiconductor substrate 101 (step S201). At this time, an element such as a transistor or a wiring may be formed over the semiconductor substrate 101 in advance.

  Next, a lower electrode film (first conductive layer) 103 is deposited on the entire surface of the first to third formation regions A1 to A3 (step S202). The state at this time corresponds to FIG.

  Next, the first capacitor insulating film 104 is deposited on the entire surface of the first to third formation regions A1 to A3 (step S203). The state at this time corresponds to FIG.

  Next, the photoresist 105 is patterned to process the first capacitive insulating film 104 (step S204), and the entire first formation region A1 and a part of the first formation region A1 of the third formation region A3 are formed. The first capacitor insulating film 104 is left in the adjacent inner peripheral portion (the region indicated by the broken line in FIGS. 2 and 7). The state at this time corresponds to FIG. Thereafter, the photoresist 105 is removed (step S205).

  Thereafter, in an additional step S206, the film thickness of the first capacitive insulating film 104 formed in steps S204 to S205 is measured. An optical method (for example, reflectance spectroscopy) can be used for measuring the film thickness.

  In the subsequent additional step S207, the film thickness of the second capacitor insulating film 106 deposited in the next process is adjusted according to the measured film thickness value of the first capacitor insulating film 104, and the first capacitor The film thickness of the second capacitor insulating film 106 is set so that the combined capacitance of the insulating film 104 and the second capacitor insulating film 106 becomes a set value. When the first capacitor insulating film 104 and the second capacitor insulating film 106 are formed of the same film material, the film of the second capacitor insulating film 106 is simply set so that the total thickness becomes a set value. What is necessary is just to set thickness.

  Thereafter, the second capacitor insulating film 106 is deposited on the entire surface of the first to third formation regions A1 to A3 with the film thickness set in step S207, and the upper electrode film is formed on the second capacitor insulating film 106. (Second conductive layer) 107 is deposited on the entire surface (step S208). The state at this time corresponds to FIG.

  Next, the photoresist 108 is patterned to process the upper electrode film 107 and the second capacitor insulating film 106 (step S209). The state at this time corresponds to FIG.

  Next, after removing the photoresist 108, the photoresist 109 is patterned to process the lower electrode film 103 (step S210). The state at this time corresponds to FIG.

  Thereafter, an interlayer insulating film 110 is deposited on the entire surface, a contact hole 111 connected to the lower electrode 103 or the upper electrode 107, and an upper layer wiring 112 are formed on the contact hole 111 (step S211), and the book shown in FIG. The inventive device 1 or the inventive device 2 shown in FIG. 6 is manufactured.

  In the manufacturing method of the present embodiment, after the first capacitive insulating film 104 is deposited, the thickness of the deposited first capacitive insulating film 104 is measured, and the second deposited according to the measured thickness value. By adjusting the film thickness of the capacitor insulating film 106, the capacitance accuracy of the first MIM capacitor element C1 can be further increased.

  In the above embodiment, the measurement of the thickness of the first capacitor insulating film 104 (step S206) is performed after the first capacitor insulating film 104 is processed (step S204) and the photoresist 105 is removed (step S205). However, it may be performed immediately after the first capacitor insulating film 104 is deposited on the entire surface (step S203). In this case, the setting of the film thickness of the second capacitor insulating film 106 (step S207) is performed before or after steps S204 and S205, regardless of whether the film thickness of the first capacitor insulating film 104 is measured (step S206). Further, it may be performed before the deposition of the second capacitor insulating film 106 (step S208).

  In the first to third embodiments, the first capacitor insulating film 104 and the second capacitor insulating film 106 have the same film material (silicon oxide film) and the same film thickness. Or it is not necessary to make it the same film thickness. For example, the first capacitor insulating film 104 may be a laminated film of silicon nitride film / silicon oxide film from the upper layer, and the second capacitor insulating film may be a single-layer film including only a silicon oxide film. It can be freely selected according to etc. Further, the method for forming the capacitive insulating film is not limited to the CVD method and the PVD method, and a method for oxidizing the surface of the lower electrode can be appropriately used. Similarly, the material forming the lower electrode 103 and the upper electrode 107 may be various metal films and semiconductor films, or a laminated film combining two or more of them as long as it has conductivity. The film forming method is not limited to the CVD method or the PVD method.

  As described above, according to the present invention, the first MIM capacitor element C1 having high capacity accuracy or high breakdown voltage and the second MIM capacitor element C2 having high capacity density can be mixedly mounted on the same substrate, and the first and The second MIM capacitance elements C1 and C2 are elements with high reliability and little variation between elements. A high-performance semiconductor device can be realized by properly using two types of MIM capacitor elements according to the application on the circuit.

  The present invention can be used as a semiconductor device, and in particular, can be used in a semiconductor device, preferably an analog integrated circuit, in which two or more types of MIM capacitor elements having different thicknesses of capacitive insulating films are provided on the same substrate. is there.

1, 2: A semiconductor device according to an embodiment of the present invention (device of the present invention)
101: Semiconductor substrate 102, 300: Insulating film 103: Lower electrode (first conductive layer)
104: first capacitive insulating film 105, 108, 109: photoresist 106: second capacitive insulating film 107: upper electrode (second conductive layer)
110, 306: Interlayer insulation film 111: Contact plug 112: Upper layer wiring 120: Etching residue 121: Isolation region 301: Lower electrode 302, 305: Capacitance insulation film 304: Intermediate electrode 307: Upper electrode A1: First formation region A2: Second formation region A3: Third formation region C1: First MIM capacitor C2: Second MIM capacitor C3: Third MIM capacitor

Claims (5)

A semiconductor device in which at least two types of MIM capacitance elements having different thicknesses of capacitive insulating films sandwiched between an upper electrode and a lower electrode are provided on a semiconductor substrate,
A first MIM capacitor element in which the capacitive insulating film is formed of a thick film of a first insulating film and a second insulating film formed above the first insulating film;
A second MIM capacitive element in which the capacitive insulating film is composed only of the second insulating film;
A third MIM capacitor including a thick film portion in which the capacitive insulating film is composed of the first and second insulating films, and a thin film portion in which the capacitive insulating film is composed only of the second insulating film. An element,
The upper electrodes of the first MIM capacitive element, the second MIM capacitive element, and the third MIM capacitive element are formed in the same layer, respectively, and the first MIM capacitive element and the second MIM capacitive element A semiconductor device, wherein a capacitor element and the lower electrode of the third MIM capacitor element are formed in the same layer.   In the third MIM capacitor element, the thick film portion of the capacitor insulating film is closer to the first MIM capacitor element than the thin film portion, and is formed in an annular shape so as to surround the first MIM capacitor element. The semiconductor device according to claim 1, wherein the semiconductor device is formed.   3. The semiconductor device according to claim 1, wherein at least one of a film material and a film thickness of the first insulating film is different from that of the second insulating film. A method for manufacturing a semiconductor device according to claim 1,
Depositing an interlayer insulating film and a first conductive layer on the semiconductor substrate;
Depositing a first insulating film;
A resist pattern that covers the entire surface of the first formation region, opens the entire surface of the second formation region, and covers a part of the third formation region that is adjacent to the first formation region beyond the first formation region is used. Patterning the first insulating film;
Depositing a second insulating film and a second conductive layer;
Using the resist pattern covering at least the step portion of the second conductive layer and the second insulating film formed on the periphery of the first insulating film remaining in the third forming region. Processing the insulating film and the second conductive layer, and separately forming an upper electrode on which the second conductive layer is patterned for each of the first to third formation regions;
Processing the first conductive layer using a resist pattern that covers at least the region where the upper electrode is formed, and forming a lower electrode patterned with the first conductive layer;
A first MIM capacitor element having the first insulating film and the second insulating film as a capacitive insulating film in the first forming region, and only the second insulating film in the second forming region. A second MIM capacitor element that is a capacitive insulating film, and a thick capacitive insulating film that uses the first and second insulating films as a capacitive insulating film and the second insulating film in the third formation region A third MIM capacitor element having a thin film capacitor insulating film having only a capacitor insulating film as a capacitor insulating film is formed. Measuring the film thickness of the first insulating film remaining in the first formation region after depositing the first insulating film and before depositing the second insulating film;
The method further comprises a step of setting a thickness of the second insulating film to be deposited in the step of depositing the second insulating film in accordance with a measured value of the thickness of the first insulating film. Item 5. A method for manufacturing a semiconductor device according to Item 4.