JP6595873B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device using a laser trimming fuse element for adjusting electrical characteristics and a method for manufacturing the same.

  As a resistance element used in a voltage dividing circuit of a semiconductor integrated circuit, a diffusion resistor in which an impurity having a conductivity type opposite to that of a semiconductor substrate is implanted into a single crystal silicon semiconductor substrate, a resistor made of polycrystalline silicon in which an impurity is implanted, or the like is used. . When a plurality of such resistors are used in the voltage divider circuit design, the length, width and resistivity are all set to be the same. By doing so, each resistance element is equally affected by variations in the shape of the etching process that determines the shape and variations in impurity implantation. Even if the absolute values of the resistance elements vary, the resistance ratio between the resistance elements This is because it can be kept constant.

  When a resistance element having a constant resistance value based on this constant shape / resistivity is used in a voltage dividing circuit, unit resistance elements 200 are connected in series or in parallel as in the resistance groups 201 to 204 in FIG. By doing so, various resistance values are realized. Since the unit resistance element 200 is a resistance element having the same shape and the same resistivity as described above, the resistance ratio of the resistance group composed of unit resistance elements having a high resistance ratio can be maintained with high accuracy.

  Further, fuses 301 to 304 made of, for example, polycrystalline silicon are installed in parallel with the resistance groups 201 to 204 so that they can be cut by laser irradiation from the outside. The resistance value between the 109 terminal A and the 110 terminal B can be changed as necessary according to whether the fuse is cut or not cut by the laser irradiation. The voltage dividing ratio with the fixed resistor formed between the 110 terminal B and the 111 terminal C is output from the 110 terminal B.

The structure of fuses 301 to 304 used for conventional laser trimming will be described with reference to FIG.
FIG. 3 (1) shows the fuses 301 to 304 of FIG. Each fuse element includes a laser cutting region with a central line width narrower than both ends, and a region for wiring connection that is connected to an internal circuit by metal wiring 8 via contact holes 7 at both ends. have. A region for cutting the fuse element by laser trimming is provided with a laser fuse cutting opening 10.

  FIG. 3 (2) shows a cross section of the AA portion of FIG. 3 (1). On the LOCOS insulating film 13 for element isolation formed on the semiconductor substrate 1, a fuse element for laser cutting is formed with polycrystalline silicon 5 having a thickness of 2000 to 4000 mm using the same layer as the gate electrode of the MOS transistor. is doing. At this time, as shown in this cross-sectional view, in the laser fuse cut opening 10, the insulating film immediately above the fuse is dry-etched to reduce the film thickness and efficiently transmit the laser energy for melting the fuse. It has a structure. The remaining film thickness of the insulating film on the fuse after dry etching is set to a desired film thickness suitable for laser processing.

  Since the fuse material used here is polycrystalline silicon 5 which also serves as the gate electrode of the MOS transistor, in the case of a semiconductor manufacturing process having only one metal wiring layer 8, a BPSG (Boron Phospho Silicate) is formed on the fuse element. Only a planarization insulating film and a final protective film made of a silicon nitride film under the first metal wiring made of glass or the like are formed. Moreover, since this silicon nitride film was removed by etching at the same time when the pad opening portion for taking out terminals to the outside of the semiconductor integrated circuit was removed, only a BPSG film having a thickness of about 1 μm exists on the fuse.

  However, in the semiconductor manufacturing process having two or more layers of metal wiring, as shown in FIG. 3B, an interlayer insulating film mainly made of a silicon oxide film is further formed on the BPSG film 16 to insulate the metal wiring layer. 22 will be laminated. Assuming that this is a film thickness of about 1 μm per layer, the thickness of the insulating film on the fuse increases as the number of wiring laminated layers increases compared to the conventional metal wiring single layer process, and a silicon oxide film of several μm. Will easily reach the thickness of. Furthermore, if the final protective film is a two-layer film that employs a silicon oxide film as a stress relaxation layer with the lower wiring metal in addition to the uppermost silicon nitride film, the silicon oxide film thickness on the fuse further increases. .

  Thus, when the silicon oxide film thickness on the fuse is increased, the laser energy at the time of fuse cutting is not efficiently consumed for cutting the fuse, and there is a risk of causing defective cutting. Therefore, as shown in the cross-sectional view of FIG. 3 (2), in addition to the uppermost silicon nitride film, the silicon oxide film below it is also reduced in thickness by dry etching technology to avoid cutting defects in laser cutting. Is common.

Such a method for forming a fuse made of polycrystalline silicon and a method for processing an insulating film on the fuse are disclosed in, for example, Patent Document 1.
However, processing of laser cutting fuses used in conventional semiconductor integrated circuits has the following difficulties.

  First, in fuse elements using polycrystalline silicon that also serves as the gate electrode of a MOS transistor, from the surface of the semiconductor integrated circuit to the polycrystalline silicon fuse element due to the miniaturization of the semiconductor manufacturing process and the accompanying increase in the number of wiring stacks. As a result, the thickness of the insulator existing in the semiconductor has increased, and it has been difficult to cut a fuse by laser irradiation from the outside, such as a fuse cut for adjusting the characteristics of a semiconductor integrated circuit.

  In addition, in order to make it easy for the laser to reach the fuse element made of polycrystalline silicon, a predetermined amount of insulating film is added to the insulating film on the polycrystalline silicon fuse element by adding a photomask process and a dry etching process. As a method of adjusting the residual film thickness to a predetermined thickness by etching, the insulation is caused by dry etching in-wafer variations, wafer-to-wafer variations, and film thickness variations in each interlayer insulating film to be laminated. The variation in the remaining film thickness of the film was larger than before. In general, in laser fuse cutting, if the insulating film thickness on the fuse element is too thick, the energy is not transmitted efficiently and the fuse is left uncut, and if it is too thin, the laser penetrates under the fuse element and damages the underlying substrate. There is a trade-off of deterioration of fuse workability, such as giving a heat treatment, and the fuse itself is not melted and reattached due to heat dissipation, so there is an optimum film thickness range for the insulation film thickness. However, the insulating film thickness variation on the fuse as described above may exceed the optimum film thickness range, and it is difficult to stabilize the laser processability.

  Furthermore, as the number of interlayer insulation films increases, the reflection of the irradiation laser occurs at the interface between the interlayer insulation films, and the degree of reflection varies depending on the state of the interface. This reaches the fuse element. This contributed to the instability of laser energy and the resulting processing.

  As for the etching mask for removing the insulating film on the fuse, it is difficult to ensure etching selectivity between the film to be etched and the etching mask. When the etching amount is large, the etching mask disappears and etching damage is caused to the base. There was a case of generating. This problem also exists when the etching stopper film proposed in Patent Document 1 is employed.

  In addition, since this polycrystalline silicon layer is generally formed by adopting an LPCVD (Low Pressure Chemical Vapor Deposition) method that is performed at a high temperature of 500 ° C. to 700 ° C., a fuse element composed of this polycrystalline silicon layer has a melting point. A method of reducing the deposited insulating film thickness on the fuse element formed after forming the interlayer insulating film using a low-level metal wiring or organic film could not be adopted.

JP-A-10-189737

  Therefore, in the present invention, a silicon-based film is used as a fuse material, and the formation process is set to a layer closer to the final protective film than before, so that the thickness of the insulating film on the fuse is reduced and high dry etching stability is achieved. It is an object of the present invention to provide a semiconductor integrated circuit device using a laser trimming fuse element and a method of manufacturing the same, which can stabilize fuse cutting by a laser without requiring control.

In order to solve the above-mentioned problems, the present invention has been made as follows.
First, a semiconductor substrate, an insulating film formed on the semiconductor substrate, a conductor made of two metals spaced apart on the insulating film, and a first refractory metal laminated on the conductor And a fuse element made of an amorphous silicon layer that covers the first refractory metal film and the side surface of the conductor and is provided in a region on the insulating film that is separated from the two conductors. A semiconductor integrated circuit device was obtained.

Further, the semiconductor integrated circuit device is characterized in that a second refractory metal film having the same shape as the amorphous silicon layer in plan view is provided under the amorphous silicon layer.
Further, the semiconductor integrated circuit device is composed of at least two metal wiring layers, the conductor is composed of the uppermost layer of the metal wiring layers, and a protective film is provided on the uppermost metal wiring layer. The semiconductor integrated circuit device is characterized by being provided.
Further, the protective film is composed of a silicon oxide film and a silicon nitride film formed thereon, and an opening from which the silicon nitride film is removed is provided on the fuse element. A semiconductor integrated circuit device was obtained.

In order to solve the above problems, the present invention takes the following means.
That is, a method for manufacturing a semiconductor integrated circuit device including a fuse element,
Forming an insulating film on the semiconductor substrate;
Laminating a first metal film and a first refractory metal film in this order on the insulating film;
The first metal film and the first refractory metal film are etched, and the first refractory metal film is disposed on the first metal film spaced apart from the fuse element region. Forming a conductor and forming a bonding pad in the bonding pad region; and
Depositing an amorphous silicon layer on the two conductors, the bonding pad and the insulating film;
The fuse element region includes the amorphous silicon layer that covers the first refractory metal film and the side surfaces of the two conductors, and is provided in a region on the insulating film apart from the two conductors. Forming a fuse element; and
Removing the amorphous silicon layer and the first refractory metal film in the bonding pad region;
Depositing a protective film comprising a lower silicon oxide film and an upper silicon nitride film on the semiconductor substrate including the fuse element;
A protective film forming step of removing the protective film on the bonding pad;
A method for manufacturing a semiconductor integrated circuit device comprising:

The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon nitride film on the fuse element is removed in the protective film forming step.
Furthermore, before the step of depositing the amorphous silicon layer, further comprising the step of depositing a second refractory metal film,
In the step of forming the fuse element, the fuse element region is provided in a region on the insulating film that covers the first refractory metal film and the side surfaces of the two conductors and is spaced from the two conductors. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a fuse element made of the amorphous silicon layer and the second refractory metal film is formed.

  According to the present invention, the fuse element is formed of a silicon-based film, and the formation process is set to a layer closer to the final protective film than in the past to reduce the thickness of the insulating film on the fuse element, thereby It is possible to provide a semiconductor integrated circuit device that realizes stable fuse cutting, high yield, and long-term reliability, and a method for manufacturing the same.

It is the model top view and model cross-section which implement | achieve the 1st Example of this invention. It is an example of the voltage dividing circuit which combined the resistive element. It is the model top view and model sectional drawing which show the conventional fuse element structure. It is the model top view and model sectional drawing which implement | achieve the 2nd Example of this invention. It is a schematic cross section which implement | achieves the 3rd Example of this invention. It is a schematic cross section which implement | achieves the 4th Example of this invention. It is a schematic cross section which implement | achieves the 7th Example of this invention. It is a schematic cross section which implement | achieves the 8th Example of this invention. It is sectional drawing of the process flow which implement | achieves the 7th Example of this invention. FIG. 10 is a process flow sectional view for realizing the seventh embodiment of the present invention, following FIG. 9. It is sectional drawing of the process flow which implement | achieves the 8th Example of this invention. FIG. 12 is a process flow sectional view for realizing the eighth embodiment of the present invention, following FIG. 11. It is a schematic cross section which implement | achieves the 5th Example of this invention. It is a schematic cross section which implement | achieves the 6th Example of this invention. It is sectional drawing of the process flow which implement | achieves the 5th Example of this invention. FIG. 16 is a process flow cross-sectional view of the fifth embodiment of the present invention, following FIG. 15. It is sectional drawing of the process flow which implement | achieves the 6th Example of this invention. FIG. 18 is a process flow sectional view for realizing the sixth embodiment of the present invention, following FIG. 17.

The present invention relates to a semiconductor integrated circuit device having a fuse circuit for laser trimming, which achieves both stable insulation film thickness on the fuse element and adoption of a fuse element material that is easy to cut by laser. The present invention proposes a semiconductor integrated circuit device having a fuse structure capable of solving the conventional difficulties relating to processability and a method for manufacturing the same.
Each example will be described below with reference to the drawings.

  FIG. 1 is a schematic plan view and a schematic sectional view showing a first embodiment of the present invention, and shows an example using a three-layer metal wiring process. First, in FIG. 1A, regarding the fuse element, an amorphous silicon layer 17 formed by sputtering is used instead of the conventional polycrystalline silicon layer formed by LPCVD. A third-layer metal wiring 14 and a third-layer metal wiring 14 forming two conductors for connecting to the second-layer metal wiring 11 connected to the internal circuit are provided at both upper and lower ends of the fuse element in the drawing. A via hole 15 is provided to connect between the metal wiring 14 and the second-layer metal wiring 11. The amorphous silicon layer 17 is laid out so that the third-layer metal wiring 14 forming the two conductors and the via hole 15 sufficiently overlap in a plane. Although not shown here, the metal wiring of the first, second and third layers uses a general semiconductor manufacturing process for fine processing. For example, the metal of the conductor used for the metal wiring is Al or Cu containing an additive such as Si or Cu is used, and a barrier metal made of a refractory metal such as Ti or TiN is arranged on the bottom surface of the conductor, and the top surface of the conductor is arranged. Is laminated with an antireflection film such as TiN. In FIG. 1 (2), the antireflection film 23 of the third-layer metal wiring 14 deeply related to the present invention is shown. The refractory metal is not limited to Ti or TiN, and may be other Ti compounds.

  FIG. 1B is a cross-sectional view taken along line AA of the fuse element 301 in FIG. In this embodiment, the fuse element 301 is provided on the interlayer insulating film 22 covering the second-layer metal wiring. On the amorphous silicon layer 17, a silicon oxide film 24 and a silicon nitride film 25, which are two protective films, are stacked. In this example, the formation of the amorphous silicon layer is performed at the timing of forming the metal wiring of the final layer, but it is not particularly limited at the time of forming the final wiring layer. I do not care.

  Further, in the structure of the present invention in FIG. 1B, both ends of the amorphous silicon layer 17 constituting the fuse element are in contact with the side surface portion and the upper surface portion of the two conductors made of the third-layer metal wiring 14. In this structure, the contact area between the fuse element and the wiring is increased to obtain a stable contact resistance.

  Further, a via hole 15 for obtaining a connection with the second layer metal wiring 11 is formed immediately below the third layer metal wiring pattern, and the second layer is then passed through a buried metal such as tungsten in the via hole. The metal wiring 11 is electrically connected to the internal circuit from there.

  In the present invention, unlike the conventional polycrystalline silicon layer manufacturing process before the wiring layer forming step, 500 ° C. is used to manufacture the fuse element in the metal wiring forming process of the first and subsequent wiring layers. Instead of the LPCVD method that cannot avoid the above high temperature treatment, a sputtering method using a silicon target material is employed. By forming the formation temperature at 200 ° C. or lower, the wiring layers and the interlayer insulating film that have already been formed are not damaged and can be used at any wiring formation timing in the multilayer metal wiring layer process. There is an advantage in the degree of freedom in the manufacturing process.

  Also, unlike the CVD method, the sputtering method is advantageous for depositing a thin film, and a thin film deposition of 1000 mm or less is easy. On the other hand, it can be performed at a low temperature treatment of 500 ° C. or lower, and a plasma CVD method or the like can be given as a manufacturing method suitable for mass production, but formation of a film of 1000 mm or less is concerned with stability. Making the fuse film thinner by using the sputtering method can reduce damage to surrounding elements and the substrate by reducing the fusing energy by the laser, and to prepare for laser damage in the plane direction and vertical direction. By reducing the size margin, it is possible to contribute to cost reduction accompanying the reduction of the semiconductor integrated circuit.

  However, in general, if the thickness of the amorphous silicon layer is less than 150 mm, the amorphous silicon layer diffuses into the underlying Al during a heat treatment at about 400 ° C., such as a plasma CVD process for forming the final protective film later, and the Al at the fuse connection portion. And the contact resistance between the amorphous silicon layer becomes remarkable. Here, in FIG. 1, since the antireflection film 23 made of a refractory metal such as TiN is left on the third-layer wiring 14, the diffusion of the amorphous silicon layer on the upper surface of the Al wiring is not a problem. . On the other hand, on the side surface of the Al wiring, although the Al wiring and the amorphous silicon layer are in direct contact, unlike the upper surface of the Al wiring, oxygen and carbon, which are by-products during dry etching processing, are attached and diffused into the Al. Is suppressed. With the above structure, the amorphous silicon layer used in the present invention can obtain a stable contact resistance with the metal wiring by setting a target thickness of 150 mm or more even if the film thickness variation of about 10% is considered. Is possible.

  Furthermore, in the usual sputtering method, when an insulating target material is formed by sputtering on a semiconductor substrate, it is difficult to control the potential of the insulating material. Therefore, sputtering using amorphous silicon as a target material as in the present invention is performed. When performing, impurities such as phosphorus and boron are added to silicon as a target material to increase the impurity concentration and lower the resistivity. Therefore, for example, a target material having a resistivity of 0.01 Ω · cm or less is generally used, and this is used to serve as a conductor for the fuse element. In this case, if the sheet resistance per unit area cannot be ignored by making the film thinner, a desired fuse resistance value is realized by adjusting the length and width of the fuse element.

  As for fuse resistance reduction, after forming a high resistivity silicon thin film that does not contain impurities, a method of injecting impurities by an ion implantation method or the like to realize a low resistivity silicon thin film can be mentioned. Therefore, it is necessary to apply a sufficient amount of heat for activation, and damage to the Al-based wiring layer and the interlayer insulating film cannot be avoided. Therefore, it is difficult to produce a low resistance fuse element made of a silicon-based material after forming a metal wiring or an interlayer insulating film by a method other than the method of preparing a sputtering with a high impurity concentration and a low resistivity as in the present invention. It is.

  Further, in FIG. 1 (2), the laser cut opening part which has been installed in the conventional example is not particularly provided. The reason is that, as described above, the amorphous silicon layer used as the fuse element is formed at the same timing as the uppermost metal wiring layer. This is because the film thickness of this fuse can be set sufficient for laser cutting. Therefore, although the film formation variation between the silicon oxide film 24 and the silicon nitride film 25 still exists, this is equivalent to the case of the conventional one-layer metal wiring process in which there is no problem in the laser cut processability, but on the other hand, because of the opening. Since there is no variation in the insulating film thickness on the fuse due to variations in dry etching, stable laser processing can be realized. In addition, it is possible to reduce the layout dimension margin such as the existing laser cut opening pattern and laser irradiation spot position variation margin and the alignment margin between the laser cut opening and the metal wiring. It can contribute to the required area reduction.

  In addition, if there is an opening for laser cutting, the silicon nitride film with excellent moisture resistance disappears, leaving room for moisture to enter the semiconductor integrated circuit through the silicon oxide film, causing corrosion and characteristics of the wiring. Although there is a possibility of long-term reliability deterioration such as fluctuation, in the first embodiment of the present invention, only the hole having the size of the laser diameter of the silicon nitride film formed at the time of laser cutting of the fuse element remains as an opening. Therefore, there is an advantage that the influence of long-term reliability can be minimized.

  In this example, the third-layer metal wiring and the second-layer metal wiring are used for the fuse element wiring in the semiconductor manufacturing process of the three-layer metal wiring. The same effect can be obtained by forming the fuse element and its wiring using the metal wiring of the first layer and the metal wiring of the first layer. In the semiconductor manufacturing process of the first layer metal wiring, although not shown, the same effect can be obtained by using the first layer metal wiring and the high concentration diffusion wiring on the silicon substrate. Thus, it can be said that the present invention can be applied to a semiconductor manufacturing process having various wiring configurations of one or more layers and has a high degree of freedom in selecting a semiconductor manufacturing process.

  As described above, the first embodiment of the present invention improves the stability of the laser cutting process of the fuse element as compared with the conventional one and fuses with a high quality capable of minimizing yield reduction and long-term reliability failure. It has a feature that an inexpensive semiconductor integrated circuit with a small required area required for the element and its periphery can be provided.

  FIG. 4 is a schematic plan view and a schematic sectional view showing a second embodiment of the present invention, and also shows an example using a three-layer metal wiring process. In the present embodiment, unlike the first embodiment, a laser fuse cut opening 10 is provided in the laser fuse cut scheduled region as shown in FIG. 4A, and the cutting line A-- of the fuse element 301 in FIG. As shown in FIG. 4B, which is a cross-sectional view at A, the silicon nitride film, which is the final protective film immediately above the fuse element, is removed by dry etching.

The film thickness of the final protective film mainly including a silicon nitride film may vary depending on the characteristics of the semiconductor factory or semiconductor process for manufacturing the semiconductor integrated circuit device, and the materials, conditions, and heat treatment used. For example, when the thickness of the uppermost metal wiring layer is increased in order to pass a large current, the final protection is performed to adjust the stress balance with the final protective film in contact with the uppermost metal wiring layer. In some cases, the thickness of the film is set to be thicker. As in the first embodiment of the present invention, the final protective film on the fuse element is left as it is, and the laser energy of the fuse cut can be sufficiently transmitted to the fuse element for thickening the final protective film. If not, the method of removing the silicon nitride film, which is the upper protective film of the two protective films, as in the second embodiment, and ensuring the laser workability is preferable. In this case, at the time of dry etching of the uppermost silicon nitride film of the two-layer protective film, the etching selectivity with the underlying silicon oxide film is set to a ratio of 10: 1 or more, so that the underlying silicon oxide film at the time of dry etching is It is easy to sufficiently reduce the variation in film thickness, and the deterioration of the laser workability due to the increase in the variation in the remaining thickness of the silicon oxide film as in the conventional example does not become obvious.
In addition, as in the conventional example, the provision of the laser cut opening 10 eliminates the silicon nitride film as the final protective film, which may lead to long-term reliability deterioration.

  For example, the fuse element generally exposes its cross section in the opening after laser cutting, but with a high voltage of several tens of volts or more being applied to the fuse element, the fuse element is exposed to moisture containing an electric field such as ions at a high temperature. When exposed, the chemical reaction is promoted at the laser cut surface by receiving electric energy, and silicon is combined with oxygen in the moisture to be transformed into a silicon oxide film and expanded. At this time, if the expansion stress cannot be absorbed, a phenomenon may occur in which cracks and fractures occur around the fuse element to accelerate the penetration of moisture into the interior and the erosion proceeds. However, the fuse element used in the present invention is thinner than the 2000 to 4000 polycrystalline silicon that is also used as a conventional gate electrode, and is set to a thickness of 150 to 1000 by sputtering. Since the area of the fuse cutting surface is ¼ or less of the conventional one, the reduction of the cutting area where chemical reaction occurs and the degree of stress generation due to it can be suppressed, and the progress of corrosion to the inside can be reduced. There are advantages over the conventional example.

  In other words, as described above, the second embodiment of the present invention forms a laser cut opening in the final protective film, so that even when the final protective film has a thick silicon nitride film, laser cutting of a stable fuse element is possible. Workability can be maintained and long-term reliability defects can be reduced as compared with conventional methods.

FIG. 5 is a schematic plan view and a schematic sectional view showing a third embodiment of the present invention, and also shows an example using a three-layer metal wiring process.
The difference from the first embodiment of FIG. 1 is that a second refractory metal film 18 is laminated under the amorphous silicon layer 17. The two laminated films have the same shape in plan view because they are collectively formed by dry etching using the same mask pattern, and there is no particular difference in the plan view of FIG.

  Further, as shown in FIG. 5 (2), which is a cross section taken along the section line AA of FIG. 5 (1), this refractory metal film 18 is a metal wiring layer forming two conductors at the fuse end. 14 and the upper antireflection film 23 made of a refractory metal, which contributes to a reduction in contact resistance. In particular, the diffusion of Al to the Al due to the heat treatment of the amorphous silicon layer, which is concerned about the side surface of the metal wiring layer 14 made of Al, has the same effect as the antireflection film 23 on the upper surface. It is possible to escape the restrictions on the transformation.

  In the first and second embodiments, the fuse element is formed only of the amorphous silicon layer. However, when the increase in resistance due to the thinning of the amorphous silicon layer cannot be ignored, or the fuse element is cut / uncut. When the semiconductor integrated circuit device is sensitive to a difference in resistance value due to the resistance value of the fuse element, the resistance value of the fuse element can be greatly reduced by installing a refractory metal film such as TiN under the amorphous silicon layer 17. ing. Both the amorphous silicon layer and the TiN layer are materials commonly used as an antireflection film for metal wiring, and the additional setting of this layer does not cause any adverse effects or side effects on the metal wiring or its peripheral elements. Workability is not impaired. Conventionally, when a fuse element is composed only of TiN, the high melting point of TiN and the thinness of the film tended to cause instability of laser cutting processing. Since the amorphous silicon layer absorbs and accumulates laser energy and generates heat, there is an advantage that cutting of TiN directly below can be performed more efficiently than in the prior art. In this way, even if a refractory metal is used as the fuse element material, the advantages of the refractory metal can be enjoyed without impairing the stability of laser cutting.

  As described above, according to the third embodiment of the present invention, while realizing a low-resistance fuse element, it is possible to improve the stability of laser cutting of the fuse element compared to the prior art and to minimize the reliability failure. It has a feature that it can provide an inexpensive semiconductor integrated circuit with high quality and a small required area for the fuse element and its periphery.

  FIG. 6 is a schematic plan view and a schematic sectional view showing a fourth embodiment of the present invention, and also shows an example using a three-layer metal wiring process. In this embodiment, in addition to the third embodiment, a laser fuse cut opening 10 is provided in the laser fuse cut scheduled region as shown in FIG. 6A, and the cutting line A of the fuse element 301 in FIG. As shown in FIG. 6B, which is a cross-sectional view at -A, only the silicon nitride film, which is the final protective film immediately above the fuse, is removed by the dry etching method.

  The purpose and effect are the same as in the second embodiment, and the silicon nitride film 25 as the final protective film is thick, and it is assumed that the laser energy at the time of fuse cutting cannot be sufficiently transmitted to the fuse. This is applied to the third embodiment.

  By adopting such a configuration, the fourth embodiment of the present invention forms a laser cut opening in the final protective film, so that even if the silicon nitride film of the final protective film is thick, a stable fuse element can be obtained. Laser cutting processability can be maintained, and long-term reliability defects can be reduced as compared with conventional methods.

  FIG. 13 is a schematic cross-sectional view showing a fifth embodiment in which the first embodiment of the present invention shown in FIG. 1 is applied to the periphery of a fuse element in a semiconductor integrated circuit device. An example using a layer metal wiring process is shown.

  In the figure, reference numeral 301 denotes the fuse element according to the first embodiment of the present invention described so far. In addition to this, the bonding pad 19 responsible for electrical connection with an external terminal, and an NMOS transistor 401 as an example of an internal circuit. And the surrounding wiring are added.

  First, it is composed of amorphous silicon 17 to which the first embodiment is applied, and a third-layer metal wiring 14 such as Al disposed at both ends of the fuse element and an antireflection film 23 made of a refractory metal such as TiN. The laminated film is connected to the internal circuit through the via hole 15 and the second layer metal wiring 11 (not shown).

  Next, an NMOS transistor 401 as an example of an internal circuit includes an N-type source / drain region 12, a gate insulating film 9, and a gate electrode 6, and includes a contact hole 7, a first layer metal wiring 8, and a first layer. Via hole 15 in the interlayer insulating film 22 connecting the second layer metal wiring and via hole 15, 3 in the interlayer insulating film 22 connecting the second layer metal wiring 11, the second layer and third layer metal wiring. Electrical connection with other elements and circuits is made through the internal circuit fine metal wiring 21 which is the metal wiring of the layer.

  Here, the interlayer insulating film 22 is used in a general semiconductor process, and is mainly made of a silicon oxide film. An etch back method using a TEOS (Tetra Ethyl Ortho Silicate) film or an SOG (Spin On Glass) film is used. Surface flatness is maintained by applying a flattening technique such as CMP (Chemical Mechanical Polishing).

  The first metal wiring and the second metal wiring are structured and formed using the same general semiconductor manufacturing process for fine processing. For example, the conductor metal used for the metal wiring is Al containing an additive such as Si or Cu, or Cu itself. In addition, for example, a barrier metal made of a refractory metal such as Ti or TiN is disposed on the bottom surface of the conductor to improve the contact property with the underlying metal or silicon substrate and at the same time improve the long-term reliability of the wiring. Yes. Further, an antireflection film made of a refractory metal such as TiN is laminated on the upper surface of the conductor to suppress reflection of light used for photolithography processing on the conductor surface. In other words, a general wiring material and its laminated structure based on the fine rules of the semiconductor manufacturing process to be applied are adopted, but since the general technique is used regardless of the present invention, these details are omitted and simplified. It is shown.

  However, for the internal circuit fine metal wiring 21 which is the third metal wiring to which the fine rule used for the wiring of the internal circuit is applied, the conductor metal and its barrier metal are similarly produced by a general structure and manufacturing process. Although an antireflection film is provided on the upper layer and used when forming the third metal wiring, the third metal at both ends of the fuse element 301 is finally used as shown in FIG. Unlike the wiring, the antireflection film is removed. It is a feature of the fifth embodiment that this situation is applied to all the third metal wirings other than the third metal wiring used for the both end electrodes of the fuse element 301. However, although the antireflection film is finally removed, it is not particularly problematic in manufacturing because it is installed during the required photolithography processing.

  In general, the antireflection film on the metal wiring used when processing the metal wiring is laminated on the metal immediately after the metal film made of Al or Cu as the conductor is deposited, and both are deposited. The layers are processed together by a photolithography technique and a dry etching technique. At the time of exposure at that time, the antireflection film plays a role of preventing light from entering unintentional portions due to reflection of light by the metal that is a conductor, and pattern deformation / cutting due thereto.

  Therefore, in such a manufacturing method, the antireflection film and the conductor always exist as one body after the etching process. However, in the present invention, since the antireflection film other than the fuse element portion is simultaneously removed in the subsequent processing of the fuse element, the structure shown in FIG. 13 is obtained.

  In addition, as a method of manufacturing the fuse element, an interlayer insulating film is provided between the fuse element and the third metal wiring, and the both can be connected by a via hole or the like. The antireflection film remains on the wiring. In the present invention, after the third metal wiring layer is formed, the fuse element is formed as it is, so that the step of forming the interlayer insulating film and forming the via hole can be omitted. Set to. One of the reasons why the antireflection film does not exist on the third metal wiring layer other than the fuse element is due to the above manufacturing reasons.

  In FIG. 13, a bonding pad 19 for taking out the electrical connection in the semiconductor integrated circuit to the outside of the semiconductor chip is provided with a third-layer metal wiring, which is also the uppermost metal wiring, for bonding wire connection. A silicon oxide film 24 and a silicon nitride film 25 constituting the final protective film immediately above are opened. Here, for the wiring connection structure for connecting the bonding pad made of the third-layer metal wiring to the previous internal circuit, a general technique is used irrespective of the present invention, so these details are omitted and simplified. Show.

  As for the third-layer metal wiring used for the bonding pad 19, the antireflection film such as TiN is removed in the same manner as the third-layer metal wiring 21 used as the fine metal wiring for the internal circuit. In comparison, it has the following advantages.

  In the conventional manufacturing process, even when the antireflection film is laminated and processed in the formation of the bonding pad, the antireflection film exposed to the opening surface at the time of dry etching for opening the final protective film of the bonding pad portion is formed. At the same time, it is removed to improve the contact of the test probe and the adhesion of the bonding wire. Nevertheless, the antireflection film remains on the metal layer under the final protective film around the final protective film opening, and the cross section of the antireflective film is exposed from the cross section of the final protective film opening. In general, a Ti-based film is easily oxidized by heat, moisture, etc. When the exposed Ti-based antireflection film is brought into contact with, for example, a water flow during dicing for a long time, Ti is oxidized and expanded to lift the final protective film. However, there are rare cases where internal moisture penetration is promoted and metal wiring corrosion and characteristic fluctuations are induced.

  In the fifth embodiment of the present invention, the anti-reflection film is not left on the third metal wiring other than the fuse element portion, and the anti-reflection film of the bonding pad portion is similarly removed. It has the advantage of preventing such quality defects and long-term reliability defects.

  As described above, the fifth embodiment of the present invention is a fuse element that has excellent long-term reliability and suppresses manufacturing costs that do not require the formation and processing of an additional interlayer insulating film, and a semiconductor integrated circuit including the fuse element. The circuit device can be provided.

  FIG. 14 is a schematic cross-sectional view showing a sixth embodiment in which the second embodiment of the present invention shown in FIG. 4 is applied to the periphery of a fuse element in a semiconductor integrated circuit. An example using a metal wiring process is shown.

  Here, as in the fifth embodiment, the NMOS transistor 401 and its peripheral wiring, the fuse element 301 and the bonding pad 19 are shown, but the structure of the NMOS transistor 401, the bonding pad 19 and the fuse element itself is the first. This is the same as the fifth embodiment. In the sixth embodiment, in the two-layer final protective film composed of the silicon oxide film 24 and the silicon nitride film 25, both layers are opened in the bonding pad portion 19 by dry etching, and the final protective film on the fuse element is formed of silicon nitride. Only the membrane is open. As explained in the second embodiment, when the thickness of the final protective film is increased due to manufacturing reasons or the like, it becomes difficult to transmit the laser at the time of fuse cutting, and the laser processability of the fuse element is impaired. In this way, the fuse opening photomask for the final protective film is prepared separately from the bonding pad opening mask and processed.

  According to the sixth embodiment of the present invention as described above, even when the final protective film is thick against the laser transmission of the fuse cut, a stable fuse cut processability can be obtained and the semiconductor integrated circuit device is excellent in long-term reliability. Can be realized.

  FIG. 7 is a schematic sectional view showing a seventh embodiment in which the third embodiment of the present invention shown in FIG. 5 is applied to the periphery of the fuse element in the semiconductor integrated circuit device. An example using a layer metal wiring process is shown.

  Here, as in the fifth embodiment, the NMOS transistor 401 and its peripheral wiring, the fuse element 301, and the bonding pad 19 are shown. However, the NMOS transistor 401 and the bonding pad 19 are the same as in the fifth embodiment. However, the fuse element 301 is composed of a laminated film of amorphous silicon 17 to which the third embodiment is applied and a refractory metal film 18 such as TiN, and a third layer of metal such as Al disposed at both ends of the fuse element. A wiring 14 and a laminated film of an antireflective film 23 made of a refractory metal such as TiN are connected to an internal circuit through a via hole 15 and a second layer metal wiring 11.

As for the third metal wiring, as in the fifth embodiment, an antireflection film is laminated only on the metal wiring at both ends of the fuse element 301, but on the wiring of the internal circuit including the bonding pad 19 and the NMOS transistor 401. The antireflection film is removed.
The final protective film composed of the uppermost silicon oxide film 24 and silicon nitride film 25 is opened only on the bonding pad 19 for taking out terminals to the outside.

  As described above, the seventh embodiment of the present invention is a low-resistance fuse element that has excellent long-term reliability and suppresses manufacturing costs that do not require the formation of an additional interlayer insulating film and its processing steps, and the fuse element. The semiconductor integrated circuit device can be provided.

  FIG. 8 is a schematic sectional view showing an eighth embodiment in which the fourth embodiment of the present invention shown in FIG. 6 is applied to the periphery of a fuse element in a semiconductor integrated circuit. An example using a metal wiring process is shown.

  Here, as in the seventh embodiment, the NMOS transistor 401 and its peripheral wiring, the fuse element 301 and the bonding pad 19 are shown, but the structure of the NMOS transistor 401, the bonding pad 19 and the fuse element itself is the first. This is the same as the seventh embodiment. In the eighth embodiment, in the two-layer final protective film composed of the silicon oxide film 24 and the silicon nitride film 25, both layers are opened in the bonding pad portion 19 by dry etching, and the final protective film on the fuse element is silicon nitride. Only the membrane is open. As explained in the fourth embodiment, when the thickness of the final protective film is increased due to manufacturing reasons or the like, it becomes difficult to transmit the laser at the time of fuse cutting, and the laser processability of the fuse element is impaired. Thus, the final protective film fuse opening mask is prepared separately from the bonding pad opening mask and processed.

  According to the eighth embodiment of the present invention as described above, stable fuse cutting processability can be obtained even when the final protective film is thick against laser transmission of fuse cutting, and long-term reliability having a low resistance fuse element. An excellent semiconductor integrated circuit device can be realized.

A method for manufacturing the semiconductor integrated circuit device shown in the fifth embodiment of the present invention will be described below with reference to FIGS. 15 and 16 as the ninth embodiment.
First, a process including an element isolation region such as the LOCOS insulating film 13, the gate insulating film 9, the gate electrode 6, and the source / drain region 12 is performed on the semiconductor substrate 1 in order to manufacture a MOS transistor. Next, a flat insulating film such as a BPSG film 16 is formed, a contact hole 7 is formed in the BPSG film, a first metal wiring 8 is formed, an interlayer insulating film 22 is formed on the metal wiring 8, and the first and second layers. The via hole 15 in the interlayer insulating film 22 for connecting the metal wiring of the layer is formed, the metal wiring 11 of the second layer is formed, and the interlayer insulating film 22 on the metal wiring 11 of the second layer is formed (FIG. 15 (1)).

  Here, regarding the structure and forming method of the first metal wiring and the second metal wiring, Al containing an additive such as Si or Cu, Cu itself, or the like is used as the metal of the conductor, and the conductivity thereof. For example, a barrier metal made of a refractory metal such as Ti or TiN is arranged on the bottom surface of the body, and an antireflection film made of a refractory metal such as TiN is laminated on the upper surface of the conductor, but details are omitted. To do. That is, the manufacturing process including the metal wiring described above employs a general method, and is not limited to a special manufacturing process, and the illustration is simplified.

Next, the formation of the via hole 15 in the interlayer insulating film 22 for connecting the second layer and the third layer metal wiring, and the formation of the third layer metal wiring 14 are performed (FIG. 15B).
Again, the details of the third metal wiring structure employ a general method, but an antireflection film 23 made of a refractory metal such as TiN, which is indispensable in the present invention, is shown in the drawing. This shows that the antireflection film 23 is laminated on all the third metal wiring layers at the end of the processing of the metal wiring.

Next, an amorphous silicon layer 17 characteristic of the present invention is laminated on the entire surface of the semiconductor substrate by sputtering (FIG. 15 (3)).
Next, a photoresist 20 is applied, the photoresist is left only in the fuse element formation planned region by using a photolithography technique, and the photoresist in other regions is removed (FIG. 16A).

  Next, using the photoresist 20 as a mask, the amorphous silicon layer 17 other than the fuse element portion is removed by a dry etching method. At this time, the refractory metal such as TiN remaining on the third-layer metal wiring other than the fuse element is simultaneously removed with the same mask. In this way, the antireflection film on the metal wiring of the third layer remains only at the wiring connection portions at both ends of the fuse element.

Next, a silicon oxide film 24 and a silicon nitride film 25 are sequentially stacked as a final protective film (FIG. 16 (2)).
Finally, the silicon nitride film and the silicon oxide film, which are the final protective films on the bonding pads 19 that are in charge of electrical connection with the external terminals, are sequentially dry-etched to form openings (FIG. 16 (3)).

  As described above, the present invention employs a manufacturing method in which a fuse element forming step is added after processing the uppermost metal film, and the fuse element itself does not use a special film, and can be applied to various semiconductor manufacturing processes. It has the flexibility to be able to.

  The manufacturing method of the sixth embodiment of the present invention will be described below using FIGS. 17 and 18 as the tenth embodiment. Here, the structural difference between the sixth embodiment and the fifth embodiment is the opening portion of the final protective film. Therefore, the formation process up to the interlayer insulating film 22 on the second metal wiring 11 on the semiconductor substrate 1 (FIG. 17A), and the formation process of the third metal wiring 14 using the antireflection film 23 (FIG. 17). (2)), deposition process of amorphous silicon layer 17 for fuse element (FIG. 17 (3)), resist patterning process for fuse element processing (FIG. 18 (1)), etching process thereof, and silicon oxidation The deposition process of the final protective film made of the film and the silicon nitride film is the same as the manufacturing method of the fifth embodiment.

In the next processing of the final protective film, first, a patterned resist 20 is formed on the silicon nitride film. The resist 20 is a pattern partially opened on the fuse element region and the bonding pad region. Using this resist 20 as a mask, the silicon nitride film 25 is selectively removed by etching, whereby a laser fuse cut opening 10 and an opening in the bonding pad 19 are simultaneously formed in the fuse element region (FIG. 18 (2)). .
Furthermore, using another photoresist and another photomask, only the silicon oxide film on the bonding pad 19 is removed by etching (FIG. 18 (3)).

  Regarding the processing of the final protective film, the first photoresist for silicon nitride film processing is applied, the opening of the first photoresist on the silicon nitride film, and the silicon nitride film are removed by etching. The first processing method of removing the photoresist, applying the second photoresist, opening the second photoresist on the silicon oxide film, removing the silicon oxide film by etching, and removing the second photoresist is performed. It can be realized by adopting it.

  Alternatively, as a second processing method of the final protective film, the first photoresist coating, the opening of the first photoresist on the silicon nitride film, and the etching removal of the silicon nitride film are performed, followed by the first processing method. The method of applying the second photoresist, opening the second photoresist on the silicon oxide film, removing the silicon oxide film, and removing the first and second photoresists is employed without removing the photoresist. May be. The advantage of the second processing method of the final protective film is that the manufacturing process can be reduced by removing the first and second photoresists at the last time. However, the silicon nitride film at the edge of the bonding pad opening is used. It also has the effect of removing the damage.

  In the second photoresist opening in the first processing method of the final protective film, the opening is wider than the opening of the silicon nitride film already formed, so that the bonding pad opening due to the displacement of the second photoresist opening is achieved. The method of suppressing the generation of silicon oxide film residue is taken. Then, the silicon oxide film is removed by etching using the exposed silicon nitride film opening as a mask. However, the silicon oxide film in the bonding pad exposed when the second photoresist is opened may be damaged by the etching of the silicon oxide film. Inevitable. If there is a concern about long-term reliability failure due to the promotion of moisture ingress at the bonding pad edge by adopting the first method, the second processing method is adopted for the final protective film. Can be wiped out.

  In the second processing method of the final protective film, the second photoresist is covered as it is after the etching of the silicon nitride film, and the second photoresist is opened wider than the opening of the silicon nitride film. Since the first photoresist is hardened by the plasma etching process of the silicon nitride film and remains as it is, the hardened first photoresist can be used as an opening mask as it is when the next silicon oxide film is etched. Etching damage to the silicon nitride film can be suppressed.

  If the first photoresist used for etching is not sufficiently cured and is readily soluble in the solvent of the photoresist, UV curing may be performed before applying the second photoresist. Curing progresses to the inside of the resist by the UV curing treatment, resulting in a hardly soluble property, and there is no fear that the pattern of the first photoresist is destroyed by the solvent of the second photoresist. Also, there is an effect that the subsequent removal of the first and second photoresists becomes easy.

  By adopting the above-described method, the present invention eliminates the antireflection film at the bonding pad opening, and further avoids etching damage at the bonding pad opening edge, thereby providing excellent long-term reliability and a laser for the fuse element. A production method with improved cutability can be provided.

  The manufacturing method of the seventh embodiment of the present invention will be described below using FIGS. 9 and 10 as the eleventh embodiment. Here, the seventh embodiment is a manufacturing method in which the fuse element used in the fifth embodiment has a laminated structure of an amorphous silicon layer and a refractory metal film in accordance with the third embodiment. is there.

  Accordingly, the formation process up to the interlayer insulating film 22 on the second metal wiring 11 on the semiconductor substrate 1 (FIG. 9A), and the formation process of the third metal wiring 14 using the antireflection film 23 (FIG. 9). Up to (2)), the same manufacturing process is performed.

Next, a refractory metal film 18 made of TiN or the like and then an amorphous silicon layer 17 are laminated on the entire surface of the semiconductor substrate by sputtering (FIG. 9 (3)).
Next, after performing a resist patterning step (FIG. 10A) for processing the fuse element, the amorphous silicon layer 17 and the refractory metal film 18 are etched using the same photoresist as a mask. At that time, the antireflection film on the third metal wiring in the region other than the fuse element is also removed by etching with the same photoresist mask.

  Thereafter, the final protective film on the bonding pad 19 is removed (FIG. 10 (3)) through the final protective film deposition step (FIG. 10 (2)) made of the silicon oxide film 24 and the silicon nitride film 25. This is the same as the manufacturing method of the fifth embodiment.

  The manufacturing method of the eighth embodiment of the present invention will be described below using FIGS. 11 and 12 as the twelfth embodiment. Here, the structural difference between the eighth embodiment and the seventh embodiment is the opening portion of the final protective film. Accordingly, the formation process up to the interlayer insulating film 22 on the second metal wiring 11 on the semiconductor substrate 1 (FIG. 11A), and the formation process of the third metal wiring 14 using the antireflection film 23 (FIG. 11). (2)), a process of depositing the refractory metal film 18 for the fuse element and the amorphous silicon layer 17 (FIG. 11 (3)), a resist patterning process for processing the fuse element (FIG. 12 (1)), and its etching The processing steps and the deposition step of the final protective film made of the silicon oxide film and the silicon nitride film are the same as the manufacturing method of the seventh embodiment.

Regarding the processing of the next final protective film, first, the upper silicon nitride film 25 of the final protective film on the fuse element and the bonding pad is removed by etching using the same photoresist, and an opening for laser fuse cutting is performed. 10 and an opening on the bonding pad 19 is formed (FIG. 12B).
Further, using another photoresist and another photomask, only the silicon oxide film on the bonding pad 19 is removed by etching (FIG. 12 (3)).

At this time, a more detailed processing method for the final protective film is as follows. As described in the description of the manufacturing method of the sixth embodiment, the first photoresist is removed and then the second photoresist is used to remove the silicon oxide film. There is a first processing method for etching and removing a silicon oxide film by etching using a second photoresist while leaving the first photoresist, whichever method is adopted. I do not care.
In the above description, the refractory metal is not limited to Ti or TiN, but may be other Ti compounds.

  The present invention having the above-described structure and manufacturing method is not limited to the step-down series regulator and voltage detector described above, and can be applied to all products that perform fuse cutting to adjust the performance of a semiconductor integrated circuit. . Therefore, it goes without saying that the present invention can be applied to uses other than the power management IC.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 5 Polycrystalline silicon film 6 Gate electrode 7 Contact hole 8 First layer metal wiring 9 Gate insulating film 10 Laser fuse cut opening 11 Second layer metal wiring 12 N-type source / drain region 13 LOCOS insulating film 14 Metal wiring 15 in third layer 15 Via hole 16 BPSG film 17 Amorphous silicon film 18 High melting point metal film 19 Bonding pad 20 Photoresist 21 Fine metal wiring for internal circuit 22 Interlayer insulating film 23 Antireflection film 24 Silicon oxide film 25 Silicon nitride film 26 P-type well region 27 N-type channel impurity region 28 P-type channel impurity region 301 Fuse 1
302 Fuse 2
303 Fuse 3
304 Fuse 4

Claims (15)

A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
Two conductors made of metal spaced apart on the insulating film;
A first refractory metal film laminated on the conductor;
A fuse element formed of an amorphous silicon layer on the first refractory metal film and on a side surface of the conductor and provided in a region on the insulating film apart from the two conductors;
A semiconductor integrated circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein a second refractory metal film having the same shape as the amorphous silicon layer in plan view is provided under the amorphous silicon layer.   The semiconductor integrated circuit device is composed of at least two metal wiring layers, the conductor is the uppermost layer of the metal wiring layers, and a protective film is further provided on the uppermost metal wiring layer. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided.   The protective film includes a silicon oxide film and a silicon nitride film formed on the silicon oxide film, and an opening from which the silicon nitride film is removed is provided on the fuse element. The semiconductor integrated circuit device according to claim 3.   5. The semiconductor integrated circuit device according to claim 1, wherein the first refractory metal film is TiN or a Ti compound. 3. The semiconductor integrated circuit device according to claim 2, wherein the second refractory metal film is TiN or a Ti compound.   7. The semiconductor integrated circuit device according to claim 1, wherein a thickness of the amorphous silicon layer is in a range of 150 to 1000 mm.   4. The semiconductor integrated circuit device according to claim 3, wherein the uppermost metal wiring layer is used for wiring and bonding pads in the semiconductor integrated circuit device other than the fuse element.   9. The semiconductor integrated circuit device according to claim 8, wherein an antireflection film made of TiN or a Ti compound is not laminated on the uppermost metal wiring layer. A method of manufacturing a semiconductor integrated circuit device including a fuse element,
Forming an insulating film on the semiconductor substrate;
Laminating a first metal film and a first refractory metal film in this order on the insulating film;
The first metal film and the first refractory metal film are etched, and the first refractory metal film is disposed on the first metal film spaced apart from the fuse element region. Forming a conductor and forming a bonding pad in the bonding pad region;
Depositing an amorphous silicon layer on the two conductors, the bonding pad and the insulating film;
The fuse element region includes the amorphous silicon layer that covers the first refractory metal film and the side surfaces of the two conductors, and is provided in a region on the insulating film apart from the two conductors. Forming a fuse element; and
Removing the amorphous silicon layer and the first refractory metal film in the bonding pad region;
Depositing a protective film comprising a lower silicon oxide film and an upper silicon nitride film on the semiconductor substrate including the fuse element;
A protective film forming step of removing the protective film on the bonding pad;
A method for manufacturing a semiconductor integrated circuit device, comprising:   11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the silicon nitride film on the fuse element is removed in the protective film forming step. A step of depositing a second refractory metal film before the step of depositing the amorphous silicon layer;
In the step of forming the fuse element, the fuse element region covers the first refractory metal film and the side surfaces of the two conductors, and is provided in a region on the insulating film apart from the two conductors. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein a fuse element made of the amorphous silicon layer and the second refractory metal film formed is formed.   13. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein TiN or a Ti compound is used for the first refractory metal film.   13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein TiN or a Ti compound is used for the second refractory metal film.   15. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the thickness of the amorphous silicon layer is in a range of 150 to 1000 mm.

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