JP2007266499A - Nonvolatile semiconductor memory and method for fabrication thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory which makes it possible to form floating gate electrodes and resistors for polysilicon film memory cell transistors each having a different impurity density on the same substrate without gate insulating film damage. <P>SOLUTION: This nonvolatile semiconductor memory comprises a memory cell transistor and resistance element formed on a semiconductor substrate 1. The memory cell transistor comprises a floating gate electrode composed of polysilicon films 3A, 6A, an inter-electrode insulating film 9A formed on the floating gate electrode and a control gate electrode 10A formed on the inter-electrode insulating film 9A. The resistance element comprises a resistor composed of polysilicon films 3, 6, a cover film 7 covering the resistor and an intermediate insulating film 9B whose structure is identical to that of the inter-electrode insulating film 9A. The impurity densities of polysilicon films 3A, 6A of the floating gate electrode are higher than those of polysilicon films 3, 6 of the resistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory and a method for manufacturing the same, and is particularly used for a NAND flash memory.

  A nonvolatile semiconductor memory, for example, a NAND flash memory, has been recently installed in various electronic devices because it can be highly integrated while being nonvolatile.

  Here, the nonvolatile semiconductor memory includes a memory cell array and a peripheral circuit arranged in the peripheral portion as main components.

  The peripheral circuit is mainly composed of a transistor, but additionally includes a floating gate resistance element using a polysilicon film formed as a resistor at the same time as the formation of the polysilicon film serving as a floating gate electrode. It is out.

  In general, the polysilicon film of the floating gate electrode is composed of a polysilicon film doped with P (phosphorus) ions, and it is necessary to increase the concentration of P ions to prevent depletion of the gate when a voltage is applied.

  On the other hand, when a resistive element having the same resistance value is produced on the chip using a material having a high resistivity and a material having a low resistivity, the chip of the resistive element is better to use a material having a high resistivity. The upper occupied area can be reduced.

  Therefore, it is required to increase the resistivity of the polysilicon film of the floating gate resistance element, and it is necessary to reduce the concentration of P ions.

  For this purpose, the polysilicon films having different P ion concentrations as described above must be formed on the same chip. As one of the methods, there is a method in which a polysilicon film is first formed undoped, and thereafter, a necessary amount of ion implantation is separately performed on each of the memory cell portion, the peripheral transistor portion, and the resistance element portion ( For example, see Patent Document 1).

However, with the recent miniaturization of memory cell transistors, the thickness of the floating gate tends to be reduced. Therefore, in the method of doping P ions by ion implantation, the P ions penetrate through the thin floating gate and damage the tunnel oxide film (gate insulating film) of the memory cell transistor, leading to a decrease in manufacturing yield.
JP 2004-363234 A

  The present invention proposes a technique for forming floating gate electrodes and resistors of memory cell transistors of different impurity concentrations made of a polysilicon film on the same substrate without damaging the gate insulating film.

  A nonvolatile semiconductor memory according to the present invention includes a memory cell transistor and a resistance element formed on a semiconductor substrate. The memory cell transistor includes a floating gate electrode made of a polysilicon film, and a floating gate electrode. An inter-electrode insulating film to be formed, and a control gate electrode on the inter-electrode insulating film, wherein the resistance element is a resistor made of a polysilicon film, a cover film covering the resistor, and the cover film And an intermediate insulating film having the same structure as the interelectrode insulating film. The impurity concentration of the polysilicon film of the floating gate electrode is higher than the impurity concentration of the polysilicon film of the resistor.

  A method for manufacturing a nonvolatile semiconductor memory according to the present invention includes a step of simultaneously forming a floating gate electrode of a memory cell transistor and a polysilicon film serving as a resistor of a resistance element on a gate insulating film; Separating the gate electrode and the resistor, covering the surface of the resistor with a cover film that prevents diffusion of impurities, and diffusing the impurities into the floating gate electrode from a gas atmosphere containing impurities. And a step of forming an interelectrode insulating film of the memory cell transistor and an intermediate insulating film of the resistance element on the upper surface of the floating gate electrode and the cover film.

  According to the present invention, it is possible to form the floating gate electrode and the resistor of the memory cell having different impurity concentrations made of the polysilicon film on the same substrate without damaging the gate insulating film.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Overview
In the nonvolatile semiconductor memory according to the example of the present invention, the floating gate electrode of the memory cell transistor and the polysilicon film serving as the resistor of the resistance element are formed at the same time, and the upper surface of the polysilicon film serving as the resistor prevents diffusion of impurities. The impurity concentration of the polysilicon film of the floating gate electrode is higher than the impurity concentration of the polysilicon film serving as the resistor due to the diffusion of impurities after the cover film is formed. Features.

  As described above, a resistive element in which the polysilicon film that becomes the resistor of the resistance element is formed simultaneously with the polysilicon film that becomes the floating gate electrode of the memory cell transistor is defined as a floating gate resistance element.

  In the example of the present invention, a manufacturing method for obtaining the above structure is also proposed. The method starts with a step of forming a floating gate electrode and a polysilicon film serving as a resistor with respect to an active region surrounded by an element isolation insulating layer at a low impurity concentration at which the resistor can obtain a desired high resistivity. Each is formed consistently. Thereafter, the above-described cover film is formed on the surface of the polysilicon film serving as a resistor, and impurities are diffused over the entire surface of the semiconductor substrate by Gas Phase Doping (hereinafter, GPD).

  As a result, the polysilicon film that becomes the floating gate electrode can be made to have an impurity concentration that does not cause depletion of the gate, and the polysilicon film that becomes the resistor is covered with the cover film, so that the impurity concentration in the polysilicon film changes. Without being able to keep the desired high resistivity.

  Therefore, polysilicon films having different impurity concentrations can be formed on the same chip.

  Further, by performing impurity diffusion using GPD, the impurity can be doped without damaging the gate insulating film. Therefore, the manufacturing yield can be improved.

2. Embodiment
Next, some preferred embodiments will be described.

  The definition of the floating gate resistance element is as described in the outline. A cover film that prevents diffusion of impurities by GPD is defined as a GPD block film.

  Further, FIG. 1 shows an example of a layout of a circuit constituting the NAND flash memory in this embodiment. The region A shown in FIG. 1 will be described as a memory cell portion and the region B as a resistance element portion.

(1) First embodiment
(A) Structure
The structure of the memory cell portion and the resistance element portion of the NAND flash memory according to this embodiment will be described with reference to FIGS.

  2 is a plan view of the memory cell portion and the resistance element portion of the NAND flash memory according to the present embodiment, FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2, and FIG. The cross section which follows the IV-IV line of is shown.

  In the memory cell portion, the polysilicon films 3A and 6A having a two-layer structure serving as floating gate electrodes are formed on the tunnel oxide film (gate insulating film) 2A in the activation region surrounded by the element isolation insulating layer 5. The polysilicon films 3A and 6A, for example, use P ions as impurities for obtaining conductivity, and have a concentration sufficient to prevent depletion of the gate due to GPD with respect to a polysilicon film formed at a low P ion concentration. It is formed by doping P ions.

  Further, an ONO film 9A is formed as an interelectrode insulating film so as to cover a part of the upper surface and side surfaces of the polysilicon film 6A. Further, a polysilicon film 10A serving as a control gate electrode is formed so as to cover part of the upper surface and side surfaces of the polysilicon film 6A serving as a floating gate electrode via the ONO film 9A. This polysilicon film 10A also functions as a word line. The coupling ratio can be improved by using a structure in which the floating gate electrode and the control gate electrode overlap with the side surface via the inter-electrode insulating film as in this embodiment mode.

  A diffusion layer 13 is formed on the surface of the semiconductor substrate 1. The diffusion layer 13 is shared by two adjacent memory cell transistors. Further, the insulating layer 11 is formed so as to cover the entire surface of the memory cell portion.

  In the resistance element portion, the polysilicon films 3 and 6 serving as the resistors of the floating gate resistance element have a low P ion concentration, and the element isolation insulation is provided on the insulating film 2B in the activation region surrounded by the element isolation insulating layer 5. It is formed so as to coincide with the upper end of the layer 5. Although the insulating film 2B is formed simultaneously with the tunnel oxide film (gate insulating film) 2A, it does not function as a gate insulating film.

  A SiN film 7 serving as a GPD block film is formed on the upper surface of the polysilicon film 6. When this SiN film 7 is subjected to GPD, P ions diffuse into the polysilicon films 3 and 6 serving as resistors. To stop doing.

  The ONO film 9B and the polysilicon films 10B and 10C are sequentially formed on the SiN film 7. The ONO film 9B is formed simultaneously with the ONO film 9A in the memory cell portion. The polysilicon films 10B and 10C are formed simultaneously with the polysilicon film forming the polysilicon film (word line) 10A. An opening X is formed in the ONO film 9 </ b> B and the SiN film 7, and a polysilicon film 10 </ b> B as an intermediate layer is embedded so as to be connected to the polysilicon film 6. The polysilicon film 10C is provided as a dummy layer for planarizing the surface of the insulating layer 11.

  The insulating layer 11 covers the entire surface of the resistance element portion, and the contact portion 12A is buried in the contact hole Y formed in the insulating layer 11 so as to be connected to the polysilicon film 10B. Metal wiring 12B is formed.

  In the floating gate resistance element as described above, the polysilicon film serving as the resistor can be formed at the same time as the floating gate electrode of the memory cell transistor. Therefore, the nonvolatile semiconductor memory including the memory cell transistor having a stacked gate structure Used as a resistance element. Further, the floating gate resistance element can stably obtain a resistance value of several hundred Ω, and the substrate bias effect that occurs when the diffusion layer is used as the resistance element does not occur.

  Hereinafter, a method for manufacturing the memory cell portion and the resistance element portion of the NAND flash memory according to the example of the present invention having such a structure will be described.

(B) Manufacturing method
A method for manufacturing the memory cell portion and the resistance element portion of the NAND flash memory according to the present embodiment will be described with reference to FIGS. (A) of each figure shows the top view of a memory cell part and a resistive element part, (b) shows sectional drawing of (a).

  First, as shown in FIG. 5, a polysilicon film 3 having a low P ion concentration that allows the floating gate resistance element to obtain a desired high resistivity is formed by using, for example, a CVD (Chemical Vapor Deposition) method. A film thickness of about 50 nm is formed on the tunnel oxide film (gate insulating film) 2A and the insulating film 2B on the surface of the semiconductor substrate 1. Next, as a mask layer, for example, after the SiN film 4 is formed on the polysilicon film 3, a resist pattern is formed on the SiN film 4 by PEP (Photo Engraving Process), and the resist pattern is used as a mask. The SiN film 4 is patterned. After removing the resist, using the SiN film 4 as a mask, the polysilicon film 3, the tunnel oxide film (gate insulating film) 2A and the insulating film 2B, and a part of the upper surface of the semiconductor substrate 1 are sequentially etched to form an element isolation groove. It is formed. Thereafter, for example, silicon oxide is formed on the entire surface so as to fill the element isolation trench, and surface polishing is performed on the silicon oxide by CMP (Chemical Mechanical Polish) until the upper surface of the SiN film 4 is exposed. Then, the element isolation insulating layer 5 is formed. The polysilicon film 3 may not be doped with impurities.

  Next, for example, after the SiN film 4 is peeled off with hot phosphoric acid, the element isolation insulating layer 5 is etched with, for example, diluted hydrofluoric acid to expose a part of the side surface of the polysilicon film 3, as shown in FIG. It becomes a structure.

  Subsequently, for example, after a polysilicon film is formed on the entire surface by CVD, surface polishing is performed by CMP so that the upper end of the polysilicon film coincides with the upper end of the element isolation insulating layer 5, as shown in FIG. Thus, for example, a polysilicon film 6 having a thickness of about 50 nm is formed.

  Thereafter, as shown in FIG. 8, a SiN film 7 to be a GPD block film is formed on the entire surface of the memory cell portion and the resistance element portion by, eg, CVD.

  Next, a resist is applied to the entire surface of the memory cell portion and the resistance element portion, a resist pattern is formed by PEP so that the upper surface of the SiN film 7 in the memory cell portion is exposed, and then the SiN film 7 is etched. . Then, as shown in FIG. 9, the patterned resist 8 is used as a mask, and the upper surface of the polysilicon film 6 in the resistance element portion is covered with the SiN film 7 as a GPD block film, and the polysilicon film 6 in the memory cell portion is covered. The upper surface is exposed. With this structure, impurities can be diffused by GPD only to the polysilicon films 3 and 6 in the memory cell portion.

Subsequently, after removing the resist 8, the semiconductor substrate 1 is placed in a PH ₃ gas atmosphere diluted with an inert gas or hydrogen gas, for example, so that the floating gate electrode has a P ion concentration that does not cause gate depletion. Heat treatment is performed, and P ions are diffused by GPD. Then, as shown in FIG. 10, in the memory cell portion, the P ions are diffused from the upper surface of the exposed polysilicon film to the vicinity of the tunnel oxide film (gate insulating film) 2A, and the polysilicon films 3A and 6A having a high P ion concentration. Is formed. At this time, diffusion of P ions by GPD causes P ions to penetrate through the thin floating gate electrode and damage the tunnel oxide film (gate insulating film) 2A of the memory cell transistor as in the ion implantation method. There is no.

  On the other hand, since the upper surface of the polysilicon film 6 is covered with the SiN film 7 which is a GPD block film in the resistance element portion, even if GPD is performed on the entire surface of the semiconductor substrate 1, P ions do not diffuse into the silicon films 3 and 6. Therefore, the P ion concentration of the polysilicon films 3 and 6 serving as the resistors is maintained at a value at which a desired high resistivity can be obtained.

  Subsequently, as shown in FIG. 11, the element isolation insulating layer 5 is etched back by, for example, dilute hydrofluoric acid treatment to expose part of the side surface of the polysilicon film 6A in the memory cell portion. At this time, in the resistance element portion, the SiN film 7 covers the upper surface of the resistance element portion, so that the element isolation insulating layer 5 is not etched back. After the dilute hydrofluoric acid treatment, ONO films 9A and 9B are formed in the memory cell portion and the resistance element portion, respectively, by, for example, the CVD method. Thereafter, a resist pattern is formed on the ONO film 9B of the resistance element portion, and etching is performed using the resist pattern as a mask so that the opening X reaches the polysilicon film 6 and the ONO film 9B and the SiN film. 7 is formed.

  Next, after a polysilicon film is formed on the ONO films 9A and 9B by, for example, a CVD method, a resist pattern is formed on the polysilicon film by PEP. Using the resist pattern as a mask, the ONO films 9A and 9B are formed. Etch the upper polysilicon film. Then, as shown in FIG. 12, a polysilicon film 10A to be a control gate electrode is formed in the memory cell portion, and a polysilicon film 10B as an intermediate layer and a polysilicon film 10C as a dummy layer are formed in the resistance element portion. It is formed. The polysilicon film 10B is embedded in the opening X formed in the ONO film 9B and the SiN film 7 so as to be connected to the polysilicon film 6. Further, in the memory cell portion, the ONO film 9A, the polysilicon films 3A and 6A, and the tunnel oxide film (gate insulating film) 2A in the region for forming the diffusion layer are sequentially etched, and the upper surface of the semiconductor substrate 1 is exposed.

  Subsequently, when ion implantation is performed using the polysilicon film 10A as a mask, a diffusion layer 13 is formed in a self-aligned manner in the memory cell portion as shown in FIG. For example, a CVD method is used on the entire surface of the resistance element portion. In the resistance element portion, contact holes Y are formed at both ends of the insulating layer 11 so as to reach the upper surface of the polysilicon film 10B, and then contact portions are formed in the contact holes Y. Thereafter, the metal wiring 12B is formed on the contact portion, whereby the memory cell portion and the resistance element portion of the NAND flash memory according to the present embodiment are completed.

  Since the memory cell portion and the resistance element portion of the NAND flash memory manufactured by the above steps can form polysilicon films having different P ion concentrations on the same semiconductor substrate 1, the resistor polysilicon film 3 , 6 can obtain a polysilicon film having a low P ion concentration and a high resistivity, and can reduce the area of the resistance element portion. On the other hand, the polysilicon films 3A and 6A of the floating gate electrode may form a floating gate electrode that does not cause gate depletion by diffusing P ions by GPD with respect to the polysilicon film having a low P ion concentration. it can.

  Further, by performing impurity diffusion using GPD, the tunnel oxide film (gate insulating film) 2A is not damaged by P ions as in the ion implantation method, so that the manufacturing yield can be improved.

  In addition, if the doping is performed at the same time as the formation of the polysilicon film, the film forming speed is lowered. However, this problem can be avoided by performing doping with GPD after the formation of the polysilicon film.

(2) Second embodiment
(A) Structure
The structure of the floating gate electrode of the memory cell transistor and the resistor of the floating gate resistance element is not limited to a polysilicon film having a two-layer structure, and may be, for example, a polysilicon film having a one-layer structure.

  In this embodiment, the case where the structure of the floating gate electrode of the memory cell transistor and the resistor of the floating gate resistance element is composed of a single layer polysilicon film will be described with reference to FIGS. .

  14 shows a plan view of the memory cell portion and the resistance element portion of the NAND flash memory according to the present embodiment, FIG. 15 shows a cross section taken along line XV-XV in FIG. 14, and FIG. The cross section which follows the XVI-XVI line of is shown.

  In the memory cell portion, the polysilicon film 3A serving as the floating gate electrode is formed on the tunnel oxide film (gate insulating film) 2A in the activation region surrounded by the element isolation insulating layer 5. The polysilicon film 3A is formed by doping a polysilicon film formed with a low P ion concentration with a sufficient concentration of P ions that does not cause gate depletion due to GPD.

  The ONO film 9A as the interelectrode insulating film, the polysilicon film 10A as the control gate electrode (word line), and the diffusion layer 13 have the same structure as in the first embodiment. Further, the insulating layer 11 is formed so as to cover the entire surface of the memory cell portion.

  In the resistance element portion, the polysilicon film 3 serving as a resistor of the floating gate resistance element has a low P ion concentration and is formed on the insulating film 2B in the activation region surrounded by the element isolation insulating layer 5. On the upper surface of the polysilicon film 3, a SiN film 7 serving as a GPD block film is formed to prevent P ions from diffusing into the polysilicon film 3 serving as a resistor when GPD is performed.

  The ONO film 9B, the polysilicon film 10B as an intermediate layer, and the polysilicon film 10C as a dummy layer have the same structure as that of the first embodiment. Furthermore, the insulating layer 11 covers the entire surface of the resistance element portion, and a contact portion 12A and a metal wiring 12B are formed.

  Hereinafter, a method for manufacturing the memory cell portion and the resistance element portion of the NAND flash memory according to the example of the present invention having such a structure will be described.

(B) Manufacturing method
First, in a process similar to the process shown in FIG. 5 of the first embodiment, in the memory cell part and the resistance element part, on the tunnel oxide film (gate insulating film) 2A and the insulating film 2B formed on the semiconductor substrate 1. Then, the polysilicon film 3 and the element isolation insulating layer 5 are sequentially formed. The polysilicon film 3 has a P ion concentration that allows the resistor to obtain a desired high resistivity. For example, the polysilicon film 3 has a film thickness of about 100 nm by a CVD method and becomes a floating gate electrode and a resistor having a single layer structure. Formed.

  Thereafter, in a process similar to the process shown in FIGS. 6 to 13 of the first embodiment, only the upper surface of the resistance element portion is covered with the SiN film 7 serving as a GPD block film, and P ions are diffused by GPD. Then, in the memory cell portion, without damaging the tunnel oxide film (gate insulating film) 2A, the P ions diffuse from the exposed upper surface of the polysilicon film to the vicinity of the tunnel oxide film (gate insulating film) 2A. A polysilicon film 3A having a high concentration is formed.

  On the other hand, in the resistance element portion, since the upper surface of the polysilicon film 3 is covered with the SiN film 7 which is a GPD block film, the diffusion of P ions does not occur in the polysilicon film 3, and the polysilicon film serving as a resistor The P ion concentration of 3 is kept at a value that provides the desired high resistivity.

  Thereafter, ONO films 9A and 9B and polysilicon films 10A, 10B, and 10C are simultaneously formed in the memory cell portion and the resistance element portion, respectively. Furthermore, after the diffusion layer 13 is formed in the memory cell portion, the insulating layer 11 is formed on the entire surface of the memory cell portion and the resistance element portion. Thereafter, a contact portion is formed in the resistance element portion and a metal wiring 12B is formed on the contact portion, thereby completing the memory cell portion and the resistance element portion of the NAND flash memory according to the present embodiment.

  As described above, even when the polysilicon film serving as the floating gate electrode and the resistor has a single layer structure, the polysilicon film serving as the floating gate electrode having a high P ion concentration and causing no gate depletion, and the P ion A polysilicon film having a low concentration and a high resistivity can be formed on the same semiconductor substrate without damaging the gate insulating film, and the same effect as that of the first embodiment can be obtained. it can.

3. Modified example
(A) Structure
In the above-described embodiment, the example in which the SiN film is used as the GPD block film has been described. However, the GPD block film covering the resistance element portion only needs to prevent the diffusion of impurities by GPD, and may be a silicon oxide film such as a TEOS film, for example.

  In that case, the TEOS film is also removed during the dilute hydrofluoric acid treatment for the element isolation insulating layer 5 after GPD. As shown in FIG. 17, the structure of the resistance element portion includes the polysilicon film 6 and the dilute hydrofluoric acid treatment. There is no GPD block film between the ONO films 9B formed later.

  A manufacturing method in the case where a TEOS film is used as the GPD block film will be described below based on the first embodiment.

(B) Manufacturing method
First, in a process similar to the process shown in FIGS. 5 to 9 of the first embodiment, the tunnel oxide film (gate insulating film) 2A and the insulating film formed on the semiconductor substrate 1 in the memory cell part and the resistance element part. Polysilicon films 3 and 6 and element isolation insulating layer 5 are sequentially formed on film 2B. The polysilicon films 3 and 6 are formed with a P ion concentration that allows the resistor of the floating gate resistance element to obtain a desired high resistivity.

  Next, as shown in FIG. 18, after a TEOS film 14 is formed as a GPD block film on the upper surface of the resistance element portion, P ions are diffused by GPD. Then, in the memory cell portion, P ions diffuse from the exposed upper surface of the polysilicon film, do not damage the tunnel oxide film (gate insulating film) 2A, and become a floating gate electrode that does not cause gate depletion. Silicon films 3A and 6A are formed.

  On the other hand, in the resistance element portion, since the upper surface of the polysilicon film 6 is covered with the TEOS film 14 which is a GPD block film, the P ion concentration of the polysilicon films 3 and 6 does not change.

  Subsequently, in order to expose a part of the side surface of the polysilicon film 6A in the memory cell portion, the element isolation insulating layer 5 is etched back by dilute hydrofluoric acid treatment. Then, the TEOS film 14 is also removed at the same time.

  Thereafter, when a process similar to the process shown in FIGS. 11 and 13 of the first embodiment is performed, the memory cell part and the resistance element part of the NAND flash memory in the present modification shown in FIG. 17 are completed.

(C) Summary
As described above, even when the GPD block film is removed after the impurity diffusion by GPD, the polysilicon film serving as a resistor having a low impurity concentration and a high resistivity, the impurity concentration is high, and the gate is depleted. A polysilicon film serving as a floating gate electrode that does not occur can be formed on the same substrate without damaging the gate insulating film.

  In this modification, the case where the TEOS film is used as the GPD block film in the first embodiment has been described. However, even in the case where the TEOS film is used as the GPD block film in the second embodiment, Similar effects can be obtained.

  Further, when the SiN film is used as the GPD block film and this SiN film is removed after GPD, the same effect as in the present modification can be obtained.

4). Application examples
(A) Structure Depletion of the gate electrode is a problem that occurs not only in memory cell transistors but also in MOS transistors (hereinafter referred to as peripheral circuit transistors) used in peripheral circuits.

  Therefore, the example of the present invention can be used even when the polysilicon film to be the gate electrode of the peripheral circuit transistor is formed with a low P ion concentration as described in the first and second embodiments. it can.

  Hereinafter, the structure of the peripheral circuit transistor will be described with reference to FIG. 19 using the region C shown in FIG. 1 as the peripheral circuit portion.

  FIG. 19A is a plan view of the memory cell portion, the peripheral circuit portion, and the resistance element portion, and FIG. 32B is a cross-sectional view taken along the line XXXII-XXXII.

  The structure of the memory cell part and the resistance element part is the structure shown in the second embodiment, and the floating gate electrode and the resistor are formed of a single layer polysilicon film. The upper surface of the polysilicon film 3 serving as a resistor is covered with a SiN film 7 serving as a GPD block film, so that diffusion of impurities due to GPD is prevented.

  In the peripheral circuit portion, the polysilicon film 3C serving as the gate electrode of the peripheral circuit transistor is formed by GPD with respect to the low P ion concentration polysilicon film formed simultaneously with the floating gate electrode and the polysilicon film serving as the resistor. By doping ions, the gate is not depleted.

  On the polysilicon film 3C, an ONO film 9C and a polysilicon film 10D are formed simultaneously with the formation of the ONO film 9A and the polysilicon film (word line) 10A of the memory cell transistor. An opening XA is formed in the ONO film 9C so that the polysilicon film 10D is connected to the polysilicon film 3C.

  Further, a diffusion layer 13C to be a source / drain region of the peripheral circuit transistor is formed on the surface of the semiconductor substrate, and a contact portion 12C and a metal wiring 12D are formed in the diffusion layer 13C and the polysilicon film 10D.

  Below, the manufacturing method of this application example is demonstrated.

(B) Manufacturing method
The manufacturing method of this application example will be described with reference to FIGS.

  A polysilicon film 3 and an element isolation insulating layer 5 are sequentially formed on the tunnel oxide film 2A, the gate insulating film 2C, and the insulating film 2B formed on the semiconductor substrate 1 in the same process as the process shown in the second embodiment. It is formed. The polysilicon film 3 is formed with a P ion concentration at which the resistor can obtain a desired high resistivity. Subsequently, an SiN film to be a GPD block film is formed on the upper surfaces of the memory cell portion, the peripheral circuit portion, and the resistance element portion, and then the upper surface of the polysilicon film 3 in the memory cell portion and the peripheral circuit portion is exposed. Then, the SiN film is removed by etching so that only the upper surface of the resistance element portion is covered with the SiN film 7.

Next, for example, the semiconductor substrate 1 is heat-treated in a PH ₃ gas atmosphere diluted with an inert gas or hydrogen gas so that the gate does not deplete, and diffusion of P ions by GPD is performed. . Then, as shown in FIG. 20, similarly to the floating gate electrode of the memory cell portion described in the second embodiment, also in the peripheral circuit portion, from the upper surface of the polysilicon film where the P ions are exposed to the vicinity of the gate electrode 2C. A polysilicon film 3C having a high P ion concentration is formed by diffusion. Since the polysilicon film 3C has a high P ion concentration, the gate is not depleted. Further, the diffusion of P ions by GPD does not damage the gate insulating film 2C.

  In the resistance element portion, since the surface of the polysilicon film 3 is covered with the SiN film 7 which is a GPD block film, even if GPD is performed on the entire surface of the semiconductor substrate 1, P ions are applied to the polysilicon film 3. No diffusion occurs. Therefore, the concentration of P ions in the polysilicon film 3 serving as a resistor is maintained at a value that provides a desired high resistivity.

  Next, the element isolation insulating layer 5 in the memory cell portion is etched back to expose a part of the side surface of the polysilicon film 3A, and then the interelectrode insulating film is formed in the memory cell portion as shown in FIG. The ONO film 9A is formed, and at the same time, ONO films 9B and 9C are formed in the resistance element portion and the peripheral circuit portion, respectively. Thereafter, openings X and XA reaching the polysilicon films 3 and 3C are formed in the ONO films 9B and 9C and the SiN film 7 by etching, respectively.

  Subsequently, a polysilicon film is formed on the upper surfaces of the ONO films 9A to 9C, a resist pattern is formed on the polysilicon film by PEP, and the resist pattern is used as a mask to the polysilicon films on the ONO films 9A to 9C. Etching is performed. Then, a polysilicon film 10A to be a control gate electrode is formed in the memory cell portion, a polysilicon film 10B to be an intermediate layer and a polysilicon film 10C to be a dummy layer in the resistance element portion, and an intermediate layer in the peripheral circuit portion. A polysilicon film 10D is formed. The polysilicon films 10B and 10D are connected to the polysilicon films 3 and 3C, respectively. Thereafter, in the memory cell portion and the peripheral circuit portion, the ONO films 9A and 9C, the polysilicon films 3A and 3C, the tunnel oxide film (gate insulating film) 2A, and the gate insulating film 2C in the region for forming the diffusion layer are sequentially etched. The upper surface of the semiconductor substrate 1 is exposed.

  Subsequently, as shown in FIG. 22, when ion implantation is performed using the polysilicon films 10A and 10C as masks, diffusion layers 13 and 13C are formed in a self-aligned manner, and then the insulating layer 11 is formed on the entire surface. . Further, in the peripheral circuit portion, the contact hole YA reaching the polysilicon film 10D and the diffusion layer 13C is formed in the insulating film 11, the contact portion 12C is embedded in the contact hole YA, and the metal wiring 12D is formed above the contact portion 12C. It is formed. In the resistance element portion, a contact hole Y reaching the polysilicon film 10B is formed in the insulating layer 11, the contact portion is buried in the contact hole Y, and a metal wiring 12B is formed above the contact portion. The memory cell portion, the resistance element portion, and the peripheral circuit portion of the NAND flash memory are completed.

(C) Summary
As described above, in the peripheral circuit transistor, the surface of the polysilicon film having a low impurity concentration which becomes the gate electrode is exposed, and the impurity is diffused by GPD. As a result, a polysilicon film which is a resistor having a low impurity concentration and a high resistivity and a gate electrode which has a high impurity concentration and does not cause gate depletion without damaging the gate insulating film of the peripheral circuit transistor. They can be formed on the same substrate.

5). Other
According to the example of the present invention, polysilicon films having different impurity concentrations can be formed on the same substrate without damaging the gate insulating film.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

4 is a layout of a nonvolatile semiconductor memory in an example of the present invention. The top view of the memory cell part and resistive element part in 1st Embodiment. Sectional drawing which follows the III-III line | wire of FIG. Sectional drawing which follows the IV-IV line of FIG. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view and sectional drawing which show 1 process of the manufacturing process of 1st Embodiment. The top view of the memory cell part and resistance element part in 2nd Embodiment. Sectional drawing which follows the XV-XV line | wire of FIG. Sectional drawing which follows the XVI-XVI line | wire of FIG. The top view and sectional drawing which show the structure of a modification. The top view and sectional drawing which show 1 process of the manufacturing process of a modification. The top view and sectional drawing which show the structure of an application example. The top view and sectional drawing which show 1 process of the manufacturing process of an application example. The top view and sectional drawing which show 1 process of the manufacturing process of an application example. The top view and sectional drawing which show 1 process of the manufacturing process of an application example.

Explanation of symbols

  1: semiconductor substrate, 2A: gate insulating film (tunnel oxide film), 2B: insulating film, 2C: gate insulating film, 3, 6: polysilicon film (resistor), 3A, 6A: polysilicon film (floating gate electrode) ), 3C: polysilicon film (gate electrode), P: P ions, 4: mask layer, 5: element isolation insulating layer, 7: SiN film (GPD block film), 8: resist, 9A, 9B, 9C: ONO Film, 10A: polysilicon film (control gate electrode), 10B, 10D: polysilicon film (intermediate layer), 10C: polysilicon film (dummy layer), 11: interlayer insulating film, 12A, 12C: contact portion, 12B, 12D: metal wiring, 13, 13C: diffusion layer, 14: TEOS film (GPD block film).

Claims (5)

  A memory cell transistor formed on a semiconductor substrate; and a resistance element, wherein the memory cell transistor includes a floating gate electrode made of a polysilicon film, an interelectrode insulating film formed on the floating gate electrode, A control gate electrode on the interelectrode insulating film, and the resistance element is formed on the cover film, a cover film covering the resistor, a resistor made of a polysilicon film, and the interelectrode insulating film And an intermediate insulating film having the same structure as that of the floating gate electrode, wherein the impurity concentration of the polysilicon film of the floating gate electrode is higher than the impurity concentration of the polysilicon film of the resistor.   The semiconductor device further includes a peripheral circuit transistor formed on the semiconductor substrate, the peripheral circuit transistor having a gate electrode made of a polysilicon film, and the impurity concentration of the polysilicon film of the gate electrode The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory has an impurity concentration higher than that of the silicon film.   The nonvolatile semiconductor memory according to claim 1, wherein the resistor, the floating gate electrode, and the gate electrode are made of one or more polysilicon films.   Simultaneously forming a floating gate electrode of the memory cell transistor and a polysilicon film serving as a resistor of the resistive element on the gate insulating film; separating the polysilicon film into the floating gate electrode and the resistor; A step of covering the surface of the resistor with a cover film that prevents diffusion of impurities; a step of diffusing the impurities into the floating gate electrode from a gas atmosphere containing impurities; and top surfaces of the floating gate electrode and the cover film And a step of forming an inter-electrode insulating film of the memory cell transistor and an intermediate insulating film of the resistive element.   The nonvolatile semiconductor according to claim 4, wherein the polysilicon film is further separated into a gate electrode of a peripheral circuit transistor, and diffuses the impurity also into the gate electrode from a gas atmosphere containing the impurity. Memory manufacturing method.

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