JP2021086952A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device including a resistive element which has high accuracy of a resistance value and in which a layout region can be easily reduced.SOLUTION: A method for manufacturing a semiconductor device 100 for forming a resistive element 23 in an interlayer insulation film 14 includes an etching stopper film forming step, an interlayer insulation film forming step, a trench forming step, and a resistive element forming step. The etching stopper film forming step forms an etching stopper film 21 which is harder to remove than an interlayer insulation film 14 by etching processing. The interlayer insulation film forming step forms an interlayer insulation film 14 so as to cover the etching stopper film 21. The trench forming step forms a linear trench 22 by etching processing to a depth reaching from an upper surface of the interlayer insulation film 14 to the etching stopper film 21. The resistive element forming step forms the resistive element 23 so as to lie along a shape of the trench 22.SELECTED DRAWING: Figure 1

Description

The present invention relates to a method for manufacturing a semiconductor device and the semiconductor device.

Among semiconductor devices in which fine elements are formed on a semiconductor substrate such as silicon, there are those in which analog circuits are formed by combining MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistor), resistance elements, fuse elements, and the like. ..

For example, in semiconductor devices in which analog circuits such as voltage regulators, voltage detectors, and switching regulators are formed, miniaturization has been conventionally required, and it is important to reduce the layout area of each semiconductor element.

Therefore, for the purpose of reducing the layout area, an insulating film is formed on the inner wall surface of the vertical groove of the substrate and is embedded in the vertical groove with the insulating film interposed therebetween, and has a resistance width in the vertical direction of the substrate and the substrate. A "vertical" resistance element using a resistor having a resistance length in the horizontal direction has been proposed (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 8-32030

On one aspect, it is an object of the present invention to provide a method for manufacturing a semiconductor device having a resistance element having a resistance element whose layout area can be easily reduced and having a high accuracy of resistance value.

In one embodiment, the method of manufacturing a semiconductor device is
A method for manufacturing a semiconductor device in which a resistance element is formed in an interlayer insulating film.
An etching stopper film forming step of forming an etching stopper film which is harder to remove by an etching process than the interlayer insulating film,
An interlayer insulating film forming step of forming the interlayer insulating film so as to cover the etching stopper film, and
A trench forming step of forming a linear trench by the etching process from the upper surface of the interlayer insulating film to a depth reaching the etching stopper film.
A resistance element forming step of forming the resistance element so as to follow the shape of the trench,
including.

On one aspect, it is possible to provide a method for manufacturing a semiconductor device having a resistance element whose layout area can be easily reduced and whose resistance value is highly accurate.

FIG. 1 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is an explanatory view showing the upper surface of the semiconductor device shown in FIG. FIG. 3 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 5 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 7 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 8 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 9 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 10 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 11 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 12 is a circuit diagram showing an example of a resistance circuit when a conventional resistance element is used. FIG. 13 is an explanatory view showing an upper surface of a conventional resistance element in the resistance circuit shown in FIG. FIG. 14 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. FIG. 15 is a circuit diagram showing a resistance circuit when the resistance element of the fourth embodiment is used. FIG. 16 is an explanatory view showing the upper surface of the resistance element of the fourth embodiment in the resistance circuit shown in FIG.

The method for manufacturing a semiconductor device according to an embodiment of the present invention is a method for manufacturing a semiconductor device in which a resistance element is formed in an interlayer insulating film, and forms an etching stopper film which is more difficult to remove by an etching process than an interlayer insulating film. The etching stopper film forming step, the interlayer insulating film forming step of forming the interlayer insulating film so as to cover the etching stopper film, and the linear trench by the etching process from the upper surface of the interlayer insulating film to the depth reaching the etching stopper film. A trench forming step of forming the above and a resistance element forming step of forming a resistance element along the shape of the trench are included, and if necessary, other steps are included.

The semiconductor device according to the embodiment of the present invention is a semiconductor device having a resistance element in the interlayer insulating film so as to cover the etching stopper film, which is more difficult to remove by the etching process than the interlayer insulating film, and the etching stopper film. An interlayer insulating film is formed, a trench formed from the upper surface of the interlayer insulating film to a depth reaching the etching stopper film, a resistance element formed along the shape of the trench, and further, if necessary. It has other parts or members.

The semiconductor device according to the embodiment of the present invention can be suitably manufactured by the method for manufacturing the semiconductor device according to the embodiment of the present invention. Further, the etching stopper film can be preferably formed by the etching stopper film forming step, the interlayer insulating film can be preferably formed by the interlayer insulating film forming step, and the trench can be preferably formed by the trench forming step. The resistance element can be preferably formed by the resistance element forming step. Therefore, in the following, while explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention, the semiconductor device according to the embodiment of the present invention will also be described.

The method for manufacturing a semiconductor device according to an embodiment of the present invention is based on the following findings.
In the technique for forming the "vertical" resistance element described in Patent Document 1, the opening of the vertical groove (trench) of the substrate becomes an elongated linear shape, so that the layout area can be easily reduced, but the depth of the trench can be reduced. The deeper the value, the lower the accuracy of the depth due to the etching process. Therefore, there is a problem that the dimensional accuracy of the resistance element formed on the inner wall surface of the trench is lowered, and the accuracy of the resistance value is lowered.
Therefore, the method for manufacturing a semiconductor device according to an embodiment of the present invention includes a step of forming an etching stopper film on the lower surface of the interlayer insulating layer to make the etching depth constant, and an etching process in the interlayer insulating layer. It includes a step of forming a trench in the etching and a step of directly forming a "vertical" resistance element on the inner wall surface of the formed trench. As a result, the method for manufacturing a semiconductor device of the present invention can easily reduce the layout area of the resistance element and increase the accuracy of the depth of the trench to improve the dimensional accuracy of the resistance element directly formed on the inner wall surface of the trench. Since it is improved, the accuracy of the resistance value can be increased.
The accuracy of the resistance value means the degree of variation with respect to the target resistance value.

Next, as an example of the semiconductor device of the present invention, each embodiment in which a MOS transistor is formed in addition to the resistance element on the semiconductor substrate will be described with reference to FIGS. 1 to 9.
In each embodiment, the semiconductor device 100 is a semiconductor device having a MOS transistor and a resistance element, but specifically, it may be a semiconductor device in which analog circuits such as a voltage regulator, a voltage detector, and a switching regulator are formed. Good.

The drawings are schematic, and the relationship between the film thickness and the plane dimensions, the ratio of each film thickness, etc. are not as shown in the drawings. Further, in a semiconductor substrate, the surface on the side where other films or layers are laminated by using the semiconductor manufacturing process is referred to as "upper surface", and the surface on the back surface side of the upper surface is referred to as "lower surface". Further, in the following, the quantity, position, shape, structure, size, etc. of a plurality of films and semiconductor elements obtained by structurally combining these are not limited to the embodiments shown below, and the present invention is carried out. The preferred quantity, position, shape, structure, size, etc. can be obtained.

[First Embodiment]
(Manufacturing method of semiconductor devices and semiconductor devices)
FIG. 1 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is an explanatory view showing the upper surface of the semiconductor device shown in FIG. 1, and shows only the configuration necessary for the explanation.
Note that FIG. 1 is a diagram schematically showing a cross section of line AA shown in FIG. Further, in FIG. 2, the dotted line region of the MOS transistor forming region M indicates a region in which the MOS transistor is formed.

As shown in FIGS. 1 and 2, in the method of manufacturing the semiconductor device 100 in the present embodiment, after forming a MOS transistor in a MOS transistor forming region M which is an active region, resistance is made to a resistance element forming region R which is a field region. It includes an etching stopper film forming step, an interlayer insulating film forming step, a trench forming step, and a resistance element forming step for forming the element 23.
The semiconductor device 100 in the present embodiment includes a wafer-shaped first conductive semiconductor substrate 1, a first conductive diffusion region 2, a field insulating film 3, a gate insulating film 4, a gate electrode 5, and a second conductive film. The mold source region 6, the second conductive type drain region 7, the first interlayer insulating film 11, the first metal wiring 12, the wiring metal layers 13 and 16, and the second interlayer insulating film 14 (interlayer insulation). It has a film), a second metal wiring 15, a contact hole 17, an etching stopper film 21, a trench 22, and a resistance element 23.

As a method for manufacturing the semiconductor device 100 in the present embodiment, first, as shown in FIG. 3, a first conductive diffusion region 2 is formed on the first conductive semiconductor substrate 1. The first conductive type diffusion region 2 is formed by injecting phosphorus as a first conductive type impurity into the first conductive type semiconductor substrate 1.
In the present embodiment, the first conductive type impurity is phosphorus, but the present invention is not limited to this. Further, in the present embodiment, the first conductive type is N type and the second conductive type described later is P type, but the present invention is not limited to this, the first conductive type is P type and the second conductive type is N type. It may be a mold.

Next, an element separation structure by STI (Shallow Trench Isolation) is provided on a part of the upper surface of the first conductive diffusion region 2 other than the MOS transistor formation region M. In the present embodiment, the field insulating film 3 of STI is a silicon oxide film formed by CVD (Chemical Vapor Deposition).
In the present embodiment, the element separation structure by STI is provided, but the present invention is not limited to this, and for example, an element separation structure by LOCOS (LOCal Oxidation of Silicon) may be provided. Further, in the present embodiment, the field insulating film 3 is a silicon oxide film formed by CVD, but the present invention is not limited to this.

Next, a gate insulating film 4 which is a silicon oxide film is formed in the central portion of the upper surface of the first conductive diffusion region 2 in the MOS transistor forming region M, and then a polycrystalline silicon film is formed on the gate insulating film 4. The gate electrode 5 is formed.
In the present embodiment, the gate insulating film 4 is a silicon oxide film and the gate electrode 5 is a polycrystalline silicon film, but the present invention is not limited to this.

Next, on the upper surface of the first conductive diffusion region 2, boron is injected between one end of the gate insulating film 4 and the field insulating film 3 facing the one end to form the second conductive source region 6. To do. Further, together with the formation of the second conductive type source region 6, boron is also injected between the other end of the gate insulating film 4 and the field insulating film 3 facing the other end to inject the boron into the second conductive type drain. Region 7 is formed.
In the present embodiment, the second conductive type impurity is boron, but the present invention is not limited to this, and may be, for example, BF ₂ .
As described above, the MOS transistor is formed in the MOS transistor forming region M.

Next, as shown in FIG. 4, BPSG (Boro-Phospho Silicate Glass) covers the upper surfaces of the field insulating film 3, the gate electrode 5, the second conductive source region 6, and the second conductive drain region 7, respectively. ) The first interlayer insulating film 11 which is a film is formed.
In the present embodiment, the first interlayer insulating film 11 is a BPSG film, but the present invention is not limited to this, for example, a laminated structure of an NSG (None-doped Silicate Glass) film and a BPSG film, a TEOS (Tetraethoxysilane) film. And a laminated structure of BPSG film may be used. Further, when an etching stopper film is formed on the lower surface of the first interlayer insulating film 11 in order to form a trench in the first interlayer insulating film 11, the first interlayer insulating film 11 is the etching stopper film. An insulating film that can be easily removed by etching is preferable.

Next, as shown in FIG. 5, from the upper surface of the first interlayer insulating film 11 flattened by CMP (Chemical Mechanical Polishing), the gate electrode 5, the second conductive source region 6, and the second conductive drain Each contact hole is provided by dry etching so as to penetrate to the upper surface of the region 7. Then, the wiring metal layer 13 is formed on the upper surface of the first metal wiring 12 formed by embedding the inside of each contact hole with tungsten.
In the present embodiment, the upper surface of the first interlayer insulating film 11 is flattened by CMP, but the present invention is not limited to this. Further, in the present embodiment, the material of the first metal wiring 12 is tungsten, but the material is not limited to this.

<Etching stopper film forming process and etching stopper film>
In the etching stopper film forming step, as shown in FIG. 6, the etching stopper film 21 is formed on the upper surface of the first interlayer insulating film 11 above the field insulating film 3 in the resistance element forming region R.
The etching stopper film 21 is a silicon nitride film, and has a lower etching rate in dry etching than the second interlayer insulating film 14 which is a silicon oxide film. Therefore, the etching stopper film 21 serves as an etching stopper that keeps the depth of the trench 22 constant when the trench 22 is formed on the second interlayer insulating film 14 by dry etching in the trench forming step described in detail later. Function.
That is, the etching stopper film forming step is a step of forming the etching stopper film 21 which is more difficult to remove by the etching process than the second interlayer insulating film 14.

The shape of the etching stopper film 21 in a plan view is not particularly limited as long as it includes the entire range in which the trench 22 is formed, and can be appropriately selected depending on the intended purpose.
The plan view shape means a shape when the semiconductor device 100 formed on the wafer-shaped first conductive semiconductor substrate 1 is viewed in a plan view. Further, the plan view means that the upper surface side of the first conductive semiconductor substrate 1 is viewed from above the first conductive semiconductor substrate 1 (in the normal direction of the first conductive semiconductor substrate 1).

The film thickness of the etching stopper film 21 is not particularly limited as long as the depth of the trench 22 can be made constant by the etching process in the trench forming step, and can be appropriately selected depending on the intended purpose.

The material of the etching stopper film 21 is not particularly limited as long as it is more difficult to remove by the etching process than the second interlayer insulating film 14 described in detail later and has insulating properties, and is appropriately selected according to the purpose. can do. For example, if the second interlayer insulating film 14 is a silicon oxide film as in the present embodiment, the etching stopper film 21 may be a silicon nitride film having a lower etching rate than the silicon oxide film, which is more difficult to remove by the etching process. ..

The etching treatment is not particularly limited as long as the etching stopper film 21 has a lower etching rate than the second interlayer insulating film 14, and can be appropriately selected depending on the intended purpose. For example, as the etching process, dry etching is preferable as in the present embodiment because the trench 22 can be stably formed without causing undercutting.

<Interlayer insulating film forming process and interlayer insulating film>
As shown in FIG. 7, the interlayer insulating film forming step is a step of forming a second interlayer insulating film 14 which is a silicon oxide film so as to cover the entire first interlayer insulating film 11 and the etching stopper film 21. is there.

The shape, structure, and size of the second interlayer insulating film 14 are particularly limited as long as they are formed so as to cover the etching stopper film 21 so that the trench 22 having the etching stopper film 21 as the bottom surface can be formed. However, it can be appropriately selected according to the purpose.

The film thickness of the second interlayer insulating film 14 is not particularly limited and may be appropriately selected depending on the intended purpose. However, the resistance element 23 formed in the second interlayer insulating film 14 according to this film thickness. Since the cross-sectional area changes, it is preferable to set the film thickness according to the target resistance value.

The material of the second interlayer insulating film 14 is not particularly limited as long as it is easier to remove by the etching process than the etching stopper film 21, and can be appropriately selected depending on the intended purpose. For example, if the etching stopper film 21 is a silicon nitride film as in the present embodiment, the second interlayer insulating film 14 may be a silicon oxide film having a higher etching rate than the silicon nitride film.

Next, as with the first interlayer insulating film 11, the upper surface of the second interlayer insulating film 14 is flattened by CMP.
In the present embodiment, the upper surface of the second interlayer insulating film 14 is flattened by CMP, but the present invention is not limited to this.

<Trench formation process and trench>
As shown in FIG. 8, the trench forming step is a step of forming the trench 22 by the etching process from the upper surface of the second interlayer insulating film 14 to the depth reaching the etching stopper film 21.
Since the variation in the depth of the trench 22 formed by the etching process is often larger than the variation in the film thickness, in the present embodiment, the etching stopper film 21 is formed at a position on the bottom surface of the trench 22. As a result, in the trench forming step of the present embodiment, the etching amount is substantially constant by forming the trench 22 by the etching process from the upper surface of the second interlayer insulating film 14 to the depth reaching the etching stopper film 21. Therefore, the accuracy of the depth of the trench 22 can be improved.

The plan view shape of the trench 22, that is, the shape of the opening of the trench 22 is not particularly limited as long as it is linear, and can be appropriately selected according to the purpose. , Curved, wound, spelled line, etc.
The line width of the linear trench 22 is preferably narrower than the depth of reaching the etching stopper film 21 from the upper surface of the second interlayer insulating film 14 from the viewpoint of reducing the layout area.

The depth of the trench 22 is not particularly limited as long as it reaches the etching stopper film 21 from the upper surface of the second interlayer insulating film 14, and can be appropriately selected depending on the intended purpose.

<Resistance element forming process and resistance element>
As shown in FIG. 9, the resistance element forming step is a step of forming the resistance element 23 in a “vertical shape” so as to follow the shape of the linear trench 22. When the resistance element 23 is formed so as to follow the shape of the trench 22 in this step, the accuracy of the depth of the trench 22 is improved by the etching stopper film 21, so that the dimensional variation of the resistance element 23 formed in the trench 22 is increased. It is possible to obtain a resistance element 23 that can be reduced and has a high accuracy of resistance value.
Further, the depth of the etching stopper film 21 from the upper surface of the second interlayer insulating film 14, that is, in the present embodiment, the cross-sectional area of the resistance element changes by changing the film thickness of the second interlayer insulating film 14. , Various resistance values can be realized with high accuracy.

The "vertical" resistance element 23 is formed of a polycrystalline silicon film so as to fill the shape of the trench 22. The polycrystalline silicon film has a low-concentration impurity region as a resistor and a high-concentration impurity region as an electrode arranged on the upper surfaces of both ends of the resistor. The low-concentration impurity region is adjusted to a desired resistance value depending on the impurity concentration and size. Further, the electrodes of the resistance element 23 are connected to a wiring metal film (not shown).

The "vertical" resistance element 23 is embedded in the trench 22 formed in the second interlayer insulating film 14 and has a resistance width in the vertical direction (normal direction) of the first conductive semiconductor substrate 1. It can be said that it is a resistance element having a film thickness and a resistance length in the horizontal direction (in-plane direction) of the first conductive semiconductor substrate 1.
Further, if the volume of the "vertical" resistance element 23 does not change as compared with the "horizontal" resistance element, the variation in the resistance value due to the crystallinity of the polycrystalline silicon is different from that of the "horizontal" resistance element. Can be equivalent.

In the present embodiment, the resistance element 23 is formed of a polycrystalline silicon film, but the present invention is not limited to this, and the resistance element 23 may be formed of, for example, a film of CrSiO, CrSiN, TiN, or the like. Further, in the present embodiment, the high-concentration impurity region is provided at both ends of the shape of the linear trench 22, but the present invention is not limited to this, and for example, regardless of the shape of the trench 22, it is easy to make contact as an electrode. Therefore, it may have a predetermined size or the like.

Next, after the resistance element forming step, as shown in FIG. 1, after the inside of the contact hole formed on each wiring metal layer 13 is embedded with tungsten to form the second metal wiring 15, the second metal wiring 15 is formed. A wiring metal layer 16 is formed on the upper surface of the metal wiring 15 of 2. Finally, a passivation film as a protective film is formed on the entire upper surface of the second interlayer insulating film 14 and the second metal wiring 15, to manufacture the semiconductor device 100 of the present embodiment.
In the present embodiment, the second metal wiring 15 is made of tungsten, but the present invention is not limited to this.

As described above, in the method of manufacturing the semiconductor device 100, the layout area of the resistance element 23 can be easily reduced by forming the resistance element 23 in a “vertical shape”. Further, in the manufacturing method of the semiconductor device 100, the accuracy of the depth of the trench 22 is improved by forming the etching stopper film 21 on the lower surface of the second interlayer insulating film 14, and the trench 22 is directly formed on the inner wall surface of the trench 22. Since the dimensional accuracy of the resistance element is improved, the accuracy of the resistance value can be increased.

[Second Embodiment]
FIG. 10 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 10, the semiconductor device 200 of the second embodiment is second to the etching stopper film 21 of the first embodiment as compared with the semiconductor device 100 of the first embodiment shown in FIG. The etching stopper film 24 of the embodiment is formed thicker.

As a result, the cross-sectional area of the resistance element 26 of the second embodiment is smaller than the cross-sectional area of the resistance element 23 of the first embodiment, so that the resistance element 26 can be made higher than the resistance element 23. it can.

[Third Embodiment]
FIG. 11 is an explanatory view showing a cross section of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
As shown in FIG. 11, in the semiconductor device 300 according to the third embodiment, the etching stopper film 27 is formed on the upper surface of the field insulating film 3. Further, the semiconductor device 300 is formed up to an etching stopper film 27 in which the trench 28 penetrates from the upper surface of the second interlayer insulating film 14 and is arranged on the lower surface of the first interlayer insulating film 11.

As a result, the trench 28 of the third embodiment is formed deeper than the trench 22 of the first embodiment shown in FIG. 1, and therefore, the third embodiment is formed more deeply than the resistance element 23 of the first embodiment. The resistance element 29 can have a larger cross-sectional area, that is, a larger volume. Therefore, since the resistance element 29 of the third embodiment has a larger volume than the resistance element 23 of the first embodiment, it is possible to suppress variations in the crystallinity of the polycrystalline silicon film, and the resistance element 29 is larger than the resistance element 23. The resistance value can be made highly accurate.

[Fourth Embodiment]
For example, if the semiconductor device is a voltage detector, the voltage is detected by comparing the reference voltage generated from the reference voltage circuit and the divided voltage divided by the voltage dividing circuit with an error amplifier. The accuracy of the pressure voltage is important.
In order to improve the accuracy of the voltage dividing voltage, conventionally, a resistance circuit 510 as shown in FIG. 12 is formed, and each fuse connected in parallel to the resistance element groups 61 to 64 is selectively blown. The resistance value of the entire resistance circuit 510 from terminals C1 to C2 may be adjusted. In this case, since it is necessary that the variation of each resistance element 51 with respect to the target resistance value R is small, the relative error of the resistance value is reduced by forming with a mask having the same line width as shown in FIG. A plurality of adjacent "horizontal" resistance elements 51 are formed. Then, the wiring metal layer 52 is appropriately arranged at both ends of the resistance element 51 to form the resistance circuit 510, but there is a problem that the layout area becomes large because nine "horizontal" resistance elements 51 are required.

Therefore, in the method for manufacturing the semiconductor device 400 according to the fourth embodiment, as shown in FIG. 14, the etching stopper films 27 and 30 are attached to the lower surfaces of the first interlayer insulating film 11 and the second interlayer insulating film 14, respectively. Form. In other words, in the method for manufacturing a semiconductor device according to the fourth embodiment, in the etching stopper film forming step, two or more etching stopper films 27, 30 having different depths from the upper surface of the second interlayer insulating film 14 are formed. Then, in the trench forming step, trenches 28 and 31 are formed up to the depth with respect to the respective etching stopper films 27 and 30, respectively, and in the resistance element forming step, two or more trenches 28 and 31 are formed so as to follow the shapes of the respective trenches 28 and 31. The resistance elements 29 and 32 are formed. That is, although other trenches may be provided in addition to the trenches 28 and 31, the semiconductor device 400 is provided with a plurality of linear trenches 28 and 31 having substantially the same line width, and at least two of them are provided. The depths of the linear trenches 28 and 31 were made different. Then, resistance elements are formed so as to follow the shapes of these trenches.
As a result, in the method for manufacturing the semiconductor device 400 according to the fourth embodiment, the resistance values of the "vertical" resistance elements 29 and 32 having different resistance values can be made highly accurate.

Further, if the thickness of each interlayer insulating film is substantially the same, it becomes easy to set the resistance value of the resistance element 29 to R and the resistance value of the resistance element 32 to 2R from the cross-sectional area of each resistor. As a result, in the method of manufacturing the semiconductor device 400, two types of resistance elements having resistance values of R and 2R can be formed with high accuracy. Therefore, the conventional resistance circuit 510 shown in FIG. 12 is shown in FIG. It can be formed with only six "vertical" resistance elements, such as the resistance circuit 410. Then, the resistance element of the resistance circuit 410 of FIG. 15 has a layout as shown in FIG. 16, and the layout area of the resistance circuit can be reduced as compared with the conventional layout shown in FIG.

In the present embodiment, two resistance elements having different resistance values are formed for use in a resistance circuit, but the present invention is not limited to this, and at least one of them has a different resistance value for use in another circuit. Three or more resistance elements may be formed.

Further, as an aspect other than the above, in the trench forming step, two or more trenches may be formed for each etching stopper film. As a result, it is possible to form two or more resistance elements having high accuracy and the same resistance value.

As described above, the method for manufacturing a semiconductor device according to an embodiment of the present invention is a method for manufacturing a semiconductor device in which a resistance element is formed in an interlayer insulating film, and the interlayer insulating film is removed by an etching process. An etching stopper film forming step for forming a difficult etching stopper film, an interlayer insulating film forming step for forming an interlayer insulating film so as to cover the etching stopper film, and etching from the upper surface of the interlayer insulating film to a depth reaching the etching stopper film. The process includes a trench forming step of forming a linear trench and a resistance element forming step of forming a resistance element along the shape of the trench.
Thereby, the method for manufacturing a semiconductor device according to an embodiment of the present invention can manufacture a semiconductor device having a resistance element whose layout area can be easily reduced and whose resistance value is highly accurate.

1 1st conductive type semiconductor substrate 2 1st conductive type diffusion area 3 Field insulating film 4 Gate insulating film 5 Gate electrode 6 2nd conductive type source area 7 2nd conductive type drain area 11 1st interlayer insulating film 12 1st Metal wiring 13, 16, 52 Wiring metal layer 14 Second interlayer insulating film (interlayer insulating film)
15 Second metal wiring 17 Contact hole 21,24,27,30 Etching stopper film 22,25,28,31 Trench 23,26,29,32,51 Resistance element 61-64 Resistance element group 100,200,300, 400 Semiconductor device 410,510 Resistance circuit R Resistance element formation area M MOS transistor formation area

Claims (7)

A method for manufacturing a semiconductor device in which a resistance element is formed in an interlayer insulating film.
An etching stopper film forming step of forming an etching stopper film that is more difficult to remove by the etching process than the interlayer insulating film.
An interlayer insulating film forming step of forming the interlayer insulating film so as to cover the etching stopper film, and
A trench forming step of forming a linear trench by the etching process from the upper surface of the interlayer insulating film to a depth reaching the etching stopper film.
A resistance element forming step of forming the resistance element so as to follow the shape of the trench,
A method for manufacturing a semiconductor device, which comprises. The method for manufacturing a semiconductor device according to claim 1, wherein the line width of the linear trench is narrower than the depth of reaching the etching stopper film from the upper surface of the interlayer insulating film. In the etching stopper film forming step, two or more etching stopper films having different depths from the upper surface of the interlayer insulating film are formed.
In the trench forming step, each of the trenches is formed to a depth with respect to each of the etching stopper films.
The method for manufacturing a semiconductor device according to claim 1 or 2, wherein in the resistance element forming step, two or more resistance elements are formed so as to follow the shape of each of the trenches. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the etching process is dry etching. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the etching stopper film is a silicon nitride film. A semiconductor device having a resistance element in the interlayer insulating film.
An etching stopper film that is more difficult to remove by etching than the interlayer insulating film,
The interlayer insulating film formed so as to cover the etching stopper film and the interlayer insulating film.
A linear trench formed from the upper surface of the interlayer insulating film to a depth reaching the etching stopper film, and
The resistance element formed along the shape of the linear trench and
A semiconductor device characterized by having. It has a plurality of the linear trenches having substantially the same line width, and has a plurality of the linear trenches.
The semiconductor device according to claim 6, wherein the depths of at least two of the linear trenches are different.

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