JP2022059519A - Semiconductor integrated circuit - Google Patents

Abstract

To provide a semiconductor integrated circuit including a trench separation structure, in which the characteristic variation is suppressed.SOLUTION: A semiconductor integrated circuit includes element regions formed on a semiconductor substrate including a first impurity region with predetermined polarity, a groove part for insulating and separating the element regions, the groove part including an insulating film formed along an inner wall of the groove part and a conductor formed on the insulating film, containing impurities with predetermined polarity, and filling the groove part, and a second impurity region formed in the first impurity region around the groove part and including impurities with predetermined polarity.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor integrated circuits.

Trench separation is known as an example of an element separation structure in a semiconductor integrated circuit. The element separation structure is an element separation technique for a semiconductor integrated circuit for preventing leakage current between adjacent elements and ensuring withstand voltage. Trench isolation is a technique for separating elements by arranging, for example, a groove (trench) filled with an insulator around the element in a semiconductor integrated circuit, and separates the elements from each other. STI (Shallow Trench Isolation), DTI (Deep Trench Isolation) ) Etc. are known. The trench separation technique is also used in vertical semiconductor integrated circuits such as trench gate type transistors.

As a document related to trench separation, for example, Patent Document 1 is known. In the method for manufacturing a semiconductor device disclosed in Patent Document 1, a step of providing a plurality of trenches for partitioning pillars on a semiconductor substrate and embedded silicon covering a first region where bit wires are formed at the bottom of the trenches. It has an oxide film, an embedded doped silicon film embedded inside the embedded silicon oxide film, and a silicon nitride film formed on the side surface of a second region, which is a region above the first region. The process of forming an exposed groove of the embedded silicon oxide film on a part of the side surface of the first region and the process of forming a non-doped silicon film on the inner surface of the groove and performing heat treatment on the upper surface of the embedded doped silicon film. It includes a step of forming a new embedded doped silicon film. Patent Document 1 states that a further miniaturized high-density semiconductor device can be manufactured according to the method for manufacturing a semiconductor device having the above configuration.

Further, a method for separating elements of a semiconductor device disclosed in Patent Document 2 is also known. In the element separation method of the semiconductor device disclosed in Patent Document 2, an N-type epitaxial layer is formed on a P-type semiconductor substrate, an oxide film and a nitride film are sequentially formed on the upper surface thereof, and then a trench layer is formed by etching. Then, after forming a sidewall made of an oxide film on the inner wall surface of the trench layer, a doped CVD film such as a BSG film containing boron is embedded. In Patent Document 2, according to such a method for separating elements of a semiconductor device, the sidewall in the trench layer prevents the boron from diffusing in the lateral direction and enables bonding with a semiconductor substrate. It is said that a good separation area can be obtained.

Further, a method for manufacturing a semiconductor device disclosed in Patent Document 3 is also known. In the method for manufacturing a semiconductor device disclosed in Patent Document 3, silicon in which an insulating film, a polysilicon thin film, boron, phosphorus and other additives are doped on the entire surface and parallel to the surface of a semiconductor substrate having a predetermined trench formed therein. The oxide film is sequentially formed, and then subjected to heat treatment to fill the recesses in the trench by the growth of the doped silicon oxide film, and the additives in the doped silicon oxide film are diffused into the polysilicon thin film, and finally the trench. A capacitor electrode is formed by etching a doped silicon oxide film other than the portion. In Patent Document 3, according to such a method for manufacturing a semiconductor device, it is possible to suppress the formation of a portion where polysilicon is not deposited inside the trench portion when the trench is embedded, and it does not depend on the variation in the shape of the trench. It is said that trenches can be embedded.

Further, the semiconductor device disclosed in Patent Document 4 is also known. In the semiconductor device disclosed in Patent Document 4, a laminated film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially laminated is formed on a side wall of a trench formed on one surface of a semiconductor substrate. It is a semiconductor device having a trench gate structure in which silicon doped with boron is embedded in a trench through a laminated film, and the silicon nitride film in the laminated film can suppress the passage of boron. It is a film thickness and a film quality, and is characterized in that the film thickness of the first silicon oxide film in the trench in the laminated film is larger than the film thickness of the second silicon oxide film on the polysilicon side. According to Patent Document 4, according to such a semiconductor device, in a semiconductor device having a trench gate structure in which boron-doped polysilicon is embedded in a trench, the withstand voltage of the insulating film formed on the side wall of the trench is lowered. It is said that it can suppress.

Japanese Unexamined Patent Publication No. 2012-004230 Japanese Unexamined Patent Publication No. 05-129426 Japanese Unexamined Patent Publication No. 02-165663 Japanese Unexamined Patent Publication No. 2004-228342

By the way, in a semiconductor integrated circuit having a groove separation structure in which non-doped polysilicon is filled in a trench, the impurity concentration of the semiconductor substrate may decrease around the trench due to the influence of thermal oxidation in the manufacturing process. The decrease in the impurity concentration of the semiconductor substrate around the trench affects the impurity concentration of the adjacent element to be separated, and the characteristics of the element may fluctuate.

The above problem will be described more specifically with reference to FIG. FIG. 4 shows a semiconductor integrated circuit 50 according to a comparative example. The semiconductor integrated circuit 50 is an example of a diode having a trench separation structure, FIG. 4A shows a cross-sectional view, and FIG. 4B shows a plan view. As shown in FIG. 4, the semiconductor integrated circuit 50 includes a p-type semiconductor substrate 11, n + impurity region 14, p + impurity region 15, and trench portion 60. The trench portion 60 includes an oxide film 12 formed on the inner surface of the trench and non-doped polysilicon 51 filled in the trench via the oxide film 12. As the p-type semiconductor substrate 11, for example, a silicon (Si) substrate to which a p-type impurity is added is used. Note that p + means a relatively high-concentration p-type impurity region, and n + means a relatively high-concentration n-type impurity region.

In the semiconductor integrated circuit 50 shown in FIG. 4, p-type impurities in the p-type semiconductor substrate 11 may be absorbed by the oxide film 12 in the manufacturing process of the semiconductor integrated circuit 50. That is, in the manufacturing process, when the thermal oxidation treatment for forming the oxide film 12 is performed after the trench is formed, a region where the impurity concentration of the p-type semiconductor substrate 11 is reduced is formed in the portion along the side wall and the bottom of the trench. May occur. The region where the impurity concentration has decreased is surrounded by p-type impurities and behaves equivalently as an n-type region. In that sense, in the following, the region where the impurity concentration has decreased is referred to as "reversal layer 52".

When the inverted layer 52 as described above is formed, the inverted layer 52 behaves like an n-type impurity region, so that it is between the n + impurity region 14 and the inverted layer 52, and between the p + impurity region 15 and the inverted layer 52. Acts like a channel, and when a bias voltage is applied to the semiconductor integrated circuit 50, a current path IR may be formed as shown in FIG. 4A. Looking at this current path IR in a plan view, it is connected via each impurity region as shown in FIG. 4 (b). When the current path IR is formed, the characteristics of the semiconductor integrated circuit 50 may be changed such as a decrease in withstand voltage. Therefore, it is necessary to suppress the generation of the current path IR as much as possible.

In this regard, although each of the patent documents 1 to 4 discloses a structure in which a substance to which an impurity is added is filled in the trench, it is assumed that the impurity diffuses to the outside of the trench. It does not try to solve the above phenomenon.

In consideration of the above facts, an object of the present invention is to suppress fluctuations in the characteristics of a semiconductor integrated circuit having a trench-separated structure.

In the semiconductor integrated circuit according to the first embodiment of the present invention, the element region formed on the semiconductor substrate including the first impurity region having a predetermined polarity and the groove portion that insulates and separates the element region. An insulating film formed along the inner wall of the semiconductor, a groove having a conductor formed on the insulating film and to which an impurity having a predetermined polarity is added and filling the groove, and a first around the groove. It includes a second impurity region containing an impurity having a predetermined polarity formed in the impurity region.

According to the semiconductor integrated circuit according to the first embodiment, the second impurity region compensates for the decrease in the impurity concentration of the first impurity region generated around the groove in the formation of the groove, and suppresses the formation of the inverted layer. do. Therefore, fluctuations in the characteristics of the semiconductor integrated circuit are suppressed.

In the semiconductor integrated circuit according to the second embodiment of the present invention, the first impurity region is a region to which an impurity having a predetermined polarity is added to the semiconductor substrate, and the element region is a p-type impurity region and an n-type impurity region. The groove is formed by surrounding the p-type impurity region and the n-type impurity region, and functions as a diode.

According to the semiconductor integrated circuit according to the second embodiment, the p-type impurity region and the n-type impurity region form a diode, and a groove portion surrounds the diode. Then, the second impurity region compensates for the decrease in the impurity concentration of the first impurity region generated around the groove portion in the formation of the groove portion, and suppresses the formation of the inverted layer. Therefore, fluctuations in characteristics such as a decrease in withstand voltage of the diode are suppressed.

In the semiconductor integrated circuit according to the third embodiment of the present invention, the first impurity region is an epitaxial layer having a predetermined polarity formed on the semiconductor substrate, and the element region corresponds to two source impurity regions. The groove is arranged between the two source impurity regions and corresponds to a gate, further includes a drain electrode formed on the back surface of the semiconductor substrate, and functions as a vertical trench gate transistor.

According to the semiconductor integrated circuit according to the third embodiment, the source impurity region, the groove portion, and the drain electrode form a vertical trench gate transistor, and the groove portion is arranged between the two source impurity regions. Then, the second impurity region compensates for the decrease in the impurity concentration of the epitaxial layer generated around the groove in the formation of the groove, and suppresses the formation of the inversion layer. Therefore, fluctuations in characteristics such as fluctuations in the threshold voltage in the vertical trench gate transistor are suppressed.

In the semiconductor integrated circuit according to the fourth embodiment of the present invention, the first impurity region is a region to which an impurity having a predetermined polarity is added to the semiconductor substrate, and the element region is a region in which at least two transistors are formed. The groove is arranged between the two transistors and has a function of separating the two transistors.

According to the semiconductor integrated circuit according to the fourth embodiment, the semiconductor integrated circuit includes two independent transistors, and a groove arranged between the two transistors has a function of separating the two transistors. Then, the second impurity region compensates for the decrease in the impurity concentration of the first impurity region generated around the groove portion in the formation of the groove portion, and suppresses the formation of the inverted layer. Therefore, the characteristic fluctuation caused by the conduction between the transistors in the semiconductor integrated circuit is suppressed.

In the semiconductor integrated circuit according to the fifth embodiment of the present invention, the conductor is polysilicon to which an impurity having the predetermined polarity is added.

According to the semiconductor integrated circuit according to the fifth embodiment, since the conductor is formed of polysilicon to which an impurity having a predetermined polarity is added, it is suitable for applying a voltage to the groove portion.

According to the present invention, in a semiconductor integrated circuit having a trench separation structure, it is possible to suppress fluctuations in the characteristics of the semiconductor integrated circuit, which is an excellent effect.

An example of the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention is shown, (a) is a cross-sectional view, and (b) is a plan view. (A) is a cross-sectional view showing an example of the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention, and (b) is for explaining the problem of the semiconductor integrated circuit according to the second embodiment. It is a figure. (A) is a cross-sectional view showing an example of the configuration of the semiconductor integrated circuit according to the third embodiment of the present invention, and (b) is for explaining the problem of the semiconductor integrated circuit according to the third embodiment. It is a figure. A configuration of a semiconductor integrated circuit according to a comparative example is shown, (a) is a cross-sectional view, and (b) is a plan view.

Hereinafter, the semiconductor integrated circuit according to the embodiment of the present invention will be described with reference to the drawings.
In each drawing, the same or equivalent components and parts are given the same reference numerals, and duplicate description will be omitted as appropriate.

[First Embodiment]
The semiconductor integrated circuit 10 according to the present embodiment will be described with reference to FIG. The semiconductor integrated circuit 10 is a form in which the semiconductor integrated circuit according to the present invention is applied to a diode. As shown in FIG. 1, the semiconductor integrated circuit 10 includes a p-type semiconductor substrate 11 to which a p-type impurity is added as a “first impurity region”, an n + impurity region 14 as an “n-type impurity region”, and “p. It is provided with a p + impurity region 15 as a "type impurity region" and a trench portion 20 as a "groove portion".
The n + impurity region constitutes the cathode region, and the p + impurity region constitutes the anode region. The trench portion 20 contains an oxide film 12 as an "insulating film" formed on the inner surface (side wall portion, bottom portion) of the trench, and boron-doped polysilicon 13 filled in the trench via the oxide film 12. As the p-type semiconductor substrate 11, for example, a silicon substrate to which a p-type impurity is added is used. The "n + impurity region" and "p + impurity region" are examples of the "element region" according to the present invention, and the "boron-doped polysilicon" is an example of the "conductor" according to the present invention.

As described above, in a semiconductor integrated circuit having a groove separation structure in which a trench is filled with non-doped polysilicon, the impurity concentration of the semiconductor substrate may decrease around the trench due to the influence of thermal oxidation in the manufacturing process. The decrease in the impurity concentration of the semiconductor substrate around this trench affects the impurity concentration of the adjacent element to be separated, or causes an interaction with the impurity concentration of the element to be separated, and the characteristics of the semiconductor integrated circuit are improved. It may fluctuate.

Therefore, in the present embodiment, the trench filling material is polysilicon to which an impurity having the same polarity as that of the p-type semiconductor substrate 11 is added. That is, in the semiconductor integrated circuit 10, the filling material inside the trench portion 20 is boron-doped polysilicon 13. Since the p-type semiconductor substrate 11 contains p-type impurities (for example, boron), the filling material of the trench portion 20 is polysilicon doped with boron, which is a p-type impurity. The p-type impurities added to the polysilicon may be the same impurities as the p-type semiconductor substrate 11, or may be different impurities. The amount of boron to be added may be small, but the amount of boron that can suppress the formation of the inverted layer 52 may be determined in advance by experiments or simulations.

When heat treatment is performed after the formation of the trench filled with boron-doped polysilicon 13, boron diffuses into the p-type semiconductor substrate 11 in the vicinity of the peripheral portion (side wall portion, bottom portion) of the trench portion 20 via the oxide film 12. That is, the semiconductor integrated circuit 10 includes an impurity region (not shown) of boron as a "second impurity region" formed along the periphery of the trench portion 20.
The impurity region has an effect of suppressing the formation of the above-mentioned channel. As a result, the decrease in the impurity concentration of the p-type semiconductor substrate 11 is suppressed, that is, the formation of the inversion layer 52 is suppressed, so that the characteristics of the semiconductor integrated circuit 10 (that is, the diode) change, for example, the withstand voltage decreases. It is suppressed.

The trench portion 20 in the semiconductor integrated circuit 10 is manufactured through the following manufacturing steps as an example.
(Step 1): A trench (opening) is formed in the p-type semiconductor substrate 11 by, for example, etching.
(Step 2): Thermal oxidation treatment is performed to form an oxide film 12 (for example, silicon oxide film (SiO ₂ )) on the inner wall including the side wall portion and the bottom portion of the trench.
(Step 3): Boron-doped polysilicon is formed on the surface of the p-type semiconductor substrate 11. At this time, boron-doped polysilicon is embedded inside the trench via the oxide film 12.
(Step 4): Boron-doped polysilicon is ground and flattened by CMP (Chemical Mechanical Polishing) or the like. By the above steps, the trench portion 20 containing the boron-doped polysilicon 13 is formed.

After (step 4), when heat treatment for forming, for example, an anode region (p + impurity region 15) and a cathode region (n + impurity region 14) is performed, boron in the trench portion 20 is deposited in the p-type semiconductor substrate 11. Spread. Therefore, in step 2, even if the impurity concentration of the p-type semiconductor substrate 11 around the trench is lowered by the above-mentioned action, the boron in the boron-doped polysilicon 13 is around the trench 20 by the heat treatment after (step 4). Since it diffuses toward and compensates for this decrease in the impurity concentration, the formation of the inverted layer 52 is suppressed.

As described in detail above, according to the semiconductor integrated circuit 10 according to the present embodiment, it is possible to suppress the characteristic fluctuation of the semiconductor integrated circuit in the semiconductor integrated circuit having the trench separation structure.

[Second Embodiment]
The semiconductor integrated circuit 70 according to the present embodiment will be described with reference to FIG. 2A. The semiconductor integrated circuit 70 is a form in which the present invention is applied to a vertical trench gate MOS (Metal Oxide Semiconductor) transistor (hereinafter, may be referred to as “trench MOS”). The semiconductor integrated circuit 70 includes an n-type semiconductor substrate 54, an n + impurity region 53 as an “element region”, a p-type epi (epitaxial) layer 55 as a “first impurity region”, and an electrode 56 as a “drain electrode”. And a trench portion 60A as a "groove portion" is included. The trench portion 60A includes a boron-doped polysilicon 61 filled in the trench via an oxide film 12 as an “insulating film” formed on the inner wall (side wall portion and bottom portion) of the trench. In the semiconductor integrated circuit 70, the n + impurity region 53 has a source function, the electrode 56 has a drain electrode function, the oxide film 12 has a gate oxide film function, and the boron-doped polysilicon 61 has a gate electrode function. As described above, the p-type impurities added to the polysilicon in the trench portion 60A are not limited to boron.

Even in the trench MOS having the above configuration, the formation of the inversion layer 52 described in the above embodiment may occur. The formation of the inversion layer 52 in the trench MOS will be described with reference to FIG. 2 (b). FIG. 2B shows a semiconductor integrated circuit 71 provided with non-doped polysilicon 62 instead of boron-doped polysilicon 61. In the semiconductor integrated circuit 71, the p-type impurities in the p-type epi layer 55 may be absorbed by the oxide film 12 in the manufacturing process of the semiconductor integrated circuit 71. That is, in the manufacturing process, when the thermal oxidation treatment for forming the oxide film 12 is performed after the trench is formed, the region along the peripheral portion of the trench where the impurity concentration of the p-type epi layer 55 is reduced, that is, the inverted layer 52 may be formed. When the inversion layer 52 is formed, the current path IR is formed, and there is a possibility that characteristic fluctuations such as threshold voltage (Vth) fluctuations may occur.

On the other hand, the trench portion 60A of the semiconductor integrated circuit 70 is also manufactured by the same process as in (Step 1) to (Step 4) described above. That is, boron in the boron-doped polysilicon 61 is diffused into the p-type epi layer 55 via the oxide film 12, and the region corresponding to the inversion layer 52 is the impurity region of boron as the “second impurity region” (not shown). (Omitted) is formed, so that the inverted layer 52 is less likely to be formed for the same reason as described above, and the characteristic fluctuation of the semiconductor integrated circuit 70 is suppressed.

[Third Embodiment]
The semiconductor integrated circuit 80 according to the present embodiment will be described with reference to FIG. 3A. The semiconductor integrated circuit 80 is a form in which the present invention is applied to separation between elements. The semiconductor integrated circuit 80 includes a p-type semiconductor substrate 11 to which a p-type impurity is added as a "first impurity region", MOS transistors 65A and 65B as an "element region", and a trench portion 60B as a "groove portion". I'm out. Each of the MOS transistors 65A and 65B includes an n + impurity region 57, a gate oxide film 59, and a gate electrode 58. The n + impurity region 57 is a source / drain region. The trench portion 60B includes a boron-doped polysilicon 63 filled in the trench via an oxide film 12 as an “insulating film” formed on the inner wall (side wall portion and bottom portion) of the trench. In the semiconductor integrated circuit 80, the trench portion 60B has a function of insulatingly separating the MOS transistor 65A and the MOS transistor 65B. As described above, the p-type impurities added to the polysilicon in the trench portion 60B are not limited to boron. Note that the MOS transistors 65A and 65B are examples, and may be other circuit elements such as bipolar transistors as long as they are subject to insulation separation by the trench portion 60B.

Even in the inter-element separation structure having the above configuration, the formation of the inversion layer 52 described in the above embodiment may occur. The formation of the inversion layer in the inter-element separation structure will be described with reference to FIG. 3 (b). FIG. 3B shows a semiconductor integrated circuit 81 provided with non-doped polysilicon 64 instead of boron-doped polysilicon 63. In the semiconductor integrated circuit 81, the p-type impurities in the p-type semiconductor substrate 11 may be absorbed by the oxide film 12 in the manufacturing process of the semiconductor integrated circuit 81. That is, in the manufacturing process, when the thermal oxidation treatment for forming the oxide film 12 is performed after the trench is formed, the region along the peripheral portion of the trench where the impurity concentration of the p-type semiconductor substrate 11 is reduced, that is, the inverted layer 52 may be formed. When the inversion layer 52 is formed, a current path IR is formed, and there is a possibility that the MOS transistor 65A and the MOS transistor 65B will be conductive. When the MOS transistor 65A and the MOS transistor 65B are electrically connected, the characteristics of both MOS transistors are changed.

On the other hand, the trench portion 60B of the semiconductor integrated circuit 80 is also manufactured by the same process as in (Step 1) to (Step 4) described above. That is, boron in the boron-doped polysilicon 63 is diffused into the p-type semiconductor substrate 11 via the oxide film 12, and the region corresponding to the inverted layer 52 is the impurity region of boron as the “second impurity region” (not shown). ) Is formed, so that the inversion layer 52 is less likely to be formed for the same reason as described above, and characteristic fluctuations due to conduction between the transistors in the semiconductor integrated circuit 80 are suppressed.

In each of the above embodiments, a form in which polysilicon is used as a material to be filled in the trench portion has been described as an example, but the present invention is not limited to this, and for example, silicon formed by using CVD (Chemical Vapor Deposition) or the like is used. It may be an oxide film such as an oxide film.

Further, in each of the above embodiments, the embodiment in which the present invention is applied to a diode, a trench MOS, and separation between elements has been described as an example, but the present invention is not limited to this, and various other embodiments such as an IGBT (Insulated Gate Bipolar Transistor) are used. It can be applied to semiconductor integrated circuits. The present invention can also be applied to trenches of various depths, corresponding to its applicability to various semiconductor integrated circuits. INDUSTRIAL APPLICABILITY The present invention can be particularly suitably used for a semiconductor integrated circuit using a relatively deep trench such as a trench MOS.

Further, the polarities (p-type, n-type) of the impurities exemplified in each of the above embodiments are examples and can be replaced. In that case, "p-type" may be read as "n-type" and "n-type" may be read as "p-type" in the above description.

10, 50, 70, 71, 80, 81 ... semiconductor integrated circuit, 11 ... p-type semiconductor substrate, 12 ... oxide film, 13 ... boron-doped polysilicon, 14 ... n + impurity region , 15 ... p + impurity region, 20 ... trench, 51 ... non-doped polysilicon, 52 ... inverted layer, 53 ... n + impurity region, 54 ... n-type semiconductor substrate, 55. .. p-type epi layer, 56 ... electrode, 57 ... n + impurity region, 58 ... gate electrode, 59 ... gate oxide film, 60, 60A, 60B ... trench part, 61 ... -Boron-doped polysilicon, 62 ... non-doped polysilicon, 63 ... boron-doped polysilicon, 64 ... non-doped polysilicon, 65A, 65B ... MOS transistor, IR ... current path

Claims (5)

An element region formed on a semiconductor substrate including a first impurity region having a predetermined polarity, a groove portion for insulatingly separating the element region, an insulating film formed along the inner wall of the groove portion, and an insulating film. A groove portion formed on the insulating film and provided with a conductor to which an impurity having a predetermined polarity is added and which fills the groove portion, and a groove portion.
A second impurity region containing impurities having a predetermined polarity formed in the first impurity region around the groove portion, and a second impurity region.
Semiconductor integrated circuits including. The first impurity region is a region to which impurities having the predetermined polarity are added to the semiconductor substrate.
The device region includes a p-type impurity region and an n-type impurity region.
The groove is formed by surrounding the p-type impurity region and the n-type impurity region.
The semiconductor integrated circuit according to claim 1, which functions as a diode. The first impurity region is an epitaxial layer having a predetermined polarity formed on the semiconductor substrate.
The element region is two source impurity regions corresponding to the source.
The groove is arranged between the two source impurity regions and corresponds to a gate.
Further including a drain electrode formed on the back surface of the semiconductor substrate,
The semiconductor integrated circuit according to claim 1, which functions as a vertical trench gate transistor. The first impurity region is a region to which impurities having the predetermined polarity are added to the semiconductor substrate.
The element region is a region in which at least two transistors are formed.
The semiconductor integrated circuit according to claim 1, wherein the groove portion is arranged between the two transistors and has a function of separating the two transistors. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the conductor is polysilicon to which an impurity having a predetermined polarity is added.

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