JP6565973B2 - 実装用部品、それを用いた半導体装置及びその製造方法 - Google Patents
実装用部品、それを用いた半導体装置及びその製造方法 Download PDFInfo
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- JP6565973B2 JP6565973B2 JP2017127296A JP2017127296A JP6565973B2 JP 6565973 B2 JP6565973 B2 JP 6565973B2 JP 2017127296 A JP2017127296 A JP 2017127296A JP 2017127296 A JP2017127296 A JP 2017127296A JP 6565973 B2 JP6565973 B2 JP 6565973B2
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Description
第1主面及び第2主面を有する本体部と、前記第1主面に設けられた金属層と、を備え、前記金属層には、前記金属層の主面に対して傾斜した傾斜面を有する凹状の認識マークが設けられている、実装用部品。
上述の実装用部品と、前記実装用部品に実装された半導体素子と、を備える半導体装置。
上述の実装用部品を準備し、前記認識マークを用いて半導体素子の実装位置を決定し、前記実装用部品の前記実装位置に前記半導体素子を固定する、半導体装置の製造方法。
本体部11は第1主面11aと第2主面11bを有している。第1主面11a側が半導体素子20を実装する側である。本体部11には、実装する半導体素子20の熱を効率的に外部に放出できるよう、熱伝導性の高い部材が用いられることが好ましい。具体的には、AlN、CuW、ダイヤモンド、SiC、セラミックスなどを実装用部品10として用いることが好ましい。また、本体部11には、後述するパッケージ本体30よりも半導体素子20との熱膨張係数差が小さい部材を用いることが好ましい。これにより、熱膨張係数差による半導体素子20の実装用部品10からの剥離の可能性を低減することができる。
金属層12は、第1主面11aに設けられている。平面視において、実装用部品10のうち金属層12が設けられた領域の少なくとも一部を、半導体素子20が実装される実装領域とすることができる。なお、本明細書において平面視とは、第1主面11aに対して垂直な方向から観察することを指す。金属層12の膜厚としては、10μm以上が挙げられ、30μm以上とすることが好ましい。これにより金属層12に認識マーク12Bを形成しやすい。また、金属層12の膜厚が増大するほど製造コストも増大するため、金属層12の膜厚は100μm以下が好ましい。
金属層12には、凹状の認識マーク12Bが設けられている。図1B及び1Cに示すように、認識マーク12Bは逆錐形状の凹部とすることが好ましい。もし認識マーク12Bが錐台形状などの底面がある形状であれば、傾斜面の平面視形状はリング状などの底面を囲む線状の形状になる。この場合、検出対象はその線状の形状であるが、その幅は傾斜面の傾きや凹部の深さによって変化し得る。一方、逆錐形状であれば、凹部全体が傾斜面であるため、錐台形状の場合と比較して、傾斜面の平面視形状が傾斜面の傾き等に影響されにくい。これにより、実際に形成した認識マーク12Bを予め登録した認識マーク12Bの画像との比較により検出する際に、より確実に検出することができる。
図1Dに示すように、金属層12は、本体部11側から順に、凹部121Aが設けられた単層の第1金属層121と、第1金属層121よりも膜厚が薄い単層又は複層の第2金属層122と、を有することができる。この場合、認識マーク12Bは、凹部121Aが第2金属層122によって被覆されることにより形成されていることが好ましい。金属層12が多層構造である場合、多層構造を形成した後に凹部を形成すると、凹部の傾斜面が平坦になりにくく、認識マーク12Bの平面視における見え方にむらが生じやすい。図1Dに示す認識マーク12Bであれば、凹部121Aが形成されているのは厚膜の第1金属層121であるので、認識マーク12Bの傾斜面に凹凸が生じにくく、平面視における見え方にむらが生じにくい。
図1A〜1Cに示すように、金属層12の表面に第1導電部材13を設けることができる。第1導電部材13は、半導体素子20を接合するための接合材料である。金属層12の表面にはさらに第2導電部材14を設けてもよい。第2導電部材14には例えば保護素子60を接合することができる。第1導電部材13及び第2導電部材14の材料としては、半導体素子20等と接合可能である導電性の部材を選択でき、例えばAuSn合金が挙げられる。第1導電部材13及び第2導電部材14は接合層だけでなくカバー層等の他の層を有していてもよく、例えばPt/AuSn/Auの積層構造とすることができる。第1導電部材13及び第2導電部材14の膜厚は、それぞれ、例えば2μm〜5μm程度が挙げられる。
図2に半導体装置100の一例を示す。半導体装置100は、パッケージ本体30とキャップ80とを有する。パッケージ本体30は例えばベース部31とヒートシンク部32とを有する。ベース部31に設けられた貫通孔にリード端子41及び42が挿入されており、これらの一方がアノードであり、他方がカソードである。ヒートシンク部32に実装用部品10が固定されている。また、実装用部品10の第1導電部材13に半導体素子20が接合され、第2導電部材14に保護素子60が接合されている。これらの部材とリード端子41及び42とは複数の金属ワイヤ70によって電気的に接続されている。キャップ80とベース部31によって囲まれた封止空間に半導体素子20と保護素子60が配置されるように、キャップ80がベース部31に溶接等によって固定される。
ベース部31には、半導体素子20で発生する熱を効率的に外部に放出できるよう、熱伝導度が比較的高い材料、例えば、20W/mK程度以上の材料を用いることが好ましい。具体的には、Cu、Al、Fe、Ni、Mo、CuW、CuMoなどの金属が挙げられ、例えばCuを用いる。ベース部31としては、円形、楕円形、矩形などの多角形又はこれらに近似する形状を主面とする板状の部材が挙げられる。例えば、3〜10mm程度の直径の円形で平板状の部材をベース部31として用いることができる。
リード端子41、42は半導体素子20を外部電源に電気的に接続するための部材である。リード端子41、42には導電性の材料を用いる。リード端子41、42は、例えば、金属からなる棒状の部材である。リード端子41、42は、例えば、ベース部31に設けられた貫通孔を貫通するように配置され、ベース部31にガラスなどで接着される。
半導体素子20は第1導電部材13に接合される。半導体素子20は、例えば発光素子であり、好ましくは半導体レーザ素子である。半導体レーザ素子は発光ダイオード(LED)よりも高い実装精度が求められるが、上述の認識マーク12Bを用いれば半導体素子20を高精度に実装することができる。また、高精度に実装可能であるので、半導体素子20は、実装用部品10に対してジャンクションダウン実装されていることが好ましい。半導体素子20として半導体レーザ素子をジャンクションダウン実装する場合には、出射するレーザ光の主要部が実装用部品10に当たらないように、平面視において半導体素子20の光出射端面を実装用部品10の端面と一致させるか、光出射端面をやや外側に突出させることが好ましい。一方で、光出射端面及びその付近の発熱を実装用部品10側に放散できるように突出量は少ないことが好ましい。認識マーク12Bを用いて半導体素子20を精度良く実装することにより、これらをバランス良く両立させることが可能である。
保護素子60は第2導電部材14に接合される。保護素子60は、半導体素子20をサージ電流による電気的破壊から保護するための部材である。保護素子60には、例えばツェナーダイオードを用いることができる。
金属ワイヤ70は金属からなる線状の部材であり、Au、Ag等の材料の直径10〜100μm程度のものを用いることができる。
図3に示すように、半導体装置100の製造方法は、実装用部品10を準備する工程S101と、認識マーク12Bを用いて半導体素子20の実装位置を決定する工程S102と、実装用部品10の実装位置に半導体素子20を固定する工程S103と、を有する。これにより、半導体素子20を実装用部品10に精度良く実装することができる。半導体素子20の実装位置を決定する工程S102において、認識マーク12Bを検出する際に用いる照明としては、例えば観察方向と同じ方向から照射する落射照明が挙げられる。また、その照明からの光は、例えば金属層12の主面12aに対して垂直な方向から照射される。また、保護素子60も半導体素子20と同様の手法で実装してよい。
11 本体部
11a 第1主面
11b 第2主面
12 金属層
12a 金属層の主面
12B 認識マーク
121 第1金属層
121A 凹部
122 第2金属層
13 第1導電部材
14 第2導電部材
15 裏面金属層
100 半導体装置
20 半導体素子
30 パッケージ本体
31 ベース部
32 ヒートシンク部
41、42 リード端子
60 保護素子
70 金属ワイヤ
80 キャップ
81 窓
Y 仮想線
Claims (12)
- 第1主面及び第2主面を有する本体部と、
前記第1主面に設けられた金属層と、を備え、
前記金属層には、前記金属層の主面に対して傾斜した傾斜面を有する凹状の認識マークが設けられており、
前記金属層は、前記本体部側から順に、凹部が設けられた単層の第1金属層と、前記第1金属層よりも膜厚が薄い単層又は複層の第2金属層と、を有し、
前記認識マークは、前記第1金属層の凹部が前記第2金属層によって被覆されることにより形成されていることを特徴とする実装用部品。 - 前記認識マークは、逆錐形状の凹部であることを特徴とする請求項1に記載の実装用部品。
- 前記第1金属層は、前記第1主面の外縁の少なくとも一部から離間して設けられていることを特徴とする請求項2に記載の実装用部品。
- 前記第1金属層が設けられた領域の少なくとも一部が実装領域であり、
前記第1金属層はCu層であることを特徴とする請求項3に記載の実装用部品。 - 前記第2金属層は、前記第1主面のうち前記第1金属層から露出した部分の全体及び前記第1金属層の全体を実質的に覆うことを特徴とする請求項3又は4に記載の実装用部品。
- 前記認識マークは、前記第1主面側から見て円形状であることを特徴とする請求項1〜5のいずれか1項に記載の実装用部品。
- 前記金属層は、複数の前記認識マークを有することを特徴とする請求項1〜6のいずれか1項に記載の実装用部品。
- 請求項1〜7のいずれか1項に記載の実装用部品と、
前記実装用部品に実装された半導体素子と、
を備える半導体装置。 - 前記半導体素子はレーザ素子であることを特徴とする請求項8に記載の半導体装置。
- 前記半導体素子は、前記実装用部品に対してジャンクションダウン実装されていることを特徴とする請求項9に記載の半導体装置。
- 請求項1〜7のいずれか1項に記載の前記実装用部品を準備し、
前記認識マークを用いて半導体素子の実装位置を決定し、
前記実装用部品の前記実装位置に前記半導体素子を固定する、半導体装置の製造方法。 - 前記実装用部品は少なくとも2つの前記認識マークを有し、
前記半導体素子の前記実装位置を決定する工程において、
前記認識マークの中心同士を結ぶ線を基準として、前記実装位置を決定することを特徴とする請求項11に記載の半導体装置の製造方法。
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