JP6557220B2 - プログラム可能なインタフェースベースの検証及びデバッグ - Google Patents

プログラム可能なインタフェースベースの検証及びデバッグ Download PDF

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JP6557220B2
JP6557220B2 JP2016518161A JP2016518161A JP6557220B2 JP 6557220 B2 JP6557220 B2 JP 6557220B2 JP 2016518161 A JP2016518161 A JP 2016518161A JP 2016518161 A JP2016518161 A JP 2016518161A JP 6557220 B2 JP6557220 B2 JP 6557220B2
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test
bus
vectors
dut
vdb
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JP2016537619A (ja
JP2016537619A5 (enExample
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ガホイ アンシュル
ガホイ アンシュル
サンタナゴパル ラグハベンドラ
サンタナゴパル ラグハベンドラ
クマール バブ プラディープ
クマール バブ プラディープ
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/20—Cathode-ray oscilloscopes
    • G01R13/22—Circuits therefor
    • G01R13/28—Circuits for simultaneous or sequential presentation of more than one variable
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)
JP2016518161A 2013-09-26 2014-09-26 プログラム可能なインタフェースベースの検証及びデバッグ Active JP6557220B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/038,743 2013-09-26
US14/038,743 US9152520B2 (en) 2013-09-26 2013-09-26 Programmable interface-based validation and debug
PCT/US2014/057579 WO2015048366A1 (en) 2013-09-26 2014-09-26 Programmable interface-based validation and debug

Publications (3)

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JP2016537619A JP2016537619A (ja) 2016-12-01
JP2016537619A5 JP2016537619A5 (enExample) 2017-11-02
JP6557220B2 true JP6557220B2 (ja) 2019-08-07

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JP2016518161A Active JP6557220B2 (ja) 2013-09-26 2014-09-26 プログラム可能なインタフェースベースの検証及びデバッグ

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Country Link
US (2) US9152520B2 (enExample)
EP (1) EP3049934A4 (enExample)
JP (1) JP6557220B2 (enExample)
CN (1) CN105474178B (enExample)
WO (1) WO2015048366A1 (enExample)

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Publication number Priority date Publication date Assignee Title
US12315585B2 (en) 2019-08-06 2025-05-27 Advantest Corporation Automated test equipment comprising a plurality of communication interfaces to a device under test

Also Published As

Publication number Publication date
US20150253387A1 (en) 2015-09-10
CN105474178A (zh) 2016-04-06
JP2016537619A (ja) 2016-12-01
US9152520B2 (en) 2015-10-06
US20150089289A1 (en) 2015-03-26
EP3049934A4 (en) 2017-04-26
CN105474178B (zh) 2019-11-26
EP3049934A1 (en) 2016-08-03
WO2015048366A1 (en) 2015-04-02

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