JPS6474474A - Pattern generating device - Google Patents

Pattern generating device

Info

Publication number
JPS6474474A
JPS6474474A JP62231698A JP23169887A JPS6474474A JP S6474474 A JPS6474474 A JP S6474474A JP 62231698 A JP62231698 A JP 62231698A JP 23169887 A JP23169887 A JP 23169887A JP S6474474 A JPS6474474 A JP S6474474A
Authority
JP
Japan
Prior art keywords
sequence generator
address information
memory
pattern memory
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62231698A
Other languages
Japanese (ja)
Inventor
Ryohei Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi High Tech Corp
Original Assignee
Hitachi Electronics Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Electronics Engineering Co Ltd filed Critical Hitachi Electronics Engineering Co Ltd
Priority to JP62231698A priority Critical patent/JPS6474474A/en
Publication of JPS6474474A publication Critical patent/JPS6474474A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To generate test patterns of two systems associatively by controlling a sequence generator which has a register and a program counter receiving data from the register selectively by an instruction memory of SQG. CONSTITUTION:A 1st sequence generator 10 generates address information for access to a 1st or 2nd pattern memory 1 or 2 according to the contents of an instruction memory 11. Further, the value of the program counter 26 is updated according to the contents of the instruction memory 11 and a 2nd sequence generator 20 generates address information on the 1st or 2nd pattern memory 1 or 2. Then a 1st selecting circuit 17 or 2nd selecting circuit 18 receives and selects the address information sent out of the 1st sequence generator 10 or address information sent out of the 2nd sequence generator 20 and sends it out to the 1st pattern memory 1st or 2nd pattern memory 2.
JP62231698A 1987-09-16 1987-09-16 Pattern generating device Pending JPS6474474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62231698A JPS6474474A (en) 1987-09-16 1987-09-16 Pattern generating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62231698A JPS6474474A (en) 1987-09-16 1987-09-16 Pattern generating device

Publications (1)

Publication Number Publication Date
JPS6474474A true JPS6474474A (en) 1989-03-20

Family

ID=16927599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231698A Pending JPS6474474A (en) 1987-09-16 1987-09-16 Pattern generating device

Country Status (1)

Country Link
JP (1) JPS6474474A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016537619A (en) * 2013-09-26 2016-12-01 日本テキサス・インスツルメンツ株式会社 Programmable interface-based verification and debugging

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016537619A (en) * 2013-09-26 2016-12-01 日本テキサス・インスツルメンツ株式会社 Programmable interface-based verification and debugging

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