FI20095884A0 - Menetelmä integroidun piirin suunnittelun verifioimiseksi verifiointiympäristössä - Google Patents
Menetelmä integroidun piirin suunnittelun verifioimiseksi verifiointiympäristössäInfo
- Publication number
- FI20095884A0 FI20095884A0 FI20095884A FI20095884A FI20095884A0 FI 20095884 A0 FI20095884 A0 FI 20095884A0 FI 20095884 A FI20095884 A FI 20095884A FI 20095884 A FI20095884 A FI 20095884A FI 20095884 A0 FI20095884 A0 FI 20095884A0
- Authority
- FI
- Finland
- Prior art keywords
- verification
- procedure
- integrated circuit
- circuit design
- environment
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20095884A FI20095884A0 (fi) | 2009-08-27 | 2009-08-27 | Menetelmä integroidun piirin suunnittelun verifioimiseksi verifiointiympäristössä |
US12/836,934 US20110055780A1 (en) | 2009-08-27 | 2010-07-15 | Method for integrated circuit design verification in a verification environment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20095884A FI20095884A0 (fi) | 2009-08-27 | 2009-08-27 | Menetelmä integroidun piirin suunnittelun verifioimiseksi verifiointiympäristössä |
Publications (1)
Publication Number | Publication Date |
---|---|
FI20095884A0 true FI20095884A0 (fi) | 2009-08-27 |
Family
ID=41050708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI20095884A FI20095884A0 (fi) | 2009-08-27 | 2009-08-27 | Menetelmä integroidun piirin suunnittelun verifioimiseksi verifiointiympäristössä |
Country Status (2)
Country | Link |
---|---|
US (1) | US20110055780A1 (fi) |
FI (1) | FI20095884A0 (fi) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9141991B2 (en) | 2008-01-31 | 2015-09-22 | Bill.Com, Inc. | Enhanced electronic data and metadata interchange system and process for electronic billing and payment system |
US10043201B2 (en) * | 2008-01-31 | 2018-08-07 | Bill.Com, Inc. | Enhanced invitation process for electronic billing and payment system |
US10769686B2 (en) | 2008-01-31 | 2020-09-08 | Bill.Com Llc | Enhanced invitation process for electronic billing and payment system |
US8095906B2 (en) | 2008-12-29 | 2012-01-10 | Altera Corporation | Method and apparatus for performing parallel routing using a multi-threaded routing procedure |
US8819789B2 (en) | 2012-03-07 | 2014-08-26 | Bill.Com, Inc. | Method and system for using social networks to verify entity affiliations and identities |
EP2720149A3 (en) * | 2012-09-07 | 2018-01-24 | Samsung Electronics Co., Ltd | Apparatus and method for generating assertion based on user program code, and apparatus and method for verifying processor using assertion |
US20150012442A1 (en) | 2013-03-14 | 2015-01-08 | Bill.Com, Inc. | Enhanced system and method for scanning and processing of payment documentation |
US10417674B2 (en) | 2013-03-14 | 2019-09-17 | Bill.Com, Llc | System and method for sharing transaction information by object tracking of inter-entity transactions and news streams |
US10115137B2 (en) | 2013-03-14 | 2018-10-30 | Bill.Com, Inc. | System and method for enhanced access and control for connecting entities and effecting payments in a commercially oriented entity network |
US10572921B2 (en) | 2013-07-03 | 2020-02-25 | Bill.Com, Llc | System and method for enhanced access and control for connecting entities and effecting payments in a commercially oriented entity network |
US9152520B2 (en) * | 2013-09-26 | 2015-10-06 | Texas Instruments Incorporated | Programmable interface-based validation and debug |
US9652978B2 (en) | 2014-04-18 | 2017-05-16 | Gentex Corporation | Trainable transceiver and mobile communications device training systems and methods |
US10268786B2 (en) * | 2017-01-04 | 2019-04-23 | Hcl Technologies Limited | System and method for capturing transaction specific stage-wise log data |
US10324815B2 (en) * | 2017-02-14 | 2019-06-18 | International Business Machines Corporation | Error checking of a multi-threaded computer processor design under test |
US10268556B2 (en) * | 2017-02-28 | 2019-04-23 | Hcl Technologies Limited | System and method for simulation results analysis and failures debug using a descriptive tracking header |
CN117725866A (zh) * | 2024-02-07 | 2024-03-19 | 北京开源芯片研究院 | 一种验证方法、装置、电子设备及可读存储介质 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5596587A (en) * | 1993-03-29 | 1997-01-21 | Teradyne, Inc. | Method and apparatus for preparing in-circuit test vectors |
US6182258B1 (en) * | 1997-06-03 | 2001-01-30 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
US20060117274A1 (en) * | 1998-08-31 | 2006-06-01 | Tseng Ping-Sheng | Behavior processor system and method |
US6553531B1 (en) * | 1999-04-22 | 2003-04-22 | Synopsys, Inc. | Method and apparatus for random stimulus generation |
US6975976B1 (en) * | 2000-03-20 | 2005-12-13 | Nec Corporation | Property specific testbench generation framework for circuit design validation by guided simulation |
US6718521B1 (en) * | 2000-08-14 | 2004-04-06 | International Business Machines Corporation | Method and system for measuring and reporting test coverage of logic designs |
US6754763B2 (en) * | 2001-07-30 | 2004-06-22 | Axis Systems, Inc. | Multi-board connection system for use in electronic design automation |
US7209851B2 (en) * | 2003-02-14 | 2007-04-24 | Advantest America R&D Center, Inc. | Method and structure to develop a test program for semiconductor integrated circuits |
US7143376B1 (en) * | 2003-03-04 | 2006-11-28 | Xilinx, Inc. | Method and apparatus for design verification with equivalency check |
US7260798B2 (en) * | 2003-12-29 | 2007-08-21 | Mentor Graphics Corporation | Compilation of remote procedure calls between a timed HDL model on a reconfigurable hardware platform and an untimed model on a sequential computing platform |
-
2009
- 2009-08-27 FI FI20095884A patent/FI20095884A0/fi not_active Application Discontinuation
-
2010
- 2010-07-15 US US12/836,934 patent/US20110055780A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20110055780A1 (en) | 2011-03-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD | Application lapsed |