JP6502635B2 - Laminated chip and method of manufacturing laminated chip - Google Patents

Description

  The present invention relates to a laminated chip in which a circuit such as a coil is formed in a magnetic body by laminating a magnetic layer and a conductive pattern by screen printing or the like, and a method of manufacturing the same.

  In recent years, electronic devices such as mobile phones and smartphones have been used in which components such as filters, capacitors, and inductors formed of laminated chips are mounted on a substrate in response to demands for downsizing and thinning.

  In a multilayer inductor, which is a type of multilayer chip, an electrically insulating magnetic layer and a conductive pattern are alternately stacked by a screen printing method or the like, and the conductive pattern is sequentially connected in the stacking direction, thereby forming a magnetic material A coil is formed so as to spiral in a spiral while overlapping in the stacking direction, and both ends of the coil are drawn out to the outer surface of the laminated chip via the respective drawing conductors.

  FIG. 3 and FIG. 4 are for explaining the manufacturing method of the above-mentioned conventional laminated inductor, and this laminated inductor is electrically conductive which forms a part of the shape of the coil by Ag paste using a printing screen etc. The pattern 1 is printed, and the pattern layer 3 on which the magnetic material 2 made of ferrite is printed is formed around the pattern 1, and these pattern layers 3 are sequentially stacked and pressure-bonded to overlap the magnetic material 2 in the above-mentioned stacking direction. The coil is manufactured by degreasing and firing it.

JP, 2008-21788, A

  By the way, in the laminated inductor obtained by the above-mentioned conventional manufacturing method, at the time of firing, as shown in FIG. 4, the crack C is generated at the connection portion of the conductive pattern 1 between the pattern layers 3 and the desired electricity In many cases, it is not possible to obtain the desired characteristics, which has been a cause of lowering the manufacturing yield.

  The present invention has been made in view of such circumstances, and can reliably prevent the occurrence of cracks in the connection portion of the conductive pattern in the stacking direction, and as a result, a product having excellent electrical characteristics can be manufactured. An object of the present invention is to provide a laminated chip which can improve the manufacturing yield and a method of manufacturing the same.

In order to solve the above-mentioned subject, in the invention according to claim 1, a plurality of pattern layers composed of conductive patterns are stacked, and the conductive patterns constituting each of the plurality of pattern layers are connected in the stacking direction. A laminated chip in which a conductive pattern is interposed, a circuit overlapping in the stacking direction is formed by the conductive pattern and the conductive pattern for connection, and an electrically insulating magnetic body is formed around the circuit , The conductive pattern for connection is not located between the magnetic members in the stacking direction, but is located between the conductive patterns and is not fixed to the magnetic member.

In the method of manufacturing a laminated chip according to the second aspect of the present invention, a pattern layer in which an electrically insulating magnetic material is printed around a conductive pattern, and a connection pattern layer in which a connection conductive pattern is formed By alternately laminating the pattern layer and the connection pattern layer in the stacking direction, thereby connecting the conductive pattern and the connection conductive pattern in the stacking direction, and for the conductive pattern and the connection. It is a manufacturing method of a lamination chip which comprises a conductive pattern and forms a circuit which overlaps in the above-mentioned lamination direction in the above-mentioned magnetic body, and the above-mentioned conductive pattern for connection is not located between the above-mentioned magnetic bodies in the above-mentioned lamination direction. It is characterized in that it is located between the conductive patterns and is not fixed to the magnetic body .

  According to the invention as set forth in claim 1 or 2, a conductive for connection for connecting conductor patterns in upper and lower pattern layers between pattern layers in which an electrically insulating magnetic material is printed around the conductive pattern. Since the connection pattern layer consisting only of patterns is interposed, the adhesion between the upper and lower conductive patterns after lamination is increased.

  As a result, since the bonding strength at the connection portion of the conductor becomes high, it is possible to suppress the generation of a crack at the time of sintering. As a result, many products with improved electrical characteristics can be manufactured, and thus the manufacturing yield can also be improved.

It is a figure for describing one Embodiment of the manufacturing method of the lamination | stacking chip which concerns on this invention. It is a longitudinal cross-sectional view which shows the laminated chip manufactured and manufactured by said one Embodiment. It is a top view which shows the conventional laminated inductor. It is a longitudinal cross-sectional view for demonstrating the manufacturing method of the laminated inductor of FIG.

Hereinafter, an embodiment of a method of manufacturing a laminated chip according to the present invention will be described based on FIGS. 1 (a) to 1 (c) and FIGS. 2 (a) and 2 (b).
In the manufacturing method of this laminated chip, first, as shown in FIG. 1A, a partial shape of a circuit such as a coil is formed as a conductive pattern 10 using Ag paste or Ni paste by screen printing or the like. The patterned layer 12 is obtained by forming an electrically insulating magnetic body 11 around the periphery using ferrite or the like.

  Next, the connection pattern layer 13 as shown in FIG. 1B is stacked on the pattern layer 12 as shown in FIG. 1C. In the connection pattern layer 13, only the connection conductive pattern 14 is formed at a position where the conductive pattern 10 of the pattern layer 12 and the conductive pattern 10 of the upper pattern layer 12 to be stacked in a later step are connected. It is.

  Then, as shown in FIGS. 2A and 2B, after the connection pattern layer 13 is laminated, the other part of the circuit such as the coil is electrically conductive in the same manner as the pattern layer 12 on the upper side thereof. The step of laminating the pattern layer 12 formed as the pattern 10 and having the magnetic body 11 formed thereon and the step of laminating the connection pattern layer 13 are sequentially repeated in the laminating direction, and the magnetic body 11 is formed. A laminated chip in which a circuit overlapping in the laminating direction is formed is manufactured.

  As a result, in the laminated chip obtained, as shown in FIG. 2B, the upper and lower conductor patterns 10 are formed between the lamination directions of the pattern layers 12 in which the magnetic material 11 is printed around the conductive patterns 10. A connection pattern layer 13 formed only of the connection conductive pattern 14 is interposed.

  In the method of manufacturing a laminated chip having the above configuration and the laminated chip manufactured thereby, as shown in FIG. 2A, a pattern layer in which an electrically insulating magnetic body 11 is printed around the conductive pattern 10 A connecting pattern layer 13 consisting of only the connecting conductive patterns 14 for connecting the conductive patterns 10 of the upper and lower pattern layers 12 is interposed between 12.

  As a result, the adhesion between the upper and lower conductive patterns after lamination is increased. Therefore, as shown in FIG. 2B, the joint strength of the connection portion of the conductors 10 and 14 after compression bonding in the lamination direction is high. As a result, since generation of cracks during sintering can be suppressed, many products having improved electrical characteristics can be manufactured, and the manufacturing yield can also be improved.

10 conductive pattern 11 magnetic body 12 pattern layer 13 connection pattern layer 14 connection conductive pattern

Claims (2)

A plurality of pattern layers composed of conductive patterns are stacked, and a conductive pattern for connection for connecting the conductive patterns constituting each of the plurality of pattern layers in the stacking direction is interposed, the conductive pattern and the conductive for connection It is a laminated chip in which a circuit overlapping in the laminating direction is formed by a pattern, and an electrically insulating magnetic material is formed around the circuit ,
The laminated chip characterized in that the conductive pattern for connection is not positioned between the magnetic members in the stacking direction but is positioned between the conductive patterns and is not fixed to the magnetic member . Alternately laminating a pattern layer on which an electrically insulating magnetic material is printed around the conductive pattern and a connection pattern layer on which the connection conductive pattern is formed;
By crimping the pattern layer and the connection pattern layer in the stacking direction, the conductive pattern and the connection conductive pattern are connected in the stacking direction,
It is a manufacturing method of a lamination chip which comprises the above-mentioned conductive pattern and the above-mentioned conductive pattern for connection, and forms a circuit which overlaps in the above-mentioned lamination direction in the above-mentioned magnetic body,
The conductive pattern for connection is not located between the magnetic members in the stacking direction but is located between the conductive patterns, and is not fixed to the magnetic member. Method.

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