JP2016051835A - Laminated chip and method of manufacturing laminated chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated chip excellent in electrical characteristics, and enhancing the manufacturing yield, by preventing occurrence of cracking in the connection of a conductive pattern reliably in the lamination direction, and to provide a method of manufacturing the same.SOLUTION: In a laminated chip where a circuit superposing in the lamination direction is formed in a magnetic material 11 by sequentially laminating pattern layers 12, where an electrically insulating magnetic material 11 is printed around a conductive pattern 10, and sequentially connecting the conductive patterns 10 in the lamination direction, a connection pattern layer 13, consisting only of a connection pattern layer 14 for connecting upper and lower conductive patterns 10, is interposed between the pattern layers 12.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a laminated chip in which a circuit such as a coil is formed in a magnetic material by laminating a magnetic material layer and a conductive pattern by screen printing or the like, and a method for manufacturing the same.

  2. Description of the Related Art In recent years, electronic devices such as mobile phones and smartphones are used in which components such as filters, capacitors, inductors, and the like made of multilayer chips are mounted on a substrate in response to requests for miniaturization and thinning.

  A multilayer inductor, which is a type of multilayer chip, has an electrically insulating magnetic layer and a conductive pattern alternately stacked by screen printing or the like, and the conductive pattern is sequentially connected in the stacking direction so that A coil that circulates in a spiral shape while being superposed in the stacking direction is formed, and both ends of the coil are respectively drawn out to the outer surface of the stack chip through lead-out conduction.

  FIG. 3 and FIG. 4 are for explaining the conventional method of manufacturing a multilayer inductor. This multilayer inductor is a conductive material that forms part of the shape of a coil with Ag paste using a printing screen or the like. The pattern 1 is printed and the pattern layer 3 is printed on the periphery of which the magnetic body 2 made of ferrite is printed, and the pattern layer 3 is sequentially stacked and pressed to overlap the magnetic body 2 in the stacking direction. This is manufactured by forming a coil to be degreased, degreased and fired.

JP 2008-21788 A

  By the way, in the multilayer inductor obtained by the above-described conventional manufacturing method, at the time of firing, as shown in FIG. In many cases, some of the product characteristics cannot be obtained, resulting in a decrease in manufacturing yield.

  The present invention has been made in view of such circumstances, and can reliably prevent a crack from occurring in the connection portion of the conductive pattern in the stacking direction, and thus can produce a product having excellent electrical characteristics. It is an object of the present invention to provide a laminated chip and a method for manufacturing the same that can improve the manufacturing yield.

  In order to solve the above-mentioned problems, the invention according to claim 1 is characterized in that a pattern layer having an electrically insulating magnetic material printed around a conductive pattern is sequentially stacked and the conductive pattern is sequentially connected in the stacking direction. As a result, in the laminated chip in which the circuit overlapping in the laminating direction is formed in the magnetic body, the connection pattern layer consisting only of the connection conductive patterns for connecting the upper and lower conductor patterns between the pattern layers. Is provided.

  According to a second aspect of the present invention, there is provided a method for manufacturing a laminated chip according to the present invention, wherein the conductive pattern is formed by sequentially laminating and pressing a pattern layer having an electrically insulating magnetic material printed around the conductive pattern. A connection pattern consisting of only connection conductive patterns for connecting the upper and lower conductor patterns between the pattern layers when forming a circuit that is sequentially connected in the stack direction and overlaps in the stack direction in the magnetic body. It is characterized by laminating layers.

  According to the first or second aspect of the present invention, the connection conductive for connecting the conductor patterns in the upper and lower pattern layers between the pattern layers in which the electrically insulating magnetic material is printed around the conductive pattern. Since the connection pattern layer consisting only of the pattern is interposed, the degree of adhesion between the upper and lower conductive patterns after lamination increases.

  Thereby, since the joint strength in the connection part of the said conductor becomes high, generation | occurrence | production of the crack at the time of sintering can be suppressed. As a result, many products with improved electrical characteristics can be manufactured, and thus the manufacturing yield can be improved.

It is a figure for demonstrating one Embodiment of the manufacturing method of the laminated chip which concerns on this invention. It is a longitudinal cross-sectional view which shows the laminated chip manufactured and manufactured by the said one Embodiment. It is a top view which shows the conventional multilayer inductor. FIG. 4 is a longitudinal sectional view for explaining a method for manufacturing the multilayer inductor of FIG. 3.

Hereinafter, an embodiment of a method for manufacturing a laminated chip according to the present invention will be described based on FIGS. 1 (a) to 1 (c) and FIGS. 2 (a) and 2 (b).
In this laminated chip manufacturing method, as shown in FIG. 1A, first, a part of a circuit such as a coil is formed as a conductive pattern 10 by using Ag paste or Ni paste by screen printing or the like, A pattern layer 12 is obtained by forming an electrically insulating magnetic body 11 using ferrite or the like around the periphery.

  Next, a connection pattern layer 13 as shown in FIG. 1B is laminated on the pattern layer 12 as shown in FIG. 1C. In this connection pattern layer 13, only the connection conductive pattern 14 is formed at the position where the conductive pattern 10 of the pattern layer 12 and the conductive pattern 10 of the upper pattern layer 12 laminated in the subsequent process are connected. It is.

  Then, as shown in FIGS. 2A and 2B, after the connection pattern layer 13 is stacked, another part of the circuit such as the coil is electrically conductive on the upper side in the same manner as the pattern layer 12. The step of laminating the pattern layer 12 formed as the pattern 10 and having the magnetic body 11 formed around the pattern 10 and the step of laminating the connection pattern layer 13 are sequentially repeated and pressure-bonded in the laminating direction. A laminated chip in which a circuit that overlaps in the laminating direction is formed is manufactured.

  As a result, in the obtained laminated chip, as shown in FIG. 2B, the upper and lower conductor patterns 10 are arranged between the lamination directions of the pattern layer 12 on which the magnetic body 11 is printed around the conductive pattern 10. A connection pattern layer 13 composed only of the connection conductive pattern 14 for connecting the two is interposed.

  In the multilayer chip manufacturing method having the above configuration and the multilayer chip manufactured thereby, a pattern layer in which an electrically insulating magnetic body 11 is printed around the conductive pattern 10 as shown in FIG. 12, a connection pattern layer 13 including only the connection conductive pattern 14 for connecting the conductor patterns 10 of the upper and lower pattern layers 12 is interposed.

  As a result, the degree of adhesion between the upper and lower conductive patterns after stacking increases, and as shown in FIG. 2B, the bonding strength of the connecting portions of the conductors 10 and 14 after being pressed in the stacking direction is high. As a result, the occurrence of cracks during sintering can be suppressed, so that many products with improved electrical characteristics can be manufactured and the manufacturing yield can be improved.

DESCRIPTION OF SYMBOLS 10 Conductive pattern 11 Magnetic body 12 Pattern layer 13 Connection pattern layer 14 Connection conductive pattern

Claims (2)

A pattern layer in which an electrically insulating magnetic material is printed around the conductive pattern is sequentially stacked, and the conductive pattern is sequentially connected in the stacking direction so as to be superimposed in the stacking direction in the magnetic material. In the laminated chip on which the circuit is formed,
A laminated chip, wherein a connection pattern layer consisting only of a connection conductive pattern for connecting the upper and lower conductor patterns is interposed between the pattern layers.   By sequentially laminating and pressing a pattern layer on which an electrically insulating magnetic material is printed around the conductive pattern, the conductive pattern is sequentially connected in the laminating direction and superimposed in the laminating direction in the magnetic material. A method of manufacturing a laminated chip, comprising: laminating a connection pattern layer composed only of a connection conductive pattern for connecting the upper and lower conductor patterns between the pattern layers when forming a circuit.

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