JP6495130B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6495130B2
JP6495130B2 JP2015146891A JP2015146891A JP6495130B2 JP 6495130 B2 JP6495130 B2 JP 6495130B2 JP 2015146891 A JP2015146891 A JP 2015146891A JP 2015146891 A JP2015146891 A JP 2015146891A JP 6495130 B2 JP6495130 B2 JP 6495130B2
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Japan
Prior art keywords
semiconductor chip
pad
electrode
connection terminal
layer
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JP2015146891A
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English (en)
Japanese (ja)
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JP2017028155A5 (enExample
JP2017028155A (ja
Inventor
翔太 三木
翔太 三木
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015146891A priority Critical patent/JP6495130B2/ja
Priority to US15/190,313 priority patent/US20170025386A1/en
Publication of JP2017028155A publication Critical patent/JP2017028155A/ja
Publication of JP2017028155A5 publication Critical patent/JP2017028155A5/ja
Application granted granted Critical
Publication of JP6495130B2 publication Critical patent/JP6495130B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2015146891A 2015-07-24 2015-07-24 半導体装置及びその製造方法 Active JP6495130B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015146891A JP6495130B2 (ja) 2015-07-24 2015-07-24 半導体装置及びその製造方法
US15/190,313 US20170025386A1 (en) 2015-07-24 2016-06-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015146891A JP6495130B2 (ja) 2015-07-24 2015-07-24 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2017028155A JP2017028155A (ja) 2017-02-02
JP2017028155A5 JP2017028155A5 (enExample) 2018-04-26
JP6495130B2 true JP6495130B2 (ja) 2019-04-03

Family

ID=57836698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015146891A Active JP6495130B2 (ja) 2015-07-24 2015-07-24 半導体装置及びその製造方法

Country Status (2)

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US (1) US20170025386A1 (enExample)
JP (1) JP6495130B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10290609B2 (en) * 2016-10-13 2019-05-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same
US10368448B2 (en) 2017-11-11 2019-07-30 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method of manufacturing a component carrier
CN109962063B (zh) * 2017-12-26 2023-04-07 深迪半导体(绍兴)有限公司 一种多芯片封装结构及工艺
KR102751333B1 (ko) * 2020-06-01 2025-01-07 삼성전자주식회사 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000138313A (ja) * 1998-10-30 2000-05-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4838068B2 (ja) * 2005-09-01 2011-12-14 日本特殊陶業株式会社 配線基板
JP2009239256A (ja) * 2008-03-03 2009-10-15 Panasonic Corp 半導体装置及びその製造方法
KR20100020718A (ko) * 2008-08-13 2010-02-23 삼성전자주식회사 반도체 칩, 그 스택 구조 및 이들의 제조 방법
KR101767108B1 (ko) * 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
JP5385471B2 (ja) * 2011-08-10 2014-01-08 新光電気工業株式会社 半導体装置の製造方法
JP5357241B2 (ja) * 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9331021B2 (en) * 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same

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Publication number Publication date
US20170025386A1 (en) 2017-01-26
JP2017028155A (ja) 2017-02-02

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