JP6484061B2 - 電子部品パッケージの製造方法 - Google Patents

電子部品パッケージの製造方法 Download PDF

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Publication number
JP6484061B2
JP6484061B2 JP2015033463A JP2015033463A JP6484061B2 JP 6484061 B2 JP6484061 B2 JP 6484061B2 JP 2015033463 A JP2015033463 A JP 2015033463A JP 2015033463 A JP2015033463 A JP 2015033463A JP 6484061 B2 JP6484061 B2 JP 6484061B2
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JP
Japan
Prior art keywords
resin sheet
pressure
sealing resin
sealing
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015033463A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015179829A (ja
Inventor
智絵 飯野
智絵 飯野
浩介 盛田
浩介 盛田
豪士 志賀
豪士 志賀
石坂　剛
剛 石坂
剛志 土生
剛志 土生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to PCT/JP2015/055233 priority Critical patent/WO2015129689A1/ja
Priority to JP2015033463A priority patent/JP6484061B2/ja
Priority to TW104106395A priority patent/TW201541577A/zh
Publication of JP2015179829A publication Critical patent/JP2015179829A/ja
Application granted granted Critical
Publication of JP6484061B2 publication Critical patent/JP6484061B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
JP2015033463A 2014-02-26 2015-02-24 電子部品パッケージの製造方法 Active JP6484061B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2015/055233 WO2015129689A1 (ja) 2014-02-26 2015-02-24 電子部品パッケージの製造方法
JP2015033463A JP6484061B2 (ja) 2014-02-26 2015-02-24 電子部品パッケージの製造方法
TW104106395A TW201541577A (zh) 2014-02-26 2015-02-26 電子零件封裝之製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014035704 2014-02-26
JP2014035704 2014-02-26
JP2015033463A JP6484061B2 (ja) 2014-02-26 2015-02-24 電子部品パッケージの製造方法

Publications (2)

Publication Number Publication Date
JP2015179829A JP2015179829A (ja) 2015-10-08
JP6484061B2 true JP6484061B2 (ja) 2019-03-13

Family

ID=54009007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015033463A Active JP6484061B2 (ja) 2014-02-26 2015-02-24 電子部品パッケージの製造方法

Country Status (3)

Country Link
JP (1) JP6484061B2 (zh)
TW (1) TW201541577A (zh)
WO (1) WO2015129689A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3905860A1 (en) * 2020-04-28 2021-11-03 Kyocera Corporation Manufacturing method of electronic component

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6512113B2 (ja) * 2016-01-08 2019-05-15 信越化学工業株式会社 太陽電池モジュールの製造方法
CN108476589B (zh) * 2016-01-13 2021-10-26 太阳油墨制造株式会社 干膜和印刷电路板
KR20170092323A (ko) 2016-02-03 2017-08-11 삼성전자주식회사 반도체 패키지의 몰딩 장치
JP6784186B2 (ja) * 2017-02-10 2020-11-11 信越化学工業株式会社 太陽電池モジュールの製造方法
JP7027458B2 (ja) * 2017-06-06 2022-03-01 ウエスト ファーマスーティカル サービシーズ インコーポレイテッド 埋込み電子機器を有するエラストマーアーティクルおよびその製造方法
CN110769878B (zh) 2017-06-06 2023-08-11 西医药服务有限公司 具有嵌入式电子装置的弹性体制品和其制造方法
JP7028264B2 (ja) * 2018-01-30 2022-03-02 昭和電工マテリアルズ株式会社 フィルム状接着剤及びその製造方法、並びに半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5435685B2 (ja) * 2007-02-28 2014-03-05 ナミックス株式会社 封止用樹脂フィルム
WO2009001564A1 (ja) * 2007-06-28 2008-12-31 Panasonic Corporation 半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール
JP5349432B2 (ja) * 2010-09-06 2013-11-20 日東電工株式会社 電子部品装置の製法およびそれに用いる電子部品封止用樹脂組成物シート

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3905860A1 (en) * 2020-04-28 2021-11-03 Kyocera Corporation Manufacturing method of electronic component

Also Published As

Publication number Publication date
WO2015129689A1 (ja) 2015-09-03
TW201541577A (zh) 2015-11-01
JP2015179829A (ja) 2015-10-08

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