JP6480099B2 - Semiconductor test jig, measuring device, test method - Google Patents

Description

  The present invention relates to a semiconductor test jig used for testing a vertical semiconductor chip, a measurement apparatus having the semiconductor test jig, and a test method using the measurement apparatus.

  Patent Document 1 discloses a prober for measuring electrical characteristics of an IGBT device. This prober performs measurement by bringing the lower electrode of the IGBT device into contact with the conductive part of the stage and applying a probe to the conductive part and the upper electrode of the IGBT device.

JP 2007-40926 A JP 2006-292727 A JP 2008-4739 A JP 2010-276477 A

  In the technique disclosed in Patent Document 1, discharge occurs between the probe applied to the conductive portion and the IGBT device, or discharge occurs between the probe applied to the conductive portion and the probe applied to the upper surface electrode. was there.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor test jig, a measuring apparatus, and a test method that can prevent discharge.

  A semiconductor test jig according to the invention of the present application is a frame in which a base plate formed of a conductive material and a plurality of frames fixed to the base plate and formed of an insulating material are provided in a lattice shape. And a through hole for exposing the base plate is formed in the frame.

  The measuring apparatus according to the present invention includes a base plate formed of a conductive material having a notch, a hole, a concave portion, or a convex portion used as an alignment portion, and an insulating material fixed to the base plate. A frame having a plurality of formed frames arranged in a lattice pattern, the frame using a semiconductor test jig in which a through hole exposing the base plate is formed, and using the alignment portion And a measuring instrument having a stage on which the semiconductor test jig is placed in a predetermined location, a first probe, and a second probe shorter than the first probe.

  The test method according to the invention of the present application includes a base plate formed of a conductive material, a frame body fixed to the base plate, and a plurality of frames formed of an insulating material provided in a lattice shape, A step of bringing the lower surface electrode of a vertical semiconductor chip having an upper surface electrode and a lower surface electrode into contact with a portion of the base plate of the semiconductor test jig that is partitioned by the frame, and using the semiconductor test jig as a stage And a step of applying the first probe to the base plate through a through-hole formed so as to expose the base plate to the frame, and applying the second probe to the upper surface electrode. And measuring the electrical characteristics of the vertical semiconductor chip.

  According to the present invention, since the probe is passed through the through hole of the frame formed of an insulating material, discharge can be prevented.

1 is a plan view of a semiconductor test jig according to a first embodiment. It is sectional drawing in the II-II line of FIG. It is a perspective view of a stage. It is a front view of a measuring device. It is sectional drawing explaining a test method. It is sectional drawing explaining a test method. It is a top view which shows the flow of an electric current with the arrow. 6 is a partially enlarged view of a semiconductor test jig according to Embodiment 2. FIG. It is a top view which shows the flow of an electric current with the arrow. FIG. 6 is a plan view of a semiconductor test jig according to a third embodiment. 10 is a plan view showing a test method according to Embodiment 3. FIG. It is a top view which shows the test method which concerns on a modification. FIG. 6 is a plan view of a semiconductor test jig according to a fourth embodiment. FIG. 9 is a cross-sectional view showing a measuring apparatus and a measuring method according to Embodiment 5. It is a perspective view of a through-hole extension part.

  A semiconductor test jig, a measuring apparatus, and a test method according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view of a semiconductor test jig 10 according to Embodiment 1 of the present invention. The semiconductor test jig 10 includes a base plate 12 made of a conductive material such as aluminum. Cutout portions 12 a are formed at the corners of the base plate 12. Four holes 12 b are formed in the outer peripheral portion of the base plate 12. The notch 12a and the hole 12b are created by machining the base plate 12, for example. The cutout portion 12a and the four holes 12b are collectively referred to as an alignment portion.

  A frame body 14 is fixed to the base plate 12. The base plate 12 and the frame body 14 are screwed. The frame 14 has a plurality of frames 14a formed of an insulating material provided in a lattice shape. The frame body 14 is formed by injection molding using a resin such as a PPS or PEEK material. For example, when the semiconductor test jig 10 is used in a high-temperature environment of 200 ° C. or higher, it is desirable that the frame body 14 be made of engineering plastic having heat resistance.

  Since the frame body 14 includes 16 frames 14 a, the base plate 12 is divided into 16 installation portions 16 by the frame body 14. One installation portion 16 is sized to accommodate one vertical semiconductor chip. The frame body 14 is formed with through holes 18 a and 18 b that expose the base plate 12. The through holes 18a and 18b are formed on the left and right sides of the frame 14a. That is, two through holes 18a and 18b are formed for one frame 14a.

  2 is a cross-sectional view taken along line II-II in FIG. The frame body 14 has a slope 14 b at a portion facing the installation portion 16. The slope 14 b is formed so as to surround the installation portion 16. Further, a groove 12 c is formed in the installation portion 16 along the outer periphery of the installation portion 16.

  FIG. 3 is a perspective view of the stage 30 on which the semiconductor test jig 10 is placed. The stage 30 includes a triangular projection 34 formed on a corner of the flat surface 32 in plan view, and four projections 36 formed on the flat surface 32 that are circular in plan view. The protrusion 34 is formed higher in the Z direction than the protrusion 36.

  FIG. 4 is a front view of the measuring device 40. The measuring device 40 includes a probe card 42. The probe card 42 includes first probes 42a and 42b and a second probe 42c shorter than the first probes 42a and 42b. The probe card 42 is fixed to the attachment portion 44. The measuring apparatus according to Embodiment 1 of the present invention includes the semiconductor test jig 10, the stage 30, and the measuring device 40 described above.

  Subsequently, a test method according to Embodiment 1 of the present invention will be described. First, the vertical semiconductor chip 50 to be tested will be described with reference to FIG. The vertical semiconductor chip 50 is formed by dividing a semiconductor wafer into pieces by dicing or the like. The vertical semiconductor chip 50 includes a main body portion 50a, an upper surface electrode 50b formed on the upper surface side of the main body portion 50a, and a lower surface electrode 50c formed on the lower surface side of the main body portion 50a. The vertical semiconductor chip 50 is configured to pass a current in the vertical direction between the upper surface electrode 50b and the lower surface electrode 50c. It is desirable that the surface of the base plate 12 be cleaned or polished so that there are no burrs or protrusions so as not to damage the lower surface electrode 50c contacting the installation portion 16.

  Then, as shown in FIG. 5, the lower surface electrode 50 c of the vertical semiconductor chip 50 is brought into contact with the installation portion 16 that is a portion delimited by the frame body 14 of the semiconductor test jig 10. In this step, the inclined surface 14 b of the frame body 14 functions as a guide for guiding the vertical semiconductor chip 50 to the installation portion 16. When the vertical semiconductor chip 50 slides along the inclined surface 14b, for example, when the semiconductor wafer is separated into the vertical semiconductor chips 50, foreign matter generated at the end of the vertical semiconductor chip 50 and in the vicinity thereof hits the inclined surface 14b. It is detached from the vertical semiconductor chip 50 and accommodated in the groove 12c. Thereby, it is possible to prevent foreign matter from entering between the lower surface electrode 50 c of the vertical semiconductor chip 50 and the base plate 12. In the first embodiment of the present invention, the vertical semiconductor chips 50 are placed one by one on all 16 installation portions 16.

  Next, the semiconductor test jig 10 on which the vertical semiconductor chip 50 is mounted is placed on the stage 30. At this time, the semiconductor test jig 10 is placed on a predetermined location of the stage 30 using the alignment portion of the semiconductor test jig 10. Specifically, first, the notch 12a is applied to the side surface of the projection 34 of the stage 30, and the direction of the semiconductor test jig 10 is determined. Thereafter, the semiconductor test jig 10 is brought close to the stage 30, and the protrusion 36 is inserted into the hole 12b. In this way, the semiconductor test jig 10 is placed on a predetermined location on the stage 30 using the alignment portion.

  Next, as shown in FIG. 6, the first probes 42a and 42b are applied to the base plate 12 through the through holes 18a and 18b of the frame body 14, and the second probe 42c is applied to the upper surface electrode 50b. Then, current is applied to the first probes 42a and 42b and the second probe 42c to measure the electrical characteristics of the vertical semiconductor chip 50.

  FIG. 7 is a plan view showing by arrows the current flow in the vertical semiconductor chip 50 when measuring the electrical characteristics of the vertical semiconductor chip 50. The current is distributed in the direction of the through hole 18a and the direction of the through hole 18b. The current flow may be in the direction opposite to the arrow in FIG.

  The reason why the first probes 42a and 42b are passed through the through holes 18a and 18b of the frame 14 in the test method according to the first embodiment of the present invention is to prevent discharge by the first probes 42a and 42b. That is, since the frame body 14 is between the first probes 42a and 42b and the end of the vertical semiconductor chip 50, the discharge between them can be suppressed. Similarly, since there is the frame 14 between the first probes 42a and 42b and the second probe 42c, the discharge between them can be suppressed.

  Moreover, it can suppress that an electric charge concentrates on the specific part of the inner wall of through-hole 18a, 18b by making the planar shape of through-hole 18a, 18b circular. In order to suppress discharge, it is preferable to provide a through hole in the highest portion of the frame body 14, but the through holes 18 a and 18 b may be formed in the inclined surface 14 b of the frame body 14. In that case, care should be taken not to cause discharge.

  According to the measurement apparatus of the first embodiment of the present invention, the semiconductor test jig 10 is utilized by using the alignment portion (notch portion 12a and hole 12b) of the semiconductor test jig 10 and the protrusions 34 and 36 of the stage 30. Can be accurately placed on a predetermined location of the stage 30. Therefore, since all the vertical semiconductor chips 50 mounted on the semiconductor test jig 10 can be aligned together, the measurement process can be prevented from becoming complicated.

  Since the measuring apparatus according to the first embodiment of the present invention makes contact with the lower surface electrode 50c of the vertical semiconductor chip 50 with the first probes 42a and 42b via the base plate 12, it is possible to pass a current through the stage 30. No. Therefore, wiring from the stage to the evaluation device or the like is not necessary. Moreover, the current path from the lower surface electrode 50c through the base plate 12 to the first probes 42a and 42b is easier to shorten than the current path from the lower surface electrode through the stage and the wiring. Therefore, the measurement accuracy can be increased by reducing the inductance of the measurement device.

  The current flowing through the base plate 12 (installation portion 16) is dispersed in the direction of the through hole 18a (first probe 42a) and the direction of the through hole 18b (first probe 42b), as shown by the arrows in FIG. Therefore, the heat generation of the vertical semiconductor chip 50 and the accompanying adverse effects can be suppressed. Here, if it is not necessary to obtain such a current dispersion effect, one first probe is sufficient. Therefore, it is sufficient to provide at least one through-hole in each of the plurality of frames.

  Since the through holes 18a and 18b are formed for each frame 14a, all the vertical semiconductor chips 50 mounted on the semiconductor test jig 10 can be measured with a uniform and short current path length.

  Since the base plate 12 and the frame body 14 are fixed by screws, the frame body 14 can be exchanged or the frame body 14 can be removed and cleaned. Because of such benefits, it is preferable that the base plate 12 and the frame body 14 be removable. As a method of detachably fixing the base plate 12 and the frame body 14, there is a method in which a concave portion is provided on one of the base plate 12 and the frame body 14 and a convex portion is provided on the other, and these are fitted together.

  Various modifications can be made to the semiconductor test jig, the measuring apparatus, and the test method according to the first embodiment of the present invention. For example, the alignment portion is not limited to the notch portion 12a and the hole 12b, and for example, a notch, a hole, a concave portion, or a convex portion can be used as appropriate. Further, the semiconductor test jig 10 can be used not only for measuring the electrical characteristics of the vertical semiconductor chip 50 but also for transporting the vertical semiconductor chip 50.

  In order to make it easy to insert the first probes 42a and 42b into the through holes 18a and 18b, a chamfering process may be performed on a portion surrounding the through holes 18a and 18b of the frame body 14. It is good also as a structure which enlarges the opening diameter of the through-holes 18a and 18b, and passes several probes, such as a laminated probe, in each of the through-holes 18a and 18b. These modifications can also be applied to semiconductor test jigs, measuring apparatuses, and test methods according to the following embodiments.

  Since the semiconductor test jig, the measuring apparatus, and the test method according to the following embodiment have much in common with the first embodiment, the difference from the first embodiment will be mainly described.

Embodiment 2. FIG.
FIG. 8 is a partially enlarged view of the semiconductor test jig according to the second embodiment of the present invention. A frame body 60 is fixed to the base plate 12. Through holes 62a, 62b, 62c, and 62d are formed in the frame 60a of the frame body 60. Since the through holes 62a, 62b, 62c, and 62d are formed on each side of the frame 60a, the installation portion 16 is surrounded by the through holes 62a, 62b, 62c, and 62d. The same applies to the other installation parts.

  In the test method according to the second embodiment of the present invention, the first probe is inserted into all of the through holes 62a, 62b, 62c, and 62d, and the electrical characteristics of the vertical semiconductor chip are measured. FIG. 9 is a plan view showing by arrows the current flow in the vertical semiconductor chip 50 when measuring the electrical characteristics of the vertical semiconductor chip 50. The current is distributed in the direction of the through hole 62a, the direction of the through hole 62b, the direction of the through hole 62c, and the direction of the through hole 62d. In this way, the current distribution of the vertical semiconductor chip 50 can be made uniform by distributing the current evenly in the four directions. Therefore, local heat generation in the vertical semiconductor chip 50 can be suppressed. The current flow may be in the direction opposite to the arrow in FIG.

  The number and arrangement of the through holes formed in the frame body 60 can be arbitrarily set as long as the current distribution of the vertical semiconductor chip can be made uniform. In order to make the current of the vertical semiconductor chip uniform, a plurality of through holes may be provided so as to surround each of the plurality of frames.

Embodiment 3 FIG.
FIG. 10 is a plan view of a semiconductor test jig 100 according to Embodiment 3 of the present invention. A through hole 104 is formed at the center of the frame body 102 in plan view. The through hole 104 is formed in the frame 102 only at one place.

  FIG. 11 is a plan view showing a test method according to Embodiment 3 of the present invention. First, one vertical semiconductor chip is placed on all the installation parts 16 one by one. In FIG. 11, the upper surface electrode 50b appears. Next, the semiconductor test jig 100 is placed on a predetermined portion of the stage by making full use of the alignment portion. Next, the first probe 106 is applied to the base plate 12 through the through hole 104, and the second probe 108 is applied to the upper surface electrode 50b of the semiconductor chip. Next, the electrical characteristics of each semiconductor chip are measured.

  In Embodiment 3 of the present invention, one first probe 106 is used as a contact for the lower surface electrodes of all semiconductor chips. Since the distance from the first probe 106 to the lower surface electrode of each vertical semiconductor chip is substantially uniform, measurement can be performed under substantially the same conditions for each vertical semiconductor chip. In addition, since it is not necessary to form a plurality of through holes in the frame body 102, the manufacturing cost of the frame body 102 can be reduced compared to the case where a plurality of through holes are formed.

  For example, in order to simultaneously pass a plurality of first probes through the through-holes, it is necessary that each element of the measuring device is accurately positioned, which complicates the process. However, when only one through hole 104 is formed as shown in FIG. 11, the first probe 106 can be easily passed through the through hole 104, so that the process can be shortened. Since the above-described effect can be obtained if the through hole 104 is formed at one place in the frame body 102, the through hole may be formed at a position other than the center of the frame body.

  FIG. 12 is a plan view showing a test method according to a modification. The vertical semiconductor chips are not placed on the four installation portions 16 adjacent to the through holes 104, and the vertical semiconductor chips are placed on the 12 installation portions 16 apart from the through holes 104. In this case, the distance between the first probe 106 and the second probe 108 can be increased as compared with the case where the vertical semiconductor chips are placed on all the installation portions 16, so that the discharge suppressing effect can be enhanced.

Embodiment 4 FIG.
FIG. 13 is a plan view of a semiconductor test jig 150 according to Embodiment 4 of the present invention. Through holes 154, 156, 158, 160 are formed at corners of the frame body 152. The first probe applied to the base plate 12 through the through-hole 154 is used for the vertical semiconductor chip placed on the four installation portions 16 indicated by A. For the vertical semiconductor chip placed on the four installation portions 16 indicated by B, the first probe applied to the base plate 12 through the through hole 156 is used. For the vertical semiconductor chip placed on the four installation portions 16 indicated by C, the first probe applied to the base plate 12 through the through hole 158 is used. For the vertical semiconductor chip placed on the four installation portions 16 indicated by D, the first probe applied to the base plate 12 through the through hole 160 is used.

  When the semiconductor test jig 150 is used in this way, it is possible to measure four vertical semiconductor chips at a time using the four first probes simultaneously. Further, the distance from the first probe to the lower surface electrode can be made substantially uniform for all the vertical semiconductor chips. For example, by placing a vertical semiconductor chip on the other three installation parts 16 without placing a vertical semiconductor chip on the place closest to the through hole 154 among the four installation parts 16 indicated by A, The distance between the first probe and the second probe may be increased.

Embodiment 5. FIG.
FIG. 14 is a cross-sectional view showing a measuring apparatus and a measuring method according to Embodiment 5 of the present invention. This measuring device is characterized by the shape of the frame and the suction mechanism of the vertical semiconductor chip and the base plate. First, the shape of the frame will be described. A through-hole extension 200 made of the same material as the frame 14 is fixed on the frame 14. The frame body 14 and the through-hole extension 200 constitute a frame body 202. The through hole 204 of the frame body 202 is longer than the through hole of the frame body 14 alone.

  The through-hole extension portion 200 and the frame body 14 immediately below the through-hole extension portion 200 are referred to as a convex portion. A convex part is a part which forms the through-hole 204 among the frame bodies 202, and is formed higher than another part. FIG. 15 is a perspective view of the through hole extension 200. The side surface of the through-hole extension 200 is formed with a curved surface. A side surface of the frame body 14 is formed as a flat surface. Therefore, the side surface of the convex portion is formed as a curved surface or a flat surface.

  By providing the convex portion, the length of the through hole 204 is longer than the length of the through hole in the first to fourth embodiments. Therefore, by measuring the electrical characteristics of the vertical semiconductor chip through the first probe in the through hole 204, the discharge between the first probe and the vertical semiconductor chip and between the first probe and the second probe. Can be reliably suppressed. And since the side surface of the convex part was formed in the curved surface or the plane, the discharge by the electric charge concentrating on a convex part can be prevented. The frame body 14 and the through hole extension 200 may be integrally formed.

  Next, a suction mechanism for the vertical semiconductor chip and the base plate will be described with reference to FIG. A through hole 210 is formed in a portion of the base plate 12 that is partitioned by the frame body 14 (installation portion 16). An intake passage 212 is formed in the stage 30 immediately below the through hole 210 and directly below the base plate 12.

  For example, by connecting an intake device such as a vacuum pump to the intake passage 212, the vertical semiconductor chip 50 can be adsorbed and fixed to the base plate 12 and the base plate 12 can be adsorbed and fixed to the stage 30. Therefore, when the first probe is brought into contact with the base plate 12 and the second probe is brought into contact with the vertical semiconductor chip 50, and during measurement, the positional deviation between the vertical semiconductor chip 50 and the base plate 12 can be suppressed. Thereby, it is possible to prevent the vertical semiconductor chip 50 from being damaged or foreign matter from entering between the vertical semiconductor chip 50 and the base plate 12 due to the displacement. The through hole 210 and the intake passage 212 may be formed linearly in plan view.

  The features of the semiconductor test jig, the measurement apparatus, and the test method according to each of the embodiments so far may be appropriately combined.

  DESCRIPTION OF SYMBOLS 10 Semiconductor test jig | tool, 12 Base board, 12a Notch part, 12b Hole, 12c Groove, 14 Frame body, 14a Frame, 14b Slope, 16 Installation part, 18a, 18b Through-hole, 30 Stage, 32 Flat surface, 34, 36 protrusions, 40 measuring instrument, 42 probe card, 42a, 42b first probe, 42c second probe, 50 vertical semiconductor chip, 50a main body, 50b upper surface electrode, 50c lower surface electrode, 60 frame body, 60a frame, 62a , 62b, 62c, 62d Through hole, 100 Semiconductor test jig, 102 Frame body, 104 Through hole, 106 First probe, 108 Second probe, 150 Semiconductor test jig, 152 Frame body, 154, 156, 158, 160 Through hole, 200 Through hole extension, 202 Frame body, 204 Hole, 210 through hole 212 intake passage

Claims (10)

A base plate formed of a conductive material;
A plurality of frames fixed to the base plate and formed of an insulating material and provided in a lattice shape, and
A through hole for exposing the base plate is formed in the frame body.   The semiconductor test jig according to claim 1, wherein at least one through hole is provided in each of the plurality of frames.   The semiconductor test jig according to claim 1, wherein a plurality of the through holes are provided so as to surround each of the plurality of frames.   The semiconductor test jig according to claim 1, wherein the through hole is formed at a center of the frame.   The semiconductor test jig according to claim 1, wherein the through hole is formed at a corner of the frame.   The semiconductor test jig according to claim 1, wherein the through hole is formed at one place in the frame.   The semiconductor test jig according to claim 1, wherein a through hole is formed in a portion of the base plate that is partitioned by the frame.   The semiconductor test jig according to claim 1, wherein a side surface of the frame body is an inclined surface.   A base plate formed of a conductive material having notches, holes, recesses, or projections used as an alignment portion, and a plurality of frames fixed to the base plate and formed of an insulating material are in a lattice shape A semiconductor test jig in which a through hole for exposing the base plate is formed in the frame body,
  A stage for placing the semiconductor test jig on a predetermined location using the alignment unit;
  A measuring apparatus comprising: a first probe; and a measuring instrument having a second probe shorter than the first probe.   The base of a semiconductor test jig, comprising: a base plate formed of a conductive material; and a frame body fixed to the base plate and having a plurality of frames formed of an insulating material provided in a lattice shape. A step of contacting the lower surface electrode of the vertical semiconductor chip having an upper surface electrode and a lower surface electrode to a portion of the plate separated by the frame body;
  Placing the semiconductor test jig on a stage;
  The first probe is applied to the base plate through a first hole in a through-hole formed to expose the base plate to the frame, the second probe is applied to the upper surface electrode, and the vertical type And a step of measuring electrical characteristics of the semiconductor chip.

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