JP2001051011A - Evaluation method for high-breakdown-voltage semiconductor chip, high-breakdown-voltage electronic apparatus board and its manufacture as well as high- breakdown-voltage semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high-breakdown-voltage semiconductor chip whose yield is en hanced after a product is assembled and whose production cost can be reduced by evaluating the characteristic of the high-breakdown-voltage semiconductor chip in a state that an elastic insulator is pressed and that a high voltage is applied. SOLUTION: A silicone rubber 8 is pressed to the termination part 9 of a high- breakdown-voltage semiconductor chip 6 in a bare state. As a result, a spark path from the side face of the chip 6 to an emitter electrode 13E can be cut off by the silicone rubber 8. Since the spark path is cut off, it is possible to suppress the generation of a spark even when a high voltage, e.g. at 200 V or higher, concretely at 4000 to 4500 V, is applied. As a result, the spark is hard to fly from the side face part of the high-breakdown-voltage semiconductor chip 6 up to the surface part of the chip, or between the high-breakdown-voltage semiconductor chip and a bonding wire which connects the chip to a board 1. Consequently, before a product is assembled, a semiconductor electronic apparatus board can be evaluated under a high-voltage environment, e.g. at 2,000 V or higher.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor chip, a high breakdown voltage electronic device substrate on which the high breakdown voltage semiconductor chip is mounted, and a high breakdown voltage semiconductor device using the high breakdown voltage electronic device substrate. It relates to reduction, improvement of reliability, and improvement of heat radiation characteristics.

[0002]

2. Description of the Related Art A high breakdown voltage semiconductor chip is a chip on which a power device, for example, an IGBT, a vertical MOSFET, a diode or the like is formed, and is used for power electronics products. Such power electronics products are widely used as control elements of power electronics systems such as uninterruptible power supply (UPS) and motor control.

[0003] Power electronics products have a rated voltage of several hundreds to several thousand volts depending on the application and the power device formed on the chip. For example, the rated voltage of an IGBT product is usually about several hundred to 2000 V.

[0004] In such IGBT products and other products, a higher rated voltage is required in accordance with the expansion of the application and the demand for higher power of the power electronics system. Products having a rated voltage of about 4000 to 4500 V have been developed.

However, the withstand voltage in a bare state where the chip is covered with a thin insulating film such as a silicon oxide film or a polyimide resin is, for example, about 2000 V. That is, when a high voltage of, for example, 2,000 V or more is applied between the collector and the emitter in a bare state of the chip, sparks fly from the side surface of the chip toward the emitter electrode formed on the upper surface of the chip, and the terminal portion of the chip is terminated. It will be destroyed.

For this reason, first, evaluation is performed under a voltage environment of 2000 V or less, and a defective chip is rejected. Thereafter, the non-defective chips are transferred to, for example, DBC (Direct Bond Copp
er) A high breakdown voltage electronic device substrate is obtained by mounting the device on a substrate or the like and wire bonding the electrodes of the chip to the wiring pattern of the DBC substrate.

[0007] Next, evaluation is performed again under a voltage environment of 2000 V or less in the state of the high breakdown voltage electronic device substrate, and the defective substrate is rejected. The evaluation under a voltage environment of 2000 V or less is because the chip is bare even in the substrate state. Thereafter, the good chip is soldered to, for example, a copper base, electrodes and a case are attached, and the inside of the case is filled with silicone gel, epoxy resin, or the like. In this state, that is, when the product is completed, 200
The evaluation is performed again under a voltage environment of 0 V or more.

[0008]

However, in the above evaluation method, for example, the rated voltage is 4000 to 4500.
In the case of V, a chip which becomes defective in the range of 2000 V to 4000 to 4500 V and an electronic device substrate cannot be rejected in advance. For this reason, the probability of failure in a product completed state increases, and there is a situation that manufacturing costs increase.

Also, in the process of finishing the electronic device substrate to a finished product state, there is a heat process of bonding the electronic device substrate and the copper base by soldering. In some cases, warpage may occur. When warpage occurs, heat radiation becomes uneven or insufficient. Furthermore, the solder may deteriorate due to thermal fatigue during actual operation, and the reliability of the high breakdown voltage semiconductor device may decrease. To avoid this possibility, instead of a copper base, AlSiC whose thermal expansion coefficient is close to that of the electronic device substrate
The use of substrates has led to an increase in component material costs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the manufacturing cost and to provide a highly reliable method for evaluating a high withstand voltage semiconductor chip, a high withstand voltage electronic device substrate, and a method for manufacturing the same. And a high breakdown voltage semiconductor device.

[0011]

In order to achieve the above object, a method for evaluating a high breakdown voltage semiconductor chip according to the present invention comprises:
An elastic insulator is pressed against the end portion of the bare high-voltage semiconductor chip, and a high voltage is applied to the high-voltage semiconductor chip while the elastic insulator is pressed. The characteristics of the high breakdown voltage semiconductor chip are evaluated in a state where the elastic insulator is pressed and the high voltage is applied.

According to the evaluation method having the above structure, an elastic insulator is pressed against the end portion of the bare high voltage semiconductor chip. For this reason, a high voltage, for example, 2
Even when a voltage of 000 V or more is applied, it is difficult for a spark to fly from the side surface portion of the chip to the upper surface portion of the chip. Therefore, it is possible to evaluate the high breakdown voltage semiconductor chip in a bare state under a high voltage environment of, for example, 2000 V or more. That is, when a high voltage semiconductor chip is to be used for a product having a rated voltage of 2000 V or more, for example, the chip can be evaluated under a rated voltage environment before assembling the product.

Thus, before assembling the product, for example, 200
Chips that become defective under a high voltage environment of 0 V or more can be rejected. Therefore, the yield after product assembly can be improved, and the manufacturing cost can be reduced.

When the assembled product is a module product on which a plurality of high voltage semiconductor chips are mounted,
The situation where one chip having a low withstand voltage is wasted on another chip having a high withstand voltage or an assembly member such as a substrate, a frame, or a lid is reduced, and the effect of reducing the manufacturing cost is further increased.

Further, since the high-breakdown-voltage semiconductor chip may be kept in a bare state, for example, it is not necessary to apply special processing to the end portion of the chip, there is almost no increase in the evaluation cost in implementing the above-described evaluation method. .

Further, since the elastic insulator is pressed against the end portion of the bare high-voltage semiconductor chip, the adhesion between the insulator and the chip is improved. By improving the adhesion, the effect of suppressing the spark is further enhanced.

In order to achieve the above object, a high withstand voltage electronic device substrate according to the present invention includes a bare high withstand voltage semiconductor chip, the bare high withstand voltage semiconductor chip mounted thereon, and the high withstand voltage semiconductor chip. The bare state, in which at least a region to which an external terminal is connected is exposed and a high voltage is applied, of the substrate on which the high breakdown voltage semiconductor chip in the bare state is mounted, and And a resilient insulator for covering a region including the surface of the high-breakdown-voltage semiconductor chip.

According to the high breakdown voltage electronic device substrate having the above structure, at least a region to which an external terminal is connected is exposed and a high voltage is applied on the substrate on which the bare high breakdown voltage semiconductor chip is mounted. A region to which a high voltage is applied, including the surface of the bare high-voltage semiconductor chip, is covered with an elastic insulator. For this reason,
For example, even when a voltage of 2000 V or more is applied, sparks are unlikely to fly from the side surface portion of the high breakdown voltage semiconductor chip to the upper surface portion of the chip, or between bonding wires connecting the chip and the substrate. Therefore, it is possible to evaluate the semiconductor electronic device substrate under a high voltage environment of, for example, 2000 V or more before product assembly.

Thus, before assembling the product, for example, 200
It is possible to reject a high-withstand-voltage electronic device substrate that becomes defective under a high-voltage environment of 0 V or more. Therefore, the yield after product assembly can be improved, and the manufacturing cost can be reduced.

In the case where the assembled product is a module product on which a plurality of high-withstand-voltage electronic device boards are mounted,
For one electronic equipment board with poor withstand voltage, another electronic equipment board with good withstand voltage or a board on which the electronic equipment board is mounted,
The situation where assembly members such as frames and lids are wasted is reduced,
The effect of reducing the manufacturing cost is further increased.

The insulator covering the electronic device substrate is
It has elasticity. For this reason, when the chip generates heat, the thermal stress acting between the chip or the electronic device substrate and the insulator is reduced.

The method of manufacturing the semiconductor device further comprises mounting and electrically connecting a bare high-voltage semiconductor chip to the substrate, wherein at least an external terminal of the substrate on which the bare high-voltage semiconductor chip is mounted is mounted. And forming a resilient insulator by injection molding, exposing a region to which a high voltage is applied including the surface of the bare high-voltage semiconductor chip in a bare state. And

In order to achieve the above object, a high breakdown voltage semiconductor device according to the present invention includes a bare high breakdown voltage semiconductor chip, a bare high breakdown voltage semiconductor chip mounted thereon, and the high breakdown voltage semiconductor chip mounted thereon. Electrically connected substrate and, of the substrate on which the bare high voltage semiconductor chip is mounted, at least a region to which external terminals are connected is exposed, and the surface of the bare high voltage semiconductor chip is exposed. A high withstand voltage electronic device substrate including a resilient insulator covering a region to which a high voltage is applied, a radiator, and pressing the resilient insulator to form the high withstand voltage electron. And a pressure contact member for pressing an apparatus substrate against the heat radiator.

According to the high-breakdown-voltage semiconductor device having the above configuration, the same effect as that of the high-breakdown-voltage electric device substrate can be obtained because the high-breakdown-voltage electronic device substrate is provided. At the same time, the high-withstand-voltage electronic device substrate is pressed against the radiator by pressing an elastic insulator. The elastic insulator also functions as a chip molding material and a pressure-cushioning cushion material. As a result, an adhesive member such as solder or a member such as a spring for pressing is not required to fix the high withstand voltage electronic device substrate to the heat radiator, so that manufacturing costs can be reduced.

Further, since an adhesive member is unnecessary, the reliability does not decrease due to the deterioration of the adhesive member, and it is possible to withstand use for a long period of time or use in a severe environment.

In addition, since the high-withstand-voltage electronic device substrate is pressed against the radiator without the interposition of an adhesive member, good heat radiation can be obtained.

Further, the chip, which is the main heat generating portion, can be pressed against the chip via an elastic insulator, and when the chip is pressed, a better heat radiation property can be obtained.

Further, since the insulator having elasticity is pressed during the pressure contact, the pressure is easily applied evenly to the high withstand voltage electronic device substrate, and the adhesion between the high withstand voltage electronic device substrate and the radiator is improved. It will be good. With good adhesion,
The heat dissipation is also good.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

[First Embodiment] FIG. 1 is a view showing an evaluation jig used in a method for evaluating a high breakdown voltage semiconductor chip according to a first embodiment of the present invention.

As shown in FIG. 1, the evaluation jig mainly comprises a stage 1, a probe 2 (2E, 2G), and a probe holder 3 for holding the probe 2. The stage 1 and the probe 2 are electrically connected to an electric property measuring device 4.

The stage 1 is provided with a mounting portion 5. The high breakdown voltage semiconductor chip 6 is mounted on the mounting portion 5. A power device such as an IGBT is formed on the high breakdown voltage semiconductor chip 6, for example.

An attachment 7 is formed on the holding base 3. A silicone rubber 8 is attached to the attachment portion 7. The silicone rubber 8 is an insulating resin having elasticity.

FIG. 2 is a perspective view showing the chip 6 and the silicone rubber 8.

As shown in FIG. 2, one example of the silicone rubber 8 has a frame shape corresponding to the end portion 9 of the chip 6. Silicone rubber 8 according to one example,
It has a fitting portion 10 fitted to the mounting portion 7 and a pressing portion 11 pressed against the end portion 9. The pressing portion 11 has a narrower width than the fitting portion 10, and when pressed,
It is easier to crush than the fitting portion 10. Such a silicone rubber 8 has an advantage that it easily adheres to the terminal portion 9.

Next, a specific example of an evaluation method using the above-described evaluation jig will be described.

FIGS. 3A to 3D are diagrams for explaining a specific example of the evaluation method.

First, as shown in FIG. 3A, for example, an IGBT is formed on a silicon wafer 12 by a wafer process, and a plurality of high voltage semiconductor chips 6 on which the IGBT is formed are obtained on the silicon wafer 12.

Next, as shown in FIG. 3B, the wafer 12 is diced to separate the chips 6 from the wafer 12.

Next, as shown in FIG. 3C, the chip 6 in the separated state (bare state) is placed on the mounting portion 5 of the stage 1.
Place on. Further, the silicone rubber 8 is attached to the attaching portion 7 of the holding base 3. At this time, the collector electrode 13C formed on the back surface of the chip 6 is electrically connected to the electrical property measuring device 4 via the stage 1 or an electrode (not shown) formed on the stage 1.

Next, as shown in FIG. 3D, the stage 1 is raised or the holding table 3 is lowered, and the silicone rubber 8 is pressed against the end portion 9 of the chip 6. At this time, the silicone rubber 8 extends from above the side surface of the chip 6 to above the emitter electrode 13E formed on the upper surface of the chip 6, and from above the side surface of the chip 6 to the gate electrode formed on the upper surface of the chip 6. It is better to press each of them above 13G.

Further, the stage 1 is raised or the holding table 3
Is lowered, the probe 2E is connected to the emitter electrode 13
E, and the probe 2G is brought into contact with the gate electrode 13G. Thereby, the emitter electrode 13E and the gate electrode 13G are each electrically connected to the electrical characteristic measuring device 4.

Next, while the silicon rubber 8 is pressed against the terminal portion 9, a voltage of 4000 to 4500V is applied.
Applied to chip 6. An example of voltage application is to apply, for example, 4000 to 4500 V to the collector electrode 13C, a ground potential (0 V) to the emitter electrode 13E, and a ground potential (0 V) to the gate electrode 13G.

Next, the silicon rubber 8 is pressed.
And with a voltage of 4000 to 4500 V applied,
The characteristics of the chip 6 are evaluated using the electric characteristic measuring device 4.

In the evaluation method according to the first embodiment, the silicone rubber 8 is pressed against the end portion 9 of the bare chip 6. For this reason, as shown in FIG.
Spark path 15 (or gate electrode)
Can be blocked by the silicone rubber 8 as shown in FIG. As a result of the spark path 15 being cut off, for example, 2000 V or more, specifically 400
Even when a high voltage such as 0 to 4500 V is applied, generation of spark can be suppressed. For this reason, it is possible to evaluate the bare chip 6 under a high voltage environment of, for example, 2000 V or more.

Therefore, the chip 6 is connected to the rated voltage 2
Even when the chip 6 is used for a product of 000 V or more, it is possible to evaluate the chip 6 under a rated voltage environment before assembling the product. That is, before assembling the product, for example, 2000
A chip 6 that becomes defective under a high voltage environment of V or more can be rejected in advance, and the yield after product assembly can be improved. As a result, the yield after assembly of the product can be improved. As a result, the situation in which assembly members such as the case and the insulating resin filling the case are wasted is reduced, and the manufacturing cost can be reduced.

When the assembled product is a module product on which a plurality of chips 6 are mounted, one chip 6 having a poor withstand voltage does not waste another chip 6 having a good withstand voltage. Therefore, the effect of reducing the manufacturing cost is further enhanced.

Further, since the chip 6 may be kept in a bare state, the spark path 15
Since there is no need to perform a process of cutting off the evaluation, there is almost no increase in the evaluation cost in implementing the above evaluation method.

Further, by pressing an insulating material having elasticity like the silicone rubber 8 against the end portion 9 of the chip 6 in a bare state, the adhesion between the silicone rubber 8 and the chip 6 is improved. And the effect of suppressing the spark can be improved.

In the first embodiment, an IGBT is illustrated as an example of a power device.
The first embodiment can be applied to an FET, a diode, and the like.

In the first embodiment, FIG.
Although the bare chip 6 shown in FIG. 3B is evaluated, it is also possible to evaluate the chip 6 in the state of the wafer 12 shown in FIG.

[Second Embodiment] In a power electronics product, a high breakdown voltage semiconductor chip 6 is mounted on an electronic device substrate, and the electrodes of the chip 6 and the wiring pattern of the substrate are wire-bonded and then housed in a case. There is.

In the case of such a product, in a state where the chip 6 is mounted / wire-bonded to the electronic device substrate,
It is desirable to evaluate.

However, as described above, the withstand voltage of the chip 6 in the bare state is, for example, about 2000 V, and it is not possible to evaluate a product having a rated voltage of 2000 V or more. For this reason, the probability of failure in the completed state of the product increases.

In the second embodiment, for example, 2000
The present invention relates to a high withstand voltage electronic device substrate which can be evaluated under a voltage environment of V or more.

FIGS. 5A to 11A show a high breakdown voltage electronic device substrate and a high breakdown voltage semiconductor device using the high breakdown voltage electronic device substrate according to the second embodiment of the present invention in the order of manufacturing steps. FIG. 5B to FIG.
FIG. 5A is a sectional view taken along the line BB in FIG.
(C) to FIG. 11 (C) are cross-sectional views along the line CC in FIG. 5 (A) to FIG. 11 (A).

Hereinafter, a high-breakdown-voltage electronic device substrate according to the second embodiment and a high-breakdown-voltage semiconductor device using the high-breakdown-voltage electronic device substrate will be described together with a method of manufacturing the same.

As shown in FIGS. 5A to 5C, D
A BC (Direct Bond Copper) substrate 21 is prepared. DB
The C substrate 21 includes an insulating substrate 22, a collector wiring layer 23C formed on the upper surface of the insulating substrate 22, and an emitter wiring layer 23.
E, gate wiring layers 23G-1, 23G-2, and a copper (Cu) layer 24 formed on the back surface of the insulating substrate 22. The insulating substrate 22 is made of, for example, alumina (Al
₂ O ₃ ), aluminum nitride (AlN), and silicon nitride (SiN). The collector wiring layer 23C, the emitter wiring layer 23E, and the gate wiring layers 23G-1, 23G-2,
3G-2 is, for example, copper (Cu), aluminum (A
l), consisting of a laminated structure of copper and aluminum.

Next, as shown in FIGS. 6A to 6C, the high breakdown voltage semiconductor chip 6 is mounted on the collector wiring layer 23C. In this example, four IGBT chips 6
-1 to 6-4, two FWD (Free-Wheeling Diode) chips 6-5 and 6-6 are mounted. With this mount, I
Collector electrode 13C of GBT chips 6-1 to 6-4, FWD
The cathode electrodes 13K of the chips 6-5 and 6-6 are electrically connected to the collector wiring layer 23C by the solder layer 25, respectively.

Next, as shown in FIGS. 7A to 7C, the emitter electrodes 13E of the IGBT chips 6-1 to 6-4 are respectively used for the emitter wiring layers 23E and the emitter bonding wires 26E. Electrical connection. Also, I
The gate electrodes 13G of the GBT chips 6-1 and 6-2 are electrically connected to the gate wiring layers 23G-1 by using gate bonding wires 26G. Further, the gate electrodes 13G of the IGBT chips 6-3 and 6-4 are electrically connected to the gate wiring layers 23G-2 using the bonding wires 26G for gates. Also, FWD chips 6-5, 6-6
Anode electrodes 13A are respectively connected to the emitter wiring layers 23E.
Are electrically connected using an anode bonding wire 26A. Thus, an electronic device substrate 30 having a circuit as shown in FIG. 12 is obtained.

Next, as shown in FIGS. 8A to 8C, the periphery of the insulating substrate 22 of the electronic device substrate 30 is covered with a collector wiring layer 23C, an emitter wiring layer 23E, and a gate wiring layer 23G-1. , 23G-2, the connection portion 27 of the external electrode
Coated with silicone rubber 28 except for C, 27E, 27G-1, 27G-2. When the copper layer 24 is present as in this embodiment, the copper layer 24 is not covered with the silicone rubber 28. This coating is performed by injection molding, and the connection portions 27C, 27E, 27G-1,
27G-2, the periphery of the insulating substrate 22 excluding the copper layer 24 can be covered with high accuracy, which is desirable.

One example of the mold used for the injection molding has a cavity for filling the silicone rubber 28 corresponding to the periphery of the electronic device substrate 30, and has connection portions 27 C, 27 E, and 27 G− in the cavity. 1, has a part that contacts 27G-2. In addition, the electronic device substrate 30 may be placed, for example, on a mold with the copper layer 24 in contact therewith.

By using such a mold and forming the silicone rubber 28 by injection molding, the electronic device substrate 30 shown in FIGS. 8A to 8C can be connected to, for example, the connection portions 27C, 27E, and 27G. -1, 27G-2, without the need to remove the silicone rubber 28 from the copper layer 24,
Obtainable.

Next, as shown in FIGS. 9A to 9C, the electronic device substrate 30 shown in FIGS.
Is placed on an evaluation jig (not shown), and 4000 to 450
A voltage of 0 V is applied to the electronic device substrate 30. An example of the voltage application is that the probe 2 is connected to the collector wiring layer 23C, for example.
4000-4500V via 9C, emitter wiring layer 2
The ground potential (0 V) is applied to 3E via the probe 29E, and the probes 29G-1, 29G are applied to the gate wiring layers 23G-1, 23G-2.
A ground potential (0 V) is applied via G-2. After this, 40
With the voltage of 00 to 4500 V applied, the characteristics of the electronic device substrate 30 are evaluated. In this evaluation, the electronic device substrate 30 determined to be defective is rejected.

Next, as shown in FIGS. 10A to 10C, the electronic device substrate 30 determined to be non-defective by the above evaluation is fixed on the copper base 31. In this example, the copper layer 24 formed on the back surface of the electronic device substrate 30 is fixed on the copper base 31 via the solder layer 32.

Next, as shown in FIGS. 11A to 11C, connection portions 27C, 27E and 27G-
External electrodes 33C, 33E, 3
3G is connected, and the frame body 34 is fixed to the periphery of the copper base 31. Next, a lid 3 having external terminals 35C, 35E, 35G connected to the external electrodes 33C, 33E, 33G.
6 (not shown in FIG. 11A)
It is fixed to the frame 34. Thus, the IGBT product 37 using the electronic device substrate 30 according to the second embodiment is completed. The IGBT product 37 is used, for example, with a heat sink (not shown) connected to the copper base 31.

The electronic device substrate 3 according to the second embodiment.
0, the collector wiring layer 2 is formed on the electronic device substrate 30.
3C, the emitter wiring layer 23E, the gate wiring layer 23G-1,
23G-2, connecting portions 27C, 27E of the external electrodes,
Except for 27G-1 and 27G-2, it is covered with silicone rubber 28. Thereby, portions where a spark path is formed on the electronic device substrate 30, for example, between the collector wiring layer 23C and the bonding wire 26E for the emitter, between the collector wiring layer 23C and the bonding wire 26G for the gate, Between the layer 23C and the bonding wire 26A for the anode;
6-4 and the end portions of the FWD chips 6-5 and 6-6 are covered with the silicone rubber 28, respectively. Thus, the spark path on the electronic device substrate 30 is blocked by the silicone rubber 28. As a result of the interruption of the spark path, for example, 2000 V or more, specifically 400
Even when a high voltage such as 0 to 4500 V is applied, generation of spark can be suppressed. Therefore, the electronic device substrate 3
0 can be evaluated under a high voltage environment of, for example, 2000 V or more.

Therefore, before assembling the product, for example, 2000
An electronic device substrate 30 that becomes defective under a high voltage environment of V or more can be rejected in advance, and the yield after product assembly can be improved. As a result, the yield after assembly of the product can be improved. As a result, a situation in which assembly members such as a case (a frame and a lid) are wasted is reduced, and manufacturing costs can be reduced.

The electronic device substrate 30 is covered with an elastic insulator such as silicone rubber 28. Thereby, when the chips 6-1 to 6-6 generate heat, the thermal stress acting particularly between the chips 6-1 to 6-6 and the silicone rubber 28 can be reduced, and the reliability of the device can be improved. .

In the second embodiment, an IGBT is used as an example of a power device.
Another power device such as an FET may be used.

Further, in the second embodiment, the electronic device substrate 30 on which the plurality of chips 6-1 to 6-6 are mounted is illustrated, but one chip may be mounted.

Although the IGBT product 37 on which one electronic device substrate 30 is mounted has been illustrated, a plurality of electronic device substrates may be mounted.

In particular, in the case of a product on which a plurality of electronic device boards 30 are mounted, there is no need to waste another electronic device substrate 30 having a good withstand voltage for one electronic device substrate 30 having a withstand voltage defect. Therefore, the effect of reducing the manufacturing cost is further enhanced.

In the second embodiment, since the periphery of the electronic device substrate 30 is covered with the silicone rubber 28, the inside of the case does not need to be filled with silicone gel or epoxy resin as in the conventional case. If the case is not filled with silicone gel or epoxy resin,
Manufacturing costs can be reduced. However, if necessary, the inside of the case can be filled with silicone gel or epoxy resin.

The silicone rubber 28 is provided around the insulating substrate 22 of the electronic device substrate 30, that is, the upper surface, the side surface,
Although the example in which the bottom surface is covered has been described, the silicone rubber 28 may cover only the upper surface of the insulating substrate 22.

[Third Embodiment] In the third embodiment, using the electronic device substrate 30 described in the second embodiment, it is possible to reduce the manufacturing cost, particularly for assembly, or to improve the reliability regarding the life of the device. The present invention relates to a high breakdown voltage semiconductor device that can be improved.

FIG. 13 is a sectional view of a high voltage semiconductor device according to the third embodiment.

As shown in FIG. 13, the pressure contact plate 41 is placed on the silicone rubber 28 of the electronic device substrate 30. The press contact plate 41 is fixed to the heat sink 43 by a screw 42.
It is fixed to. As a result, the electronic device substrate 30 includes
A pressure is applied from the pressure contact plate 41, and the electronic device substrate 30 is pressed against the heat sink 43.

A case 44 is fixed on the heat sink 43. The case 44 houses the electronic device substrate 30.

In the high withstand voltage semiconductor device according to the third embodiment, the electronic device substrate 30 is pressed against the heat sink 43 by pressing the elastic silicone rubber 28. Therefore, for example, soldering is not required to fix the electronic device substrate 30 to the heat sink 43, and the manufacturing cost can be reduced.

Further, since no solder is required, the reliability does not decrease due to the deterioration of the solder, and the device can withstand use for a long period of time or in a severe environment, thereby improving its reliability. Can be done.

Further, since the electronic device substrate 30 is pressed against the heat sink 43 without using the solder, the heat dissipation is good. In addition, since the chip 6 which is the main heat-generating portion is pressed against the chip via the silicone rubber 28, the heat radiation is further improved.

Also, since the silicone rubber 28 having elasticity is pressed at the time of pressing, the pressure is easily applied evenly to the electronic device substrate 30, and the electronic device substrate 3 is pressed.
0 and the heat sink 43 have good adhesion. When the adhesiveness is good, the heat dissipation is also good.

FIG. 14 is a sectional view of a high breakdown voltage semiconductor device according to a modification of the third embodiment.

As shown in FIG. 14, in the third embodiment, since no solder is required, the copper layer 24 can be omitted from the DBC substrate 21.

According to such a modification, the same effect as that of the third embodiment can be obtained, and the copper layer 24 can be omitted, so that the manufacturing cost of the DBC substrate 21 can be suppressed. Obtainable.

[0087]

As described above, according to the present invention, it is possible to provide a method for evaluating a high-breakdown-voltage semiconductor chip, a high-breakdown-voltage electronic device substrate and a method for manufacturing the same, and a high-breakdown-voltage semiconductor device which can reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a view showing an evaluation jig used in a method for evaluating a high breakdown voltage semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a chip and a silicone rubber.

FIGS. 3A to 3D are diagrams for explaining a method for evaluating a high breakdown voltage semiconductor chip according to the first embodiment;

FIGS. 4A and 4B are cross-sectional views each showing a high breakdown voltage semiconductor chip on which an IGBT is formed.

FIG. 5A is a plan view showing one manufacturing step of an electronic device substrate according to a second embodiment of the present invention, and FIG. 5B is a sectional view taken along line BB in FIG. 5A. FIG. 5C is a cross-sectional view taken along the line CC in FIG. 5A.

FIG. 6A is a plan view showing one manufacturing step of an electronic device substrate according to a second embodiment of the present invention, and FIG. 6B is a sectional view taken along line BB in FIG. 6A. FIG. 6C is a cross-sectional view along the line CC in FIG. 6A.

7A is a plan view showing one manufacturing step of an electronic device substrate according to a second embodiment of the present invention, and FIG. 7B is a view taken along line BB in FIG. 7A. FIG. 7C is a cross-sectional view taken along the line CC in FIG. 7A.

FIG. 8A is a plan view showing one manufacturing step of an electronic device substrate according to a second embodiment of the present invention, and FIG. 8B is a view taken along line BB in FIG. 8A. FIG. 8C is a cross-sectional view taken along line CC in FIG. 8A.

FIG. 9A is a plan view showing one manufacturing step of an electronic device substrate according to a second embodiment of the present invention, and FIG. 9B is a sectional view taken along line BB in FIG. 9A. FIG. 9C is a cross-sectional view taken along the line CC in FIG. 9A.

FIG. 10A is a plan view showing one manufacturing step of an electronic device substrate according to a second embodiment of the present invention, and FIG.
FIG. 1B is a sectional view taken along line BB in FIG.
0 (C) is a sectional view taken along line CC in FIG. 10 (A).

FIG. 11A is a plan view showing one manufacturing step of the electronic device substrate according to the second embodiment of the present invention;
FIG. 1B is a sectional view taken along line BB in FIG.
FIG. 1C is a cross-sectional view along the line CC in FIG.

FIG. 12 is a circuit diagram of an electronic device substrate according to a second embodiment of the present invention.

FIG. 13 is a sectional view of a high withstand voltage semiconductor device according to a third embodiment of the present invention.

FIG. 14 is a sectional view of a high withstand voltage semiconductor device according to a modification of the third embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Stage, 2, 2E, 2G ... Probe, 3 ... Probe holding stand, 4 ... Electric property measuring instrument, 5 ... Mounting part, 6 ... High voltage semiconductor chip, 6-1-6-4 ... IGBT chip, 6 -5, 6-6: FWD chip, 7: mounting portion, 8: silicone rubber, 9: terminal portion, 10: fitting portion, 11: pressing portion, 12: silicon wafer, 13C: collector electrode, 13E: emitter Electrode, 13G: Gate electrode, 13K: Cathode electrode, 13A: Anode electrode, 14: Side surface portion, 15: Spark path, 21: DBC substrate, 22: Insulating substrate, 23C: Collector wiring layer, 23E: Emitter wiring layer, 23G -1, 23G-2: gate wiring layer, 24: copper layer, 25: solder layer, 26C: bonding wire for collector, 26E: bonding wire for emitter, 26A: anode Connecting wires, 27C, 27E, 27G-1, 27G-2: connecting portions of external electrodes, 28: silicone rubber, 29C, 29E, 29G-1, 29G-1: probe, 30: electronic device substrate, 31: copper base , 32: solder layer, 33C, 33E, 33G: external electrode, 34: frame, 35C, 35E, 35G: external terminal, 36: lid, 37: IGBT product, 41: pressure contact plate, 42: screw, 43 ... Heat sink, 44 ... case.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshinari Uetake 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Microelectronics Center Co., Ltd. (72) Inventor Takao Sakamoto Komukai, Saiyuki-ku, Kawasaki-shi No. 1, Toshiba-cho, Toshiba Microelectronics Center (72) Inventor Naoyuki Inoue No. 1, Komukai Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa F-Terminal, Toshiba Microelectronics Center, Inc. AG03 AG12 AH05 4M106 AA02 BA01 BA14 DD01 DJ01

Claims (6)

[Claims] A step of pressing an insulator having elasticity against an end portion of a bare high-voltage semiconductor chip; and a step of applying a high voltage while the insulator having elasticity is pressed. Applying a voltage to the high withstand voltage semiconductor chip; and evaluating a characteristic of the high withstand voltage semiconductor chip in a state in which the elastic insulator is pressed and the high voltage is applied. A method for evaluating a high withstand voltage semiconductor chip, comprising: 2. A high-voltage semiconductor chip in a bare state, a substrate on which the high-voltage semiconductor chip in the bare state is mounted, and to which the high-voltage semiconductor chip is electrically connected; At least a region to which external terminals are connected is exposed on the substrate on which the chip is mounted, and a region to which a high voltage is applied including a surface of the bare high-voltage semiconductor chip is coated. A high-breakdown-voltage electronic device substrate, comprising: an insulating material; 3. The high-voltage electronic device substrate according to claim 2, wherein the insulator is a silicone resin. 4. A step of mounting and electrically connecting a bare high-voltage semiconductor chip to a substrate, wherein at least an external terminal of the substrate on which the bare high-voltage semiconductor chip is mounted is connected. Forming a resilient insulator by injection molding, which exposes a region to be applied and covers a region to which a high voltage is applied including the surface of the bare high voltage semiconductor chip. A method for manufacturing an electronic device substrate, comprising: 5. A high-voltage semiconductor chip in a bare state, a substrate on which the high-voltage semiconductor chip in the bare state is mounted and to which the high-voltage semiconductor chip is electrically connected, and a high-voltage semiconductor chip in the bare state. At least a region to which external terminals are connected is exposed on the substrate on which the chip is mounted, and a region to which a high voltage is applied including a surface of the bare high-voltage semiconductor chip is coated. A high-pressure electronic device substrate including the above-described insulator, a heat radiator, and a press-contact member that presses the resilient insulator to press the high-voltage electronic device substrate against the heat radiator. High breakdown voltage semiconductor device. 6. The high breakdown voltage semiconductor device according to claim 5, wherein the insulator is a silicone resin.