JP6479207B2 - Power semiconductor module with improved bonding connection structure - Google Patents

Power semiconductor module with improved bonding connection structure Download PDF

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Publication number
JP6479207B2
JP6479207B2 JP2017548171A JP2017548171A JP6479207B2 JP 6479207 B2 JP6479207 B2 JP 6479207B2 JP 2017548171 A JP2017548171 A JP 2017548171A JP 2017548171 A JP2017548171 A JP 2017548171A JP 6479207 B2 JP6479207 B2 JP 6479207B2
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bonding
power semiconductor
semiconductor module
group
leg
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JP2018508126A (en
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ペルマー ライムント
ペルマー ライムント
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Infineon Technologies Bipolar GmbH and Co KG
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Infineon Technologies Bipolar GmbH and Co KG
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Description

本発明はパワー半導体モジュールに関する。パワー半導体モジュールは、パワーエレクトロニクス回路に使用される半導体アセンブリである。パワー半導体モジュールは、通常はインバータや整流器のように車両用途および産業用途に使用されている。パワー半導体モジュールに含まれている半導体コンポーネントは、通常は、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）半導体チップまたはＭＯＳＦＥＴ（金属酸化膜半導体電界効果トランジスタ）半導体チップである。ＩＧＢＴおよびＭＯＳＦＥＴの半導体チップは、様々な公称電圧および電力を有する。いくつかのパワー半導体モジュールは、過電圧保護のために半導体パッケージ内に付加的な半導体ダイオード（すなわちフリーホイールダイオード）も有する。   The present invention relates to a power semiconductor module. A power semiconductor module is a semiconductor assembly used in power electronics circuits. Power semiconductor modules are usually used for vehicle and industrial applications such as inverters and rectifiers. The semiconductor component contained in the power semiconductor module is usually an IGBT (insulated gate bipolar transistor) semiconductor chip or a MOSFET (metal oxide semiconductor field effect transistor) semiconductor chip. IGBT and MOSFET semiconductor chips have various nominal voltages and powers. Some power semiconductor modules also have an additional semiconductor diode (ie freewheeling diode) in the semiconductor package for overvoltage protection.

より高出力な用途に対しては、パワー半導体モジュールは、通常は、個々の基板上に１つ以上のパワー半導体構成素子（以下では単にパワー半導体とも称する）を有している。基板は、通常は、パワー半導体モジュールを電気的に絶縁するために、Ａｌ２Ｏ３、ＡｌＮ、Ｓｉ３Ｎ４またはその他の好適な材料などのような少なくとも１つの絶縁セラミック基板を有している。基板は、通常、金属ベースプレートに被着されており、この金属ベースプレートは、ヒートシンクへのモジュールの機械的固定および熱的結合のための安定化された支持体として用いられる。少なくともセラミック基板の上面は、一方ではその上に配置されかつ規則的にはんだ付けされたパワー半導体を接触接続させ、他方では電気的な電位面、特に負荷電位面を提供するために、純粋なまたはめっきされたＣｕ、Ａｌまたはその他の好適な材料によって金属被覆されている。これらの電位面は、一方では、パワー半導体とのいわゆるボンディング接続部を介した電流供給または引き出しに用いられ、他方では、モジュールへのもしくはモジュールからの、特にそのハウジングからの電流供給または引き出しに用いられる端子部品との機械的固定および電気的接続に用いられ、例えば、端子部品を、ハウジング外部の外部導体と、例えばねじ込み式接続を介して接続させるために用いられる。電位面のために設けられた金属層は、通常は、共晶銅接合法（ＤＣＢ）、共晶アルミニウム接合法（ＤＡＢ）または活性金属硬ろう付け法（ＡＭＢ）を用いてセラミック基板にボンディングされる。 For higher power applications, power semiconductor modules typically have one or more power semiconductor components (hereinafter also simply referred to as power semiconductors) on individual substrates. The substrate typically has at least one insulating ceramic substrate, such as Al 2 O 3 , AlN, Si 3 N 4 or other suitable material, to electrically insulate the power semiconductor module. . The substrate is usually attached to a metal base plate, which is used as a stabilized support for mechanical fixation and thermal coupling of the module to a heat sink. At least the top surface of the ceramic substrate is purely or in order to contact, on the one hand, power semiconductors arranged on it and regularly soldered, and on the other hand to provide an electrical potential surface, in particular a load potential surface. Metallized with plated Cu, Al or other suitable material. These potential planes are used on the one hand for current supply or extraction via so-called bonding connections with power semiconductors, and on the other hand for current supply or extraction to or from the module, in particular from its housing. For example, it is used for connecting the terminal component to an external conductor outside the housing, for example, via a screw-in connection. The metal layer provided for the potential surface is usually bonded to the ceramic substrate using eutectic copper bonding (DCB), eutectic aluminum bonding (DAB) or active metal brazing (AMB). The

電位面を、関連するパワー半導体の基板とは反対側の少なくとも１つの端子面と電気的に接続するために、ボンディングワイヤの形態のボンディング接続部（ワイヤボンディング接続部とも称する）かまたはボンディングストリップ部（ボンディングストリップ接続部とも称する）が規則的に設けられており、これらは電位面と半導体の端子面との間の導電的な接触接続を形成している。パワーエレクトロニクスの分野では、純粋なアルミニウム（９９．９９％以上のＡｌ含有量）および銅材料がボンディング接続部のために使用される。一方ではボンディング接続部と端子面との間、他方ではボンディング接続部と電位面との間の接続を形成するための方法の様々な変化形態には、サーモコンプレッションボンディング法（略してＴＣ−ボンディング）、サーモソニック−ボール−ウェッジボンディング法（ＴＳ−ボンディング）、ウルトラソニック−ウェッジ−ウェッジボンディング法（ＵＳボンディング）がある。この場合、一方ではボンディング接続部と端子面との間、他方ではボンディング接続部と端子電位面との間でそれぞれ形成された接触接続領域はボンディング脚部と称する。   A bonding connection in the form of a bonding wire (also referred to as a wire bonding connection) or a bonding strip for electrically connecting the potential surface with at least one terminal surface opposite to the associated power semiconductor substrate (Also referred to as bonding strip connections) are regularly provided, which form a conductive contact connection between the potential plane and the semiconductor terminal plane. In the field of power electronics, pure aluminum (99.99% Al content or more) and copper materials are used for bonding connections. Various variations of the method for forming the connection between the bonding connection and the terminal surface on the one hand and between the bonding connection and the potential surface on the other include the thermo compression bonding method (TC-bonding for short). , Thermosonic-ball-wedge bonding method (TS-bonding), and ultrasonic-wedge-wedge bonding method (US bonding). In this case, the contact connection region formed between the bonding connection portion and the terminal surface on the one hand and between the bonding connection portion and the terminal potential surface on the other hand is referred to as a bonding leg portion.

この種のパワー半導体モジュールと、その構造化に求められるパワー半導体構成素子への要求およびそれに伴う性能は、近年において恒常的に高まっている。例えば、半導体構成素子の単位面積当たりの電流強度は増加している。さらに経済的な必要性から、半導体素子は、その電力限界にますます近づけて動作されている。   In recent years, this type of power semiconductor module and the demands on the power semiconductor components required for structuring and the accompanying performance have been constantly increasing. For example, the current intensity per unit area of the semiconductor component is increasing. In addition, due to economic needs, semiconductor devices are being operated closer to their power limits.

パワー半導体モジュールまたはパワー半導体構成素子の性能に対する決定的な外的要因は、熱放出ならびに電流供給および引き出しである。パワー半導体構成素子の電流供給および引き出しに関する従来技術には、例えばワイヤボンディング接続部またはボンディングストリップ接続部として様々な態様のボンディング接続部がある。電流負荷の高いパワー半導体では、１００μｍ〜５００μｍの直径の太線かまたは太いワイヤストリップが使用される。それらの断面が十分でない場合には、複数の平行なボンディング接続部が規則的に設けられる。本発明の対象は、この種のボンディング接続部の性能にある。   Critical external factors for the performance of a power semiconductor module or power semiconductor component are heat dissipation and current supply and extraction. In the prior art relating to current supply and extraction of power semiconductor components, there are various types of bonding connections such as wire bonding connections or bonding strip connections. For power semiconductors with a high current load, thick or thick wire strips with a diameter of 100 μm to 500 μm are used. If their cross-section is not sufficient, a plurality of parallel bonding connections are regularly provided. The subject of the present invention is the performance of this type of bonding connection.

パワー半導体構成素子のためのワイヤボンディング接続部は、例えば独国特許出願公開第１９５４９０１１号明細書（ＤＥ１９５４９０１１Ａ１）から公知である。そこに紹介されているそれらのパワー半導体モジュールでは、パワー半導体構成素子が、はんだ接続を用いて基板上に配置される。このパワー半導体素子の第２の主表面のはんだ接続部は、電流供給および引き出しの一部を表している。さらなる電流端子は、パワー半導体素子の第１の主表面の端子面を提供する金属化部と、負荷電位面と、の間のワイヤボンディング接続部を用いて形成される。公知のワイヤボンディング接続部に対する特徴は、ボンディングワイヤが相互に密接して配置されていること、および個々のボンディングワイヤのボンディング脚部が、特にパワー半導体構成素子に関して、一列にまたはわずかにオフセットされて配置されていることにある。   Wire bonding connections for power semiconductor components are known, for example, from DE 19549011 (DE19549011A1). In those power semiconductor modules introduced therein, the power semiconductor components are placed on the substrate using solder connections. The solder connection portion on the second main surface of the power semiconductor element represents a part of current supply and extraction. The further current terminal is formed using a wire bonding connection between the metallization that provides the terminal surface of the first main surface of the power semiconductor element and the load potential surface. A characteristic for known wire bonding connections is that the bonding wires are placed in close proximity to each other and that the bonding legs of the individual bonding wires are in line or slightly offset, especially with respect to power semiconductor components. It is to be arranged.

従来技術によれば、パワー半導体構成素子は、電流供給のために隣接して配置された個別のボンディングワイヤだけを用いて接触接続されるのでなく、ボンディングワイヤの方向で少なくとも部分的に上下に位置する２つ以上のボンディングワイヤを用いて頻繁に接触接続される。個別のボンディングワイヤは、パワー半導体構成素子上の電流分布の改善のためにも、その端子面と複数のボンディング脚部を用いて頻繁に接触接続する。   According to the prior art, the power semiconductor components are not contact-connected using only individual bonding wires arranged adjacent to supply current, but rather at least partly up and down in the direction of the bonding wires. The contact connection is frequently made using two or more bonding wires. Individual bonding wires are frequently contact-connected using their terminal surfaces and a plurality of bonding legs to improve the current distribution on the power semiconductor component.

シミュレーションでは、負荷端子電位面とパワー半導体構成素子との間のボンディングワイヤの従来技術による配置構成の場合、電流が、端子面を介してパワー半導体構成素子内に不均一に給電され、それによってパワー半導体構成素子がその全面において電流導通のために均等に負荷されないことが示されている。   In the simulation, in the case of a prior art arrangement of the bonding wires between the load terminal potential plane and the power semiconductor component, current is fed non-uniformly into the power semiconductor component via the terminal plane and thereby the power It has been shown that the semiconductor component is not equally loaded for current conduction across its entire surface.

独国特許出願公開第１０２０４１５７号明細書（ＤＥ１０２０４１５７Ａ１）には、導体路とパワー半導体構成素子との導電接続のためのワイヤボンディング接続部が開示されており、ここでは、全てのボンディングワイヤの間隔またはボンディングワイヤの個々のグループ内での間隔が可変であり、それによってボンディングワイヤの延在方向に垂直な方向での電流給電が従来技術に比べてより均一に構成されている。   German Offenlegungsschrift 10 204 157 (DE 10204157 A1) discloses a wire bonding connection for conductive connection between a conductor track and a power semiconductor component, where all bonding wire spacings or The spacing between individual groups of bonding wires is variable, so that the current feeding in the direction perpendicular to the direction in which the bonding wires extend is made more uniform than in the prior art.

独国特許第１０２００５０３９９４０号明細書（ＤＥ１０２００５０３９９４０Ｂ４）は、複数のボンディング接続部の第２のボンディング脚部が端子面全体にわたってチェス盤状に交互に分散され、これらのボンディング接続部が複数のボンディング接続部からなる２つのグループを形成するワイヤボンディング接続部を開示しており、ここでは、これらのグループは、ボンディング接続部の長さが異なっており、さらにそれらの第２のボンディング脚部は、端子面上で共通のセグメントまたは共通の領域を画定していない。   German Patent No. 102005039940 (DE102005039940B4) discloses that second bonding legs of a plurality of bonding connections are alternately distributed in a chessboard shape over the entire terminal surface, and these bonding connections are a plurality of bonding connections. Wire bonding connections are disclosed which form two groups of: wherein the groups have different lengths of bonding connections, and their second bonding legs are terminal surfaces Does not define a common segment or common area above.

ワイヤボンディング接続部のこの態様における欠点は、この場合この種の複雑なトポロジーを有意に使用できるようにするためには、パワー半導体構成素子の十分に大きな端子面が使用可能でなければならないことである。   The disadvantage of this aspect of the wire bonding connection is that a sufficiently large terminal surface of the power semiconductor component must be available in this case in order to be able to use this kind of complex topology significantly. is there.

特に、ダイオードおよびサイリスタを有するパワー半導体モジュールの場合、とりわけ、このパワー半導体構成素子のサージ電流負荷を考慮しなければならない。これらの電流サージは、１／１０秒単位の短期間のうちに、パワー半導体構成素子の連続負荷を何度も上回る。この場合、連続動作用に設計されたボンディング接続部の態様は、必ずしも有利ではないことが判明している。   In particular, in the case of a power semiconductor module with a diode and a thyristor, the surge current load of this power semiconductor component must be taken into account. These current surges exceed the continuous load of the power semiconductor component many times in a short period of 1/10 second. In this case, it has been found that the aspect of the bonding connection designed for continuous operation is not necessarily advantageous.

本発明が基礎とする課題は、ボンディング接続部の最大通電容量が、全体として、特にサージ電流負荷の場合において改善され、特に電流分布とひいては個々のボンディング接続部を介した熱分布とがさらに補償される、パワー半導体モジュール用のボンディング接続部を提供することにある。この課題は本発明により、請求項１に記載の特徴を有するパワー半導体モジュールによって解決される。さらに、本発明の特に好ましい態様は、従属請求項に開示されている。特許請求の範囲に個別に記載された特徴は、任意に技術的に有意な方法で相互に組み合わせ可能であり、それらは本発明のさらなる態様を示していることを指摘しておく。この説明は、特に図面との関連において、本発明を付加的に特徴付け、特定するものである。   The problem on which the present invention is based is that the maximum current carrying capacity of the bonding connection is improved as a whole, especially in the case of surge current loads, in particular the current distribution and thus the heat distribution through the individual bonding connections is further compensated. Another object of the present invention is to provide a bonding connection for a power semiconductor module. This object is achieved according to the invention by a power semiconductor module having the features of claim 1. Furthermore, particularly preferred embodiments of the invention are disclosed in the dependent claims. It is pointed out that the features individually recited in the claims can be combined with one another in any technically significant way, and they represent further aspects of the invention. This description additionally characterizes and identifies the invention, particularly in conjunction with the drawings.

本発明によるパワー半導体モジュールは、基板、好ましくは電気的に絶縁された基板を有している。例えばこの基板は、Ａｌ２Ｏ３、ＡｌＮ、Ｓｉ３Ｎ４などのようなセラミック基板である。この基板は、好ましくは、金属ベースプレート上に配置され、この場合このベースプレートは、ヒートシンクへの配置と、場合によっては固定のために構成されている。 The power semiconductor module according to the invention has a substrate, preferably an electrically insulated substrate. For example, the substrate is a ceramic substrate such as Al 2 O 3 , AlN, Si 3 N 4 or the like. The substrate is preferably placed on a metal base plate, where the base plate is configured for placement on a heat sink and possibly fixation.

本発明によれば、さらに、少なくとも１つのパワー半導体が設けられている。ここで考察されるパワー半導体は、例えば、パワーダイオードのような制御されていない構成素子か、またはパワーサイリスタもしくは例えばバイポーラトランジスタなどのパワートランジスタのような制御された構成素子でもある。これらの制御された構成素子は、その駆動制御のために、一般的にその第１の主表面上に設けられた金属化部によって提供される少なくとも１つのさらなる端子面を有しており、このさらなる端子面は、導通する負荷電流から電気的に分離され、さらに従来技術により、ボンディング接続部を用いて、基板の制御電位表面にも接続されている。この制御端子間のボンディング接続部は、本発明の対象ではない。   According to the invention, at least one power semiconductor is further provided. The power semiconductors considered here are either uncontrolled components such as, for example, power diodes, or controlled components such as power thyristors or power transistors such as, for example, bipolar transistors. These controlled components have at least one further terminal surface, generally provided by a metallization provided on their first main surface, for their drive control, The further terminal surface is electrically isolated from the conducting load current and is also connected to the control potential surface of the substrate using bonding connections according to the prior art. This bonding connection between the control terminals is not the subject of the present invention.

本発明によれば、パワー半導体は、基板とは反対側の自身の側に端子面を有している。この端子面は、連続的な金属化部として形成することができ、あるいは、例えば、ＩＧＢＴのエミッタ端子面の場合のように、セグメント化されていてもよい。   According to the present invention, the power semiconductor has a terminal surface on its own side opposite to the substrate. This terminal surface can be formed as a continuous metallization, or it may be segmented, as in the case of an IGBT emitter terminal surface, for example.

本発明によれば、さらに、基板上でパワー半導体に隣接して配置され、場合によってはセグメント化された負荷電位面が設けられている。   In accordance with the present invention, there is further provided a load potential surface which is arranged adjacent to the power semiconductor on the substrate and possibly segmented.

本発明によれば、さらに、端子面を、負荷電位面に平行かつ導電的に接続させるための複数のボンディング接続部が設けられている。本発明によれば、複数のボンディング接続部の各々は、少なくとも１つの第１のタイプのボンディング脚部、略して第１のボンディング脚部を有しており、この場合、第１のボンディング脚部は、それが少なくとも１つの負荷電位面上に配置されていることによって特徴付けられている。さらに、複数のボンディング接続部の各々は、本発明によれば、複数の第２のボンディング脚部を有しており、この場合は、それらがパワー半導体の端子面上に配置されている。本発明によれば、各ボンディング接続部は、端子面上に少なくとも１つの終端部を有しており、好ましくは１つの終端部は負荷電位面上に設けられ、１つの終端部は端子面上に設けられ、さらに好ましくは、ボンディング接続部は、それらの終端部において、それぞれボンディング脚部を用いて終端している。   According to the present invention, a plurality of bonding connections for connecting the terminal surface in parallel and conductively to the load potential surface are further provided. According to the invention, each of the plurality of bonding connections has at least one first type of bonding leg, abbreviated first bonding leg, in which case the first bonding leg. Is characterized by being arranged on at least one load potential plane. Furthermore, each of the plurality of bonding connections has a plurality of second bonding legs according to the invention, in which case they are arranged on the terminal surface of the power semiconductor. According to the present invention, each bonding connection has at least one terminal end on the terminal surface, preferably one terminal end is provided on the load potential surface, and one terminal end is on the terminal surface. More preferably, the bonding connection portions are terminated at their end portions by using bonding leg portions, respectively.

本発明によれば、複数のボンディング接続部は、同じ数のボンディング脚部を有する複数のボンディング接続部からなる少なくとも２つのグループに配列されている。本発明によれば、１つのグループの各ボンディング接続部の第２のボンディング脚部は、専ら、端子面の部分面によって画定される、当該端子面のセグメントまたは領域に配置されている。換言すれば、異なるグループのセグメントまたは領域は、相互に空間的に分離されて配置されているか、または第２のボンディング脚部に関して表現すれば、本発明によれば、グループの第２のボンディング脚部の空間的に交差する配置構成は設けられていない。好ましくは、グループの各ボンディング接続部の第２のボンディング脚部は、専ら、端子面の厳密に１つの共通の部分面に配置されている。好ましくはこの部分面は、それ自体閉じられている。好ましくは、グループごとに、１５〜５０のボンディング接続部が設けられており、さらに好ましくは、１６〜３０のボンディング接続部が設けられている。   According to the present invention, the plurality of bonding connections are arranged in at least two groups of bonding connections having the same number of bonding legs. According to the invention, the second bonding leg of each bonding connection of a group is arranged exclusively in a segment or region of the terminal surface defined by a partial surface of the terminal surface. In other words, the different groups of segments or regions are arranged spatially separated from each other or expressed in terms of the second bonding leg, according to the invention, the second bonding leg of the group. There is no provision for spatially intersecting parts. Preferably, the second bonding leg of each bonding connection of the group is exclusively arranged on exactly one common partial surface of the terminal surface. Preferably this partial surface is itself closed. Preferably, 15 to 50 bonding connections are provided for each group, and more preferably 16 to 30 bonding connections are provided.

本発明によれば、グループは、当該グループの第１のボンディング脚部が、負荷電位面上で、パワー半導体から、異なった間隔ではあるが、ただし各グループ内では一致している間隔をおいて配置されていることに関して異なっている。本発明による、グループに所属するボンディング接続部の他に、さらなるボンディング接続部が設けられていてもよい。これらのさらなるボンディング接続部は、例えば、制御電位面を、制御されたパワー半導体の所属の制御端子面に電気的に接続させるために設けられている。   In accordance with the present invention, the group has a first bonding leg of the group at a different distance from the power semiconductor on the load potential plane, but with a matching distance within each group. Different with respect to being arranged. In addition to the bonding connections belonging to the group according to the invention, further bonding connections may be provided. These further bonding connections are provided, for example, to electrically connect the control potential surface to the control terminal surface to which the controlled power semiconductor belongs.

本発明の基本的な考察は、負荷電流を導通させるパワー半導体の端子面上の電流密度を、従来技術に比べてより均一にさせることにある。本発明による実施形態によれば、グループごとの電流供給および引き出しがパワー半導体の端子面の１つの領域に限定され、特に均一な負荷電流分布と、ひいてはオーミック熱損失の分布とが、ボンディング接続部を介して達成されることが示された。   The basic consideration of the present invention is to make the current density on the terminal surface of a power semiconductor that conducts a load current more uniform than in the prior art. According to an embodiment according to the invention, the current supply and withdrawal per group is limited to one region of the terminal surface of the power semiconductor, in particular the uniform load current distribution and thus the ohmic heat loss distribution It has been shown to be achieved through

本発明に従って、負荷電位面からパワー半導体構成素子の接触接続面もしくは金属化部まで改善構成されるボンディング接続部は、複数の個別のボンディングワイヤまたはボンディングストリップも有しており、これらのボンディングワイヤまたはボンディングストリップは、自身の側で、複数の第２のボンディング脚部を、パワー半導体構成素子の金属化部上に有している。これらの第２のボンディング脚部は、任意に配置されていてもよい。ここでは関連するするセグメントまたは領域内への第２の脚部の規則的な配置構成が好ましい。例えば、関連するグループに所属する第２の脚部の配置構成がチェス盤状であるならば、この場合の第２のボンディング脚部は、ここでは同じ「色」のフィールド上にのみ配置され、すなわち列ごとにずらされて配置される。平行な同一列の配置構成は好ましく、この場合は次に隣接する第２の脚部の間の間隔は両方向で維持される。   In accordance with the present invention, a bonding connection that is configured to improve from a load potential surface to a contact connection surface or metallization of a power semiconductor component also includes a plurality of individual bonding wires or bonding strips. The bonding strip has on its side a plurality of second bonding legs on the metallization of the power semiconductor component. These second bonding legs may be arbitrarily arranged. Here, a regular arrangement of the second legs within the relevant segment or region is preferred. For example, if the arrangement of the second legs belonging to the related group is chessboard-like, the second bonding legs in this case are arranged only on the same “color” field here, That is, they are arranged shifted for each column. A parallel parallel arrangement is preferred, in which case the spacing between the next adjacent second legs is maintained in both directions.

ボンディング接続部は、好ましくは、ボンディング接続部の温度に起因する膨張の際の機械的な引っ張り負荷および／または圧力負荷ができるだけわずかしかかからないようにするために、ボンディング脚部の間が湾曲形状に形成される。   The bonding connections are preferably curved between the bonding legs in order to minimize the mechanical tensile and / or pressure loads during expansion due to the temperature of the bonding connections. It is formed.

好ましい実施形態によれば、１つのグループのボンディング接続部は長さが異ならない。さらに好ましくは、１つのグループのボンディング接続部は全て同じ長さを有する。   According to a preferred embodiment, a group of bonding connections is not different in length. More preferably, all the bonding connections of one group have the same length.

好ましい実施形態によれば、グループに所属するボンディング接続部の材料は、アルミニウムまたは銅を含む。例えば、ボンディング接続部は、９９．９９％以上の純度を有する高純度アルミニウムまたは高純度銅からなる。代替的に、ボンディング接続部は、例えばアルミニウム合金または銅合金からなり、この場合は合金化添加剤として、マグネシウム、シリコン、銀などが、例えばボンディング接続部の熱伝導特性または導電性特性もしくは機械的特性を改善する添加剤として設けられる。好ましくはボンディング接続部は、ボンディングワイヤである。例えば、ボンディングワイヤは、丸い断面を有する。好ましくは、断面直径は、１００μｍ〜８００μｍの範囲、より好ましくは１２５μｍ〜５００μｍの範囲にあり、例えば３００μｍである。   According to a preferred embodiment, the material of the bonding connection belonging to the group comprises aluminum or copper. For example, the bonding connection portion is made of high-purity aluminum or high-purity copper having a purity of 99.99% or higher. Alternatively, the bonding connection is made of, for example, an aluminum alloy or a copper alloy, in which case magnesium, silicon, silver, etc. are used as the alloying additive, for example, the thermal or conductive properties or mechanical properties of the bonding connection. Provided as an additive to improve properties. Preferably, the bonding connection is a bonding wire. For example, the bonding wire has a round cross section. Preferably, the cross-sectional diameter is in the range of 100 μm to 800 μm, more preferably in the range of 125 μm to 500 μm, for example 300 μm.

好ましい実施形態によれば、１つのグループのボンディング接続部は、それぞれ１つの第３のボンディング脚部を有し、該第３のボンディング脚部は、第１と第２のボンディング脚部の間のボンディング接続部の延在部において、負荷電位面から絶縁されて配置された基板の金属化部上に配置されることが想定される。本発明の趣旨における絶縁配置は、それ自体が金属化に関するものであり、したがってボンディング接続部によって形成される電気的接続に矛盾するものではない。換言すれば、この態様では、金属化部は、専ら、少なくとも１つのボンディング接続部を介して負荷電位面に電気的に接続される。付加的なボンディング脚部によって生じる付加的な湾曲状の案内に基づき、関連するボンディング接続部の延長が生じる。このことは、それらのボンディング接続部の長さに関して異なるグループを補償することが可能な手段を提供する。ここでの付加的なボンディング脚部は、この場合絶縁された金属化部上への配置構成に基づき、本発明の基本的考察の趣旨における電流分布にマイナスの影響を与えることなく、ボンディング接続部の付加的な機械的安定化をもたらす。好ましくは、グループの第３のボンディング脚部は、基板の共通の金属化部上に配置され、基板との接続によって、とりわけ有利な冷却が生じる。例えば、それらは、パワー半導体の１つの縁部に平行かつ縁部から離間して延在する仮想線に沿って配置される。   According to a preferred embodiment, one group of bonding connections each has one third bonding leg, the third bonding leg between the first and second bonding legs. In the extension part of the bonding connection part, it is assumed that it is arranged on the metallization part of the substrate arranged insulated from the load potential surface. The insulating arrangement within the meaning of the present invention per se relates to metallization and is therefore not inconsistent with the electrical connection formed by the bonding connection. In other words, in this aspect, the metallization part is electrically connected exclusively to the load potential surface via at least one bonding connection. Based on the additional curved guidance produced by the additional bonding legs, an extension of the associated bonding connection occurs. This provides a means by which different groups can be compensated for the length of their bonding connections. The additional bonding legs here are based on the arrangement on the insulated metallization in this case, without any negative influence on the current distribution for the purpose of the basic considerations of the invention. Provides additional mechanical stabilization. Preferably, the third bonding leg of the group is arranged on a common metallization of the substrate, and the connection with the substrate results in particularly advantageous cooling. For example, they are arranged along a virtual line extending parallel to and spaced from one edge of the power semiconductor.

本発明の趣旨における「セグメント」との概念は、互いに電気的に絶縁されて配置されている領域を意味する。例えばここでは、その電気的な絶縁が基板上への配置から生じる金属化部があげられるが、ただしその他の電気的な接続も除外されない。導電接続は、例えば１態様では、負荷端子部品を介して形成され、これにより、セグメントへの共通の負荷電流供給の機能またはセグメントからの共通の負荷電流引き出しの機能が作用する。例えば、セグメントは、パワー半導体の対向する縁部に対して平行かつ離間されて配置されている。外部からの導体路端部との電気的および機械的接続に用いられ、場合によってはパワー半導体モジュールのハウジングからの電気的接続線の引き出しに用いられる負荷端子部品は、例えば鏡面対称に構成されたブラケットとして構成されている。   The concept of “segment” in the meaning of the present invention means a region that is electrically insulated from each other. For example, here is a metallization whose electrical insulation results from its placement on the substrate, but other electrical connections are not excluded. For example, in one aspect, the conductive connection is formed via a load terminal component, which acts as a common load current supply to the segment or a common load current draw from the segment. For example, the segments are arranged parallel to and spaced from opposite edges of the power semiconductor. The load terminal component used for electrical and mechanical connection with the end of the conductor path from the outside, and in some cases used for drawing out the electrical connection line from the housing of the power semiconductor module, is configured to be mirror-symmetric, for example. It is configured as a bracket.

したがって、例えば、本発明によるパワー半導体モジュールは、対称的なブラケットとして構成され、そのブラケット端部が負荷電位面の２つのセグメントと接触接続する、好ましくははんだ付けを介して接触接続する少なくとも１つの端子部品を含む。例えばこのブラケットは、金型部品であり、好ましくは、銅または銅合金からなる金型部品である。   Thus, for example, the power semiconductor module according to the invention is configured as a symmetrical bracket, at least one of which is connected in contact with the two segments of the load potential surface, preferably via soldering, with the bracket ends being in contact connection Including terminal parts. For example, the bracket is a mold part, preferably a mold part made of copper or a copper alloy.

好ましい実施形態によれば、グループのボンディング接続部は、それらの配置構成に関して鏡面対称性が生じるように配置される。その際には、本発明によるグループに所属するボンディング接続部の他に、この対称性の影響を受けない、例えばパワー半導体の制御端子と所属の制御電位面との接続に用いられるような、ボンディング接続部も想定可能であることは排除されるべきではない。   According to a preferred embodiment, the bonding connections of the groups are arranged such that mirror symmetry occurs with respect to their arrangement. In this case, in addition to the bonding connection part belonging to the group according to the present invention, the bonding which is not affected by this symmetry, for example, used for connection between the control terminal of the power semiconductor and the control potential surface to which it belongs. It should not be excluded that connections can be envisaged.

好ましい態様によれば、少なくとも２つのグループは、ボンディング接続部ごとに第２のボンディング脚部の数が異なっている。例えば、１つのグループは、ボンディング接続部ごとに２つの第２のボンディング脚部を有し、別のグループは、ボンディング接続部ごとに３つの第２のボンディング脚部を有する。   According to a preferred embodiment, at least two groups differ in the number of second bonding legs for each bonding connection. For example, one group has two second bonding legs for each bonding connection and another group has three second bonding legs for each bonding connection.

好ましい態様によれば、所属の負荷電位面もしくは所属の負荷電位面セグメントと、所属の接触接続面領域もしくは接触接続面セグメントと、の間で、所属のボンディング接続部によって橋絡すべき間隔が最大であるグループは、ボンディング接続部ごとに最小数の第２のボンディング脚部を有することが想定される。   According to a preferred embodiment, the maximum distance between the associated load potential plane or the associated load potential plane segment and the associated contact connection area or the contact connection plane segment is to be bridged by the associated bonding connection. Is assumed to have a minimum number of second bonding legs per bonding connection.

好ましい態様によれば、パワー半導体は、８ｍｍ〜５０ｍｍの範囲、好ましくは９ｍｍ〜２５ｍｍの範囲、より好ましくは１０ｍｍ〜２０ｍｍの範囲の最低縁部長を有している。   According to a preferred embodiment, the power semiconductor has a minimum edge length in the range of 8 mm to 50 mm, preferably in the range of 9 mm to 25 mm, more preferably in the range of 10 mm to 20 mm.

好ましくは、パワー半導体モジュールは、さらにハウジング、例えばプラスチックからなるハウジング、好ましくは繊維強化型熱可塑性プラスチックのような繊維強化されたプラスチックからなるハウジングを含む。好ましくはこのハウジングは、スリーブハウジングとして構成されている。   Preferably, the power semiconductor module further comprises a housing, for example a housing made of plastic, preferably a housing made of fiber reinforced plastic such as a fiber reinforced thermoplastic. Preferably this housing is configured as a sleeve housing.

好ましい態様によれば、本発明によるパワー半導体モジュールは、厳密に２つのパワー半導体または２の倍数に相応する数のパワー半導体を含んでいる。例えば、パワー半導体の数に対応する数の基板が設けられている。第１のパワー半導体のボンディング接続部は、それぞれ同じ数のボンディング脚部を有する複数のボンディング接続部からなる２つのグループに配列され、１つのグループの各ボンディング接続部の第２のボンディング脚部は、専ら、端子面の部分面によって画定される、当該端子面のセグメントまたは領域に配置されている。第１のパワー半導体のグループは、当該グループの第１のボンディング脚部が、第１のパワー半導体の負荷電位面の２つのセグメントの別のセグメント上に配置され、さらにそれぞれ第１のパワー半導体の径方向に対向する２つの縁部に隣接して配置されていることに関して異なっている。第２のパワー半導体のボンディング接続部に接続される厳密に１つの、第２のパワー半導体の負荷電位面は、第１および第２のパワー半導体の間で、第２のパワー半導体の１つの縁部と、第１のパワー半導体の残りの縁部のうちの１つと、に隣接して配置されている。１実施形態によれば、第２のパワー半導体の負荷電位面は、基板の金属化部によって形成されており、この金属化部は、同時に第１のパワー半導体との接触接続を形成し、かつ／または第２のパワー半導体に所属するさらなる負荷電位面を形成する。これにより、所属の負荷電位面を含めたパワー半導体の省スペース的な配置構成を、均一な電流分布と同時に達成することが可能になる。特に、それによって負荷電位面もしくはそのセグメントの対称的な配置構成が可能となる。このことは、例えば、本発明によるパワー半導体モジュールに所属するハウジングの外部に配置されている外部導体路とのさらなる接続のために、定期的に使用される端子部品も、例えばブラケット形状で、対称的に設計することが可能になるという利点を有する。このことは、特に均一な電流分布だけでなく、本発明によるモジュールの簡単な製造ももたらす。   According to a preferred embodiment, the power semiconductor module according to the invention comprises exactly two power semiconductors or a number of power semiconductors corresponding to a multiple of two. For example, the number of substrates corresponding to the number of power semiconductors is provided. The first power semiconductor bonding connections are arranged in two groups of bonding connections each having the same number of bonding legs, and the second bonding legs of each bonding connection in one group are: , Exclusively located in a segment or region of the terminal surface defined by a partial surface of the terminal surface. In the first power semiconductor group, the first bonding leg of the group is disposed on another segment of the two segments of the load potential surface of the first power semiconductor, and each of the first power semiconductors The difference is that they are arranged adjacent to two radially opposite edges. Exactly one, the load potential plane of the second power semiconductor connected to the bonding connection of the second power semiconductor is between one edge of the second power semiconductor between the first and second power semiconductors. And one of the remaining edges of the first power semiconductor. According to one embodiment, the load potential surface of the second power semiconductor is formed by a metallization part of the substrate, which metallization part simultaneously forms a contact connection with the first power semiconductor, and And / or a further load potential plane belonging to the second power semiconductor is formed. This makes it possible to achieve a space-saving arrangement of power semiconductors including the associated load potential surface at the same time as a uniform current distribution. In particular, this allows a symmetrical arrangement of the load potential plane or its segments. This means that, for example, the terminal parts used regularly for the purpose of further connection with the external conductor tracks arranged outside the housing belonging to the power semiconductor module according to the invention are also symmetrical, for example in the bracket shape. Has the advantage that it can be designed in an efficient manner. This leads not only to a particularly uniform current distribution, but also to a simple production of the module according to the invention.

パワー半導体は、バイポーラトランジスタ、サイリスタ、ダイオードを含むグループから選択されている。好ましくは厳密に２つのパワー半導体は、異なるパワー半導体の対である。   The power semiconductor is selected from the group including bipolar transistors, thyristors, and diodes. Preferably exactly two power semiconductors are pairs of different power semiconductors.

本発明は、さらに、前述した各実施形態のうちの１つのヒートシンクとパワー半導体モジュールとからなり、前述した相応の技術的利点を有する装置に関する。   The invention further relates to a device comprising a heat sink and a power semiconductor module in each of the embodiments described above and having the corresponding technical advantages described above.

以下では本発明を、図面に基づきより詳細に説明する。この場合これらの図面は例示的なものとしてのみ理解されるべきであり、１つの好ましい変化実施例を示しているにすぎない。   Hereinafter, the present invention will be described in more detail with reference to the drawings. In this case, these drawings should be understood as illustrative only and show only one preferred variant embodiment.

本発明によるパワー半導体モジュール１０の第１の実施形態の平面図Plan view of a first embodiment of a power semiconductor module 10 according to the present invention. 図１のパワー半導体モジュールの詳細図Detailed view of the power semiconductor module of FIG. 図１のパワー半導体モジュールのさらなる詳細図Further details of the power semiconductor module of FIG. 本発明によるパワー半導体モジュール１０の第２の実施形態の平面図Plan view of a second embodiment of a power semiconductor module 10 according to the present invention. 図４に示された構造の説明のためいくつかの構成部品を抜いた図４による平面図4 is a plan view of FIG. 4 with some components removed to illustrate the structure shown in FIG. 図４に示された構造の説明のため別の構成部品を抜いた図４による平面図FIG. 4 is a plan view of the structure shown in FIG. 4 with other components removed.

図１〜図３は、本発明によるパワー半導体モジュール１０の第１の実施形態を示し、それに対して図４〜図６は、本発明によるパワー半導体モジュール１０の第２の実施形態を示す。第１および第２の実施形態のモジュールは、実質的に、使用されるパワー半導体１，２およびボンディング接続構造部、とりわけ第２のパワー半導体２の詳細によって異なる。図１〜図３による第１の実施形態は、第１のパワー半導体１および第２のパワー半導体２として、２つのサイリスタを有し、それに対して図４〜図６の実施形態は、第１のパワー半導体１もしくは第２のパワー半導体２として、２つのダイオードを有する。   1 to 3 show a first embodiment of a power semiconductor module 10 according to the present invention, whereas FIGS. 4 to 6 show a second embodiment of a power semiconductor module 10 according to the present invention. The modules of the first and second embodiments differ substantially depending on the details of the power semiconductors 1, 2 and the bonding connection structure used, in particular the second power semiconductor 2. The first embodiment according to FIGS. 1 to 3 has two thyristors as the first power semiconductor 1 and the second power semiconductor 2, whereas the embodiment of FIGS. The power semiconductor 1 or the second power semiconductor 2 has two diodes.

第１の実施形態のパワー半導体モジュール１０は、金属ベースプレート５を有しており、このベースプレート５は、図示されていないヒートシンク上への配置と固定に用いられる。ベースプレート５の、ヒートシンクとは反対側には、セラミックからなる２つの電気的に絶縁された基板３，４が被着されている。基板３，４の、ベースプレート５とは反対側の表面には、それぞれ複数の金属化部が被着されており、それぞれ１つは、その上に配置されたパワー半導体１，２の主表面の固定と電気的接触接続に使用される。基板３，４の他の金属化部は、パワー半導体１，２のための負荷電位面１３ａ，１３ｂ，２３の提供に用いられる。この場合、第１のパワー半導体１には、とりわけ、２つのセグメント１３ａ，１３ｂから形成された負荷電位面が割り当てられている。１つの負荷電位面へのセグメント１３ａ，１３ｂの割り当ては、パワー半導体の、ここではパワー半導体１のカソードの同じ機能的な相互接続によって生じ、ただし、図示されていない端子部品の平行な電流供給または引き出しによっても相応に生じる。この端子部品は、ブラケット状でかつ鏡面対称に構成され、パワー半導体１と交差的に配置され、そのブラケット自由端部は負荷電位面１３ａ，１３ｂ上に載置されてこれとはんだ付けされる。相互に実質的に平行に配置されている、アルミニウムボンディングワイヤまたは代替的に銅ボンディングワイヤからなる、複数のボンディング接続部１５，１６が設けられている。これらのボンディング接続部１５，１６の各々は、第１のボンディング脚部３１を有し、この第１のボンディング脚部３１は、それが負荷電位面もしくは所属のセグメントとの接触接続部を有することによって優れている。これらのボンディング接続部１５，１６の各々は、少なくとも２つ、ここでは３つの第２のボンディング脚部３２を有しており、これらの第２のボンディング脚部３２は、それらが端子面１１もしくは端子面１１のここではセグメント１２ａ，１２ｂのような所属の領域に配置されていることによって優れている。以下で説明する全てのボンディング脚部３１，３２，３３は、ＵＳ−ウェッジ−ウェッジボンディングにより、それぞれボンディング接続部によって接触接続される金属化部と接続されている。   The power semiconductor module 10 of the first embodiment has a metal base plate 5 that is used for placement and fixing on a heat sink (not shown). On the opposite side of the base plate 5 from the heat sink, two electrically insulated substrates 3 and 4 made of ceramic are attached. A plurality of metallized portions are respectively deposited on the surfaces of the substrates 3 and 4 opposite to the base plate 5, and one of them is a main surface of the power semiconductors 1 and 2 disposed thereon, respectively. Used for fixed and electrical contact connection. The other metallizations of the substrates 3 and 4 are used to provide load potential surfaces 13a, 13b, 23 for the power semiconductors 1,2. In this case, the first power semiconductor 1 is assigned, among other things, a load potential surface formed by two segments 13a and 13b. The assignment of the segments 13a, 13b to one load potential plane is caused by the same functional interconnection of the power semiconductor, here the cathode of the power semiconductor 1, provided that a parallel current supply of terminal components not shown or Produced accordingly by drawer. This terminal part is formed in a bracket shape and is mirror-symmetrical, and is disposed so as to intersect with the power semiconductor 1, and the bracket free ends are placed on the load potential surfaces 13a and 13b and soldered thereto. A plurality of bonding connections 15, 16 are provided, consisting of aluminum bonding wires or alternatively copper bonding wires, arranged substantially parallel to each other. Each of these bonding connections 15, 16 has a first bonding leg 31, which has a contact connection with the load potential surface or the segment to which it belongs. Is better by. Each of these bonding connections 15, 16 has at least two, here three, second bonding legs 32, which are connected to the terminal surface 11 or Here, the terminal surface 11 is excellent because it is disposed in a region to which the segment 12a, 12b belongs. All of the bonding legs 31, 32, and 33 described below are connected to metallized portions that are contact-connected by bonding connection portions by US-wedge-wedge bonding, respectively.

セグメント１２ａおよび１２ｂは、パワー半導体１の機能的な相互接続に基づいて、端子面１１に、ここではカソード端子面に統合される。図中のそれぞれ第１のボンディング脚部３１および第２のボンディング脚部３２の符号は、明瞭化のために省略されている。ボンディング脚部３１，３２の間で、ボンディング接続部は、湾曲部を形成し、この湾曲部は、図３中に第１のパワー半導体１のボンディング接続部に関連して明確に示されている。グループ１５および１６のボンディング接続部は、それらが全て同じ数の第２のボンディング脚部３２を有し、かつ端子面１１上に存在する終端部を有していることによって優れている。したがって、一方の負荷電位面セグメント１３ａから出発して、複数の第２のボンディング脚部３２を端子面１１上で形成しながら、ただしそこで終端することなく、別の負荷端子面セグメント１３ｂまで、そこにおいて再び終端するために延在している、図示されていないボンディング接続部は、本発明による、ひいては複数のグループの１つに所属するボンディング接続部としては見なされないであろう。ボンディング接続部１５および１６をグループに区別して分割することは、一方では、グループのボンディング接続部を、専ら、端子面の部分面によって画定されるセグメント、詳細には端子面１１のセグメント１２ａもしくは１２ｂに配置することによって生じ、他方では、それらの第１のボンディング脚部３１を負荷電位面の別のセグメント１３ａもしくは１３ｂに配置することによって生じる。本発明による平行かつ枝分かれした電流供給もしくは引き出し、およびここでの最良なケースのように、端子面のセグメントまで延在する分枝は、電流分布に関して、特に、端子面の複数のセグメントにわたって延在するこれまでに公知のボンディング接続部に比べて、有利に作用することが示された。パワー半導体１のボンディング接続部の第２のボンディング脚部３２の配置構成は、軸線４４に沿って鏡面対称である。   The segments 12 a and 12 b are integrated into the terminal surface 11, here the cathode terminal surface, based on the functional interconnection of the power semiconductor 1. Reference numerals of the first bonding leg 31 and the second bonding leg 32 in the drawing are omitted for the sake of clarity. Between the bonding legs 31, 32, the bonding connection forms a curved portion, which is clearly shown in FIG. 3 in relation to the bonding connection of the first power semiconductor 1. . The bonding connections of the groups 15 and 16 are excellent because they all have the same number of second bonding legs 32 and have terminations present on the terminal surface 11. Thus, starting from one load potential surface segment 13a, a plurality of second bonding legs 32 are formed on the terminal surface 11, but without terminating there, to another load terminal surface segment 13b. Bonding connections (not shown) that extend to terminate again in FIG. 1 would not be considered as bonding connections belonging to one of the groups according to the invention. Separating and dividing the bonding connections 15 and 16 into groups, on the one hand, divides the bonding connections of the group exclusively into segments defined by the partial surfaces of the terminal surfaces, in particular the segments 12a or 12b of the terminal surfaces 11 On the other hand, by placing their first bonding legs 31 in another segment 13a or 13b of the load potential surface. A parallel and branched current supply or extraction according to the invention, and as in the best case here, a branch extending to a segment of the terminal surface extends with respect to the current distribution, in particular across a plurality of segments of the terminal surface. Thus, it has been shown to be advantageous compared to previously known bonding connections. The arrangement configuration of the second bonding legs 32 of the bonding connection portion of the power semiconductor 1 is mirror-symmetrical along the axis 44.

本発明による態様は、特に、さらに別の基板４上に配置されている第２のパワー半導体２に関している。そのボンディング接続部２５，２６の具体的な構成は、図２において詳細に認識可能である。このパワー半導体２もサイリスタである。ここでも、複数のボンディング接続部２５，２６が、同じ数のボンディング脚部３１および３２の複数のボンディング接続部からなる少なくとも２つのグループ２５，２６に配列され、１つのグループの各ボンディング接続部の第２のボンディング脚部３２は、専ら、端子面のそれ自体閉じられた共通の部分面によって画定される、端子面２１のセグメント２２ａもしくは２２ｂに配置されている。これらのグループは、それらの第１のボンディング脚部３１が、ここでは基板３上に存在する所属の負荷電位面２３上で、パワー半導体２から、異なった間隔ではあるが、ただし各グループ内では一致している間隔ａ１もしくはａ２をおいて配置されていることに関して異なっている。ここでは、その所属のセグメント２２ａが、関連する負荷電位面２３に空間的に近接して配置されているグループ２６の間隔ａ２は、その所属のセグメント２２ｂが、関連する負荷電位面から空間的にさらに離間されて配置されているグループ２５の間隔ａ１よりも大きくなるように選択されており、これによって、少なくともほぼ、ボンディング接続部２５，２６の長さの一致が生じる。 The embodiment according to the invention particularly relates to a second power semiconductor 2 arranged on a further substrate 4. The specific configuration of the bonding connections 25 and 26 can be recognized in detail in FIG. This power semiconductor 2 is also a thyristor. Again, a plurality of bonding connections 25, 26 are arranged in at least two groups 25, 26 comprising a plurality of bonding connections of the same number of bonding legs 31, 32, and each bonding connection of one group is arranged. The second bonding leg 32 is arranged exclusively in the segment 22a or 22b of the terminal surface 21 defined by a common partial surface that is itself closed on the terminal surface. These groups have their first bonding legs 31 spaced apart from the power semiconductor 2 on the associated load potential surface 23, which now exists on the substrate 3, but within each group. The difference is that they are arranged with a matching spacing a 1 or a 2 . Here, the affiliation of the segment 22a is, distance a 2 of the associated load potential surface 23 in spatial proximity to placed in that group 26, the segment 22b of the affiliation, spatially from the associated load potential surface It is selected to be larger still than the distance a 1 of the group 25 are spaced apart are disposed, whereby, at least approximately, matching the length of the bonding connections 25 and 26 occurs.

図４〜図６に示された第２の実施形態のパワー半導体モジュール１０は、金属ベースプレート５を有しており、この金属ベースプレート５は、図示されていないヒートシンク上への配置と固定に用いられる。ベースプレート５の、ヒートシンクとは反対側には、セラミックからなる２つの電気的に絶縁された基板３，４が被着されている。基板３，４の、ベースプレート５とは反対側の表面には、それぞれ複数の金属化部が被着されており、それぞれ１つは、その上に配置されたパワー半導体１，２の主表面の固定と電気的接触接続に使用される。これらのパワー半導体１，２はそれぞれ前述したようにパワーダイオードである。基板３，４の他の金属化部は、パワー半導体１，２のための負荷電位面１３ａ，１３ｂ，２３の提供に用いられる。この場合、パワー半導体１には、とりわけ、２つのセグメント１３ａ，１３ｂから形成された負荷電位面が割り当てられている。１つの負荷電位面へのセグメント１３ａ，１３ｂの割り当ては、パワー半導体の、ここではパワー半導体１のアノード端子の同じ機能的な相互接続によって生じ、ただし、図示されていない端子部品の平行な電流供給または引き出しによっても相応に生じる。この端子部品は、ブラケット状でかつ鏡面対称に構成されており、パワー半導体１と交差的に配置され、そのブラケット自由端部は負荷電位面１３ａ，１３ｂ上に載置されてこれとはんだ付けされる。相互に実質的に平行に配置されている、アルミニウムボンディングワイヤまたは代替的に銅ボンディングワイヤからなる、複数のボンディング接続部１５，１６が設けられている。これらのボンディング接続部１５，１６の各々は、第１のボンディング脚部３１を有し、この第１のボンディング脚部３１は、それが負荷電位面もしくは所属のセグメント１３ａもしくは１３ｂとの接触接続部を有することによって優れている。これらのボンディング接続部１５，１６の各々は、少なくとも２つ、ここでは３つの第２のボンディング脚部３２を有しており、これらの第２のボンディング脚部３２は、それらが端子面１１もしくは端子面１１の所属の領域１２ａ，１２ｂに配置されていることによって優れている。これらの領域１２ａ，１２ｂは、ここでは一点鎖線によって相互に区別されており、セグメント化は存在しないが、端子面１１は、第１の実施形態のパワー半導体１とは異なり、連続的な金属化部によって画定されている。図中のそれぞれ第１のボンディング脚部３１および第２のボンディング脚部３２の符号は、明瞭化のために省略されている。ボンディング脚部３１，３２の間で、ボンディング接続部は、湾曲部を形成する。グループ１５および１６のボンディング接続部は、それらが全て同じ数の第２のボンディング脚部３２を有し、かつ端子面１１上に存在する終端部を有していることによって優れている。ボンディング接続部１５および１６をグループに区別して分割することは、一方では、グループのボンディング接続部を、専ら、端子面の部分面によって画定される領域、詳細には端子面１１の領域１２ａもしくは１２ｂに配置することによって生じ、他方では、それらの第１のボンディング脚部３１を負荷電位面の別のセグメント１３ａもしくは１３ｂに配置することによって生じる。本発明による平行でかつ枝分かれした電流供給もしくは引き出し、およびここでの最良なケースのように、端子面のセグメントまで延在する分枝は、電流分布に関して、特に、端子面の複数のセグメントにわたって延在するこれまでに公知のボンディング接続部に比べて、有利に作用することが示された。   The power semiconductor module 10 of the second embodiment shown in FIGS. 4 to 6 has a metal base plate 5, and this metal base plate 5 is used for placement and fixing on a heat sink (not shown). . On the opposite side of the base plate 5 from the heat sink, two electrically insulated substrates 3 and 4 made of ceramic are attached. A plurality of metallized portions are respectively deposited on the surfaces of the substrates 3 and 4 opposite to the base plate 5, and one of them is a main surface of the power semiconductors 1 and 2 disposed thereon, respectively. Used for fixed and electrical contact connection. Each of these power semiconductors 1 and 2 is a power diode as described above. The other metallizations of the substrates 3 and 4 are used to provide load potential surfaces 13a, 13b, 23 for the power semiconductors 1,2. In this case, the power semiconductor 1 is assigned, among other things, a load potential surface formed from two segments 13a and 13b. The assignment of the segments 13a, 13b to one load potential plane is caused by the same functional interconnection of the power semiconductor, here the anode terminal of the power semiconductor 1, but with a parallel current supply of terminal components not shown. Or it can be caused by a drawer. This terminal part is formed in a bracket shape and is mirror-symmetrical, and is disposed so as to intersect with the power semiconductor 1, and the bracket free ends are placed on the load potential surfaces 13a and 13b and soldered thereto. The A plurality of bonding connections 15, 16 are provided, consisting of aluminum bonding wires or alternatively copper bonding wires, arranged substantially parallel to each other. Each of these bonding connections 15, 16 has a first bonding leg 31, which is a contact connection with the load potential plane or the segment 13a or 13b to which it belongs. It is excellent by having. Each of these bonding connections 15, 16 has at least two, here three, second bonding legs 32, which are connected to the terminal surface 11 or It is excellent by being arranged in the region 12a, 12b to which the terminal surface 11 belongs. These regions 12a and 12b are distinguished from each other by a one-dot chain line here, and there is no segmentation. However, unlike the power semiconductor 1 of the first embodiment, the terminal surface 11 is a continuous metallization. Defined by the part. Reference numerals of the first bonding leg 31 and the second bonding leg 32 in the drawing are omitted for the sake of clarity. Between the bonding legs 31 and 32, the bonding connection portion forms a curved portion. The bonding connections of the groups 15 and 16 are excellent because they all have the same number of second bonding legs 32 and have terminations present on the terminal surface 11. Separating and dividing the bonding connections 15 and 16 into groups means, on the one hand, that the bonding connections of the group are exclusively defined by the regions defined by the partial surfaces of the terminal surfaces, in particular the regions 12a or 12b of the terminal surfaces 11. On the other hand, by placing their first bonding legs 31 in another segment 13a or 13b of the load potential surface. As in the case of the parallel and branched current supply or extraction according to the invention, and in the best case here, the branches extending to the segment of the terminal surface extend with respect to the current distribution, in particular over a plurality of segments of the terminal surface. It has been shown to be advantageous compared to the existing known bonding connections.

本発明によるボンディング接続部の態様は、特に、さらに別の基板４上に配置されている第２のパワー半導体２に関している。そのボンディング接続部２５，２６の具体的な構成は、図５において詳細に認識可能であり、ここではそれぞれ例示的に示されたボンディング接続部２５もしくは２６において明らかである。このパワー半導体２もダイオードである。ここでも、複数のボンディング接続部２５，２６が、それぞれ同じ数のボンディング脚部３１および３２の複数のボンディング接続部からなる少なくとも２つのグループ２５，２６に配列され、１つのグループの各ボンディング接続部の第２のボンディング脚部３２は、専ら、端子面の共通のそれ自体閉じられた部分面によって画定される、端子面２１の領域２２ａもしくは２２ｂに配置されている。しかしながら、図５に示すように、ボンディング接続部２５，２６の一部を省略することにより、これらのグループはボンディング脚部の数において異なることが明らかにされる。グループ２５は、全部で３つのボンディング脚部を有し、そのうちの２つのみが第２のボンディング脚部３２であるのに対して、グループ２６は、全部で５つのボンディング脚部を有し、そのうちの３つが第２のボンディング脚部である。その上さらに、端子面２１上に存在する第２のボンディング脚部３２と、負荷電位面２３上に存在する第１のボンディング脚部３１と、の間には、それぞれ１つの第３のボンディング脚部３３が設けられており、この第３のボンディング脚部３３は、負荷電位面２３と端子面２１とに対して電気的に絶縁されて基板４上に配置された金属化部３０上に配置されている。１つのグループ２６のみが第３のボンディング脚部３３をそのボンディング接続部に有し、それらの全ては金属化部３０の閉じられた表面上に配置されている。   The embodiment of the bonding connection according to the invention relates in particular to the second power semiconductor 2 arranged on a further substrate 4. The specific configuration of the bonding connection portions 25 and 26 can be recognized in detail in FIG. 5, and is apparent in the bonding connection portion 25 or 26 shown here as an example. This power semiconductor 2 is also a diode. Here again, the plurality of bonding connections 25 and 26 are arranged in at least two groups 25 and 26 each consisting of a plurality of bonding connections of the same number of bonding legs 31 and 32, respectively. The second bonding leg 32 is arranged exclusively in the region 22a or 22b of the terminal surface 21, which is defined by a common closed partial surface of the terminal surface. However, as shown in FIG. 5, by omitting some of the bonding connections 25 and 26, it becomes clear that these groups differ in the number of bonding legs. Group 25 has a total of three bonding legs, only two of which are second bonding legs 32, whereas group 26 has a total of five bonding legs, Three of them are second bonding legs. In addition, a third bonding leg is provided between the second bonding leg 32 existing on the terminal surface 21 and the first bonding leg 31 existing on the load potential surface 23. The third bonding leg 33 is disposed on the metallized portion 30 that is electrically insulated from the load potential surface 23 and the terminal surface 21 and disposed on the substrate 4. Has been. Only one group 26 has a third bonding leg 33 in its bonding connection, all of which are located on the closed surface of the metallization 30.

２つのグループのボンディング接続部は、さらに、それらの第１のボンディング脚部３１が、ここでは基板３上に存在する所属の負荷電位面２３上で、パワー半導体２から、異なった間隔ではあるが、ただし各グループ内では一致している間隔ａ１もしくはａ２をおいて配置されていることに関して異なっている。ここでは、その所属のセグメント２２ａが、関連する負荷電位面２３に空間的に近接して配置されているグループ２６の間隔ａ２は、その所属のセグメント２２ｂが、関連する負荷電位面から空間的にさらに離間されて配置されているグループ２５の間隔ａ１よりも大きくなるように選択されており、これによって、異なる数の第２のボンディング脚部３２および付加的な第３のボンディング脚部３３の特徴と協働して、少なくともほぼ、ボンディング接続部２５，２６の長さの一致が生じる。 The two groups of bonding connections are furthermore at different distances from the power semiconductor 2 on their associated load potential plane 23 where their first bonding legs 31 are here on the substrate 3. However, there is a difference with respect to the fact that each group is arranged with a matching interval a 1 or a 2 . Here, the affiliation of the segment 22a is, distance a 2 of the associated load potential surface 23 in spatial proximity to placed in that group 26, the segment 22b of the affiliation, spatially from the associated load potential surface Is selected to be greater than the spacing a 1 of the groups 25 that are further spaced apart, so that a different number of second bonding legs 32 and additional third bonding legs 33 are selected. In cooperation with this feature, at least approximately the length matching of the bonding connections 25, 26 occurs.

図５および図６に基づけば、第２のパワー半導体２に所属する負荷電位面２３は、パワー半導体１および２の縁部に平行に延在するように配置されているのに対し、第３のボンディング脚部３３のために設けられた金属化部３０は、平行に離間されて、負荷電位面２３と第２のパワー半導体２の縁部との間を延在していることが明らかにされる。負荷電位面２３は、この場合、金属化部によって画定され、この金属化部は、図示されていない端子部品のための端子面１４とはんだ付け面とをそこに画定するために、第１のパワー半導体１の下方を、当該金属化部がこの場合第１のパワー半導体１の基板３に面する主表面に接触しながら他方の側まで延在している。   5 and 6, the load potential surface 23 belonging to the second power semiconductor 2 is arranged so as to extend in parallel to the edges of the power semiconductors 1 and 2, whereas the third It is clear that the metallized portion 30 provided for the bonding leg 33 is extended in parallel between the load potential surface 23 and the edge of the second power semiconductor 2. Is done. The load potential surface 23 is in this case defined by a metallization, which in order to define a terminal surface 14 and a soldering surface for a terminal component not shown in the first Underneath the power semiconductor 1, the metallization part in this case extends to the other side while in contact with the main surface facing the substrate 3 of the first power semiconductor 1.

Claims (14)

パワー半導体モジュール（１０）であって、
少なくとも１つの基板（４）と、
前記基板（４）上に配置され、前記基板とは反対側の自身の側に端子面（２１）を有している少なくとも１つのパワー半導体（２）と、
前記基板（４）上で前記パワー半導体（２）に隣接して配置された負荷電位面（２３）と、
前記端子面（２１）を、前記負荷電位面（２３）に平行かつ導電的に接続させるための複数のボンディング接続部（２５，２６）と、
を備えており、
各ボンディング接続部（２５，２６）は、前記負荷電位面（２３）上に少なくとも１つの第１のボンディング脚部（３１）を有し、前記端子面（２１）上に複数の第２のボンディング脚部（３２）を有し、前記各ボンディング接続部（２５，２６）は、前記端子面（２１）上に少なくとも１つの終端部を有し、
前記複数のボンディング接続部（２５，２６）は、同じ数のボンディング脚部を有する複数のボンディング接続部からなる少なくとも２つのグループ（２５，２６）に配列され、１つのグループの各ボンディング接続部の前記第２のボンディング脚部（３２）は、専ら、前記端子面の部分面によって画定される、前記端子面（２１）のセグメントまたは領域（２２ａもしくは２２ｂ）に配置されており、
前記グループは、前記グループの前記第１のボンディング脚部（３１）が、前記負荷電位面（２３）上で、前記パワー半導体（２）から、異なった間隔ではあるが、ただし各グループ内では一致している間隔（ａ１もしくはａ２）をおいて配置されていることに関して異なっており、
少なくとも１つの前記グループの前記ボンディング接続部（２６）が、それぞれ１つの第３のボンディング脚部（３３）を有し、前記第３のボンディング脚部（３３）は、前記第１のボンディング脚部（３１）と前記第２のボンディング脚部（３２）との間の前記ボンディング接続部（２６）の延在部において、前記負荷電位面（２３）から電気的に絶縁されて前記基板（４）上に配置された金属化部（３０）上に配置されており、
全ての前記グループ（２５もしくは２６）の前記ボンディング接続部は、長さが実質的に異ならない、
パワー半導体モジュール（１０）。 A power semiconductor module (10),
At least one substrate (4);
At least one power semiconductor (2) disposed on the substrate (4) and having a terminal surface (21) on its side opposite to the substrate;
A load potential surface (23) disposed adjacent to the power semiconductor (2) on the substrate (4);
A plurality of bonding connections (25, 26) for connecting the terminal surface (21) in parallel and conductively to the load potential surface (23);
With
Each bonding connection (25, 26) has at least one first bonding leg (31) on the load potential surface (23), and a plurality of second bondings on the terminal surface (21). Each of the bonding connections (25, 26) has at least one terminal end on the terminal surface (21);
The plurality of bonding connection portions (25, 26) are arranged in at least two groups (25, 26) including a plurality of bonding connection portions having the same number of bonding legs, and each bonding connection portion of one group is arranged. It said second bonding leg (32) exclusively, said defined by partial surfaces of the terminal surface is disposed in the segment or region (22a or 22b) of said terminal surface (21),
The group has a different spacing from the power semiconductor (2) on the load potential surface (23), but the first bonding leg (31) of the group is different within each group. are different with respect to that are arranged at a match in which spacing (a 1 or a 2),
At least one of the bonding connections (26) of the group each has one third bonding leg (33), and the third bonding leg (33) is the first bonding leg. In the extended portion of the bonding connection (26) between the (31) and the second bonding leg (32), the substrate (4) is electrically insulated from the load potential surface (23). Arranged on the metallization part (30) arranged above,
The bonding connections of all the groups (25 or 26) are not substantially different in length,
Power semiconductor module (10). 前記グループ（２５もしくは２６）ごとの各ボンディング接続部の前記第２のボンディング脚部（３２）は、専ら、前記端子面（２１）の厳密に１つの共通の部分面に配置されている、
請求項１記載のパワー半導体モジュール（１０）。 Said second bonding legs of the bonding connection of each group (25 or 26) (32) exclusively, is tightly disposed on a common partial surfaces of said terminal surface (21),
The power semiconductor module (10) according to claim 1. 前記共通の部分面は、それ自体閉じられている、
請求項２記載のパワー半導体モジュール（１０）。 The common partial surface is itself closed,
The power semiconductor module (10) according to claim 2 . 前記金属化部（３０）は、平行に離間されて、前記負荷電位面（２３）と１つの前記パワー半導体（１）の１つの縁部との間に延在している、The metallization (30) is spaced in parallel and extends between the load potential surface (23) and one edge of one power semiconductor (1),
請求項１から３までのいずれか１項記載のパワー半導体モジュール（１０）。The power semiconductor module (10) according to any one of claims 1 to 3. 前記負荷電位面（２３）はセグメント化されている、The load potential surface (23) is segmented,
請求項１から４までのいずれか１項記載のパワー半導体モジュール（１０）。The power semiconductor module (10) according to any one of claims 1 to 4. 前記グループ（２６）の前記第３のボンディング脚部（３３）は、共通の前記金属化部（３０）上に配置されている、
請求項１から５までのいずれか１項記載のパワー半導体モジュール（１０）。 Wherein the third bonding leg group (26) (33) are arranged on a common said metallization (30),
The power semiconductor module (10) according to any one of claims 1 to 5 . 前記ボンディング接続部（２５，２６）は、ボンディングワイヤである、
請求項１から６までのいずれか１項記載のパワー半導体モジュール（１０）。 The bonding connection portions (25, 26) are bonding wires.
The power semiconductor module (10) according to any one of claims 1 to 6. １つの前記グループ（２５もしくは２６）の前記第２のボンディング脚部（３２）は、規則的なパターンで配置されている、
請求項１から７までのいずれか１項記載のパワー半導体モジュール（１０）。 It said second bonding legs of one of said groups (25 or 26) (32) are arranged in a regular pattern,
The power semiconductor module (10) according to any one of claims 1 to 7. 少なくとも２つのグループ（２５もしくは２６）は、前記ボンディング接続部ごとに前記第２のボンディング脚部（３２）の数が異なっている、
請求項１から８までのいずれか１項記載のパワー半導体モジュール（１０）。 At least two groups (25 or 26) have different numbers of second bonding legs (32) for each of the bonding connections.
A power semiconductor module (10) according to any one of the preceding claims. 前記パワー半導体は、８ｍｍ〜５０ｍｍの範囲の縁部長を有している、
請求項１から９までのいずれか１項記載のパワー半導体モジュール（１０）。 The power semiconductor has an edge length in the range of 8 mm to 50 mm;
A power semiconductor module (10) according to any one of the preceding claims. グループごとに、１５〜５０の前記ボンディング接続部（２５，２６）が設けられている、
請求項１から１０までのいずれか１項記載のパワー半導体モジュール（１０）。 For each group, the bonding connection of 15 to 50 (25, 26) is provided,
A power semiconductor module (10) according to any one of the preceding claims. 前記パワー半導体（２）および所属の前記負荷電位面（２３）は、セラミック基板（４）上に配置されている、
請求項１から１１までのいずれか１項記載のパワー半導体モジュール（１０）。 The power semiconductor (2) and the associated load potential surface (23) are arranged on a ceramic substrate (4);
A power semiconductor module (10) according to any one of the preceding claims. 前記パワー半導体（２）は、ダイオード、トランジスタまたはサイリスタである、請求項１から１２までのいずれか１項記載のパワー半導体モジュール（１０）。 The power semiconductor module (10) according to any one of claims 1 to 12, wherein the power semiconductor (2) is a diode, a transistor or a thyristor. 厳密に２つの前記パワー半導体（１，２）または２の倍数に相応する数の前記パワー半導体を備え、第１のパワー半導体（１）の前記ボンディング接続部（１５，１６）は、同じ数のボンディング脚部を有する複数のボンディング接続部からなる２つのグループ（１５もしくは１６）に配列され、１つのグループの各ボンディング接続部の前記第２のボンディング脚部（３２）は、専ら、前記端子面（１１）の部分面によって画定される、前記端子面（１１）のセグメントまたは領域（１２ａもしくは１２ｂ）に配置されており、前記第１のパワー半導体（１）のグループ（１５もしくは１６）は、前記グループ（１５もしくは１６）の前記第１のボンディング脚部（３１）が、前記第１のパワー半導体（１）の前記負荷電位面の２つのセグメント（１３ａ，１３ｂ）のうちの相異なるセグメント上に配置され、さらにそれぞれ前記第１のパワー半導体（１）の径方向に対向する２つの縁部に隣接して配置されていることに関して異なっており、さらに第２のパワー半導体（２）の前記ボンディング接続部（２５，２６）に接続される厳密に１つの前記負荷電位面（２３）が、前記第１および前記第２のパワー半導体（１，２）の間で、前記第２のパワー半導体（２）の１つの縁部と、前記第１のパワー半導体（１）の残りの縁部のうちの１つと、に隣接して配置されている、
請求項１から１３までのいずれか１項記載のパワー半導体モジュール（１０）。 Exactly two power semiconductors (1, 2) or a number of the power semiconductors corresponding to multiples of 2 are provided, and the bonding connections (15, 16) of the first power semiconductor (1) have the same number. arranged in a plurality of two groups of bonding connection (15 or 16) having a bonding leg, the second bonding legs of the bonding connection of one group (32) exclusively, said terminal surface Arranged in a segment or region (12a or 12b) of the terminal surface (11), defined by a partial surface of (11), the group (15 or 16) of the first power semiconductor (1) being said first bonding leg (31), the two segments of the load potential surface of the first power semiconductor (1) of said group (15 or 16) Cement (13a, 13b) are arranged on different segments of the, it differs with respect to being further disposed adjacent to the two opposite edges in the radial direction of each of the first power semiconductor (1) cage, yet the second power semiconductor (2) wherein exactly one of said load potential surface which is connected to the bonding connection (25, 26) of (23), said first and said second power semiconductor (1 , 2) adjacent to one edge of the second power semiconductor (2) and one of the remaining edges of the first power semiconductor (1). Yes,
The power semiconductor module (10) according to any one of claims 1 to 13.
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