JP2006066704A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2006066704A
JP2006066704A JP2004248410A JP2004248410A JP2006066704A JP 2006066704 A JP2006066704 A JP 2006066704A JP 2004248410 A JP2004248410 A JP 2004248410A JP 2004248410 A JP2004248410 A JP 2004248410A JP 2006066704 A JP2006066704 A JP 2006066704A
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Japan
Prior art keywords
upper electrode
electrode layer
temperature rise
current
chip
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Application number
JP2004248410A
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Japanese (ja)
Inventor
Mikio Shirai
幹夫 白井
Takayoshi Kuriyama
貴好 栗山
Masayasu Ishiko
雅康 石子
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Toyota Motor Corp
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Toyota Motor Corp
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Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP2004248410A priority Critical patent/JP2006066704A/en
Publication of JP2006066704A publication Critical patent/JP2006066704A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for large power which can improve the reliability of junction parts of solder junction, wire bonding or the like, and can set the highest operation temperature under a power device driving condition to a high level by more uniforming temperature rise distribution. <P>SOLUTION: In the semiconductor element for a large current, the temperature rise distribution of the semiconductor element is influenced by the area distribution of resistors in an upper electrode layer 48, and the temperature rise distribution of the semiconductor element is determined dependently on the plane arrangement condition of a plurality of connections 50 in the upper electrode layer 48 because of the large current. Temperature rise distribution by the zigzag arrangement of the connections 50 like a pattern 2 is clearly different from that by the linear arrangement of the connection parts 50 like a pattern 1. This phenomenon indicates qualitatively good coincidence with a result of simulation. It is also available to form a plurality of connections between respective wires and the upper electrode layer 48. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置に係り、特に大電流用半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device for large current.

ハイブリッド車両には周知のように、インバータ回路等の電力装置のように、大電力を処理する回路が搭載される。これらの大電力処理回路には様々のパワーデバイスが用いられ、例えば、インバータ回路では、パワーダイオードやＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｔｏｒ：絶縁ゲート型バイポーラトランジスタ）等の大電力用半導体素子が使用される。   As is well known, a hybrid vehicle is equipped with a circuit that processes high power, such as a power device such as an inverter circuit. Various power devices are used for these high power processing circuits. For example, in an inverter circuit, a high power semiconductor element such as a power diode or an IGBT (Insulated Gate Bipolar Transistor) is used.

これらの大電力半導体素子の各電極を外部と接続するには、大電流を扱うために、電流通路の断面積を大きくする必要がある。そのため、例えば、半導体素子チップの下面に広く下部電極を設け、これを回路基板のパッド上に搭載して広い面積で接続し、また、チップの上面からは、電力の大きさに応じて複数本の太いワイヤを用いてワイヤボンディングにより外部端子に接続することが行われる。   In order to connect each electrode of these high power semiconductor elements to the outside, it is necessary to increase the cross-sectional area of the current path in order to handle a large current. Therefore, for example, a lower electrode is widely provided on the lower surface of the semiconductor element chip, and this is mounted on a pad of a circuit board and connected in a wide area. Also, a plurality of electrodes are provided from the upper surface of the chip according to the power level. A thick wire is used to connect to an external terminal by wire bonding.

たとえば、特許文献１には、複数のトランジスタセルを1つのチップとする高周波高出力トランジスタにおいて、セラミック基板の上にコレクタパッド層を設け、これにトランジスタチップをダイボンディングで固着させ、チップの上部のベース電極及びエミッタ電極から、トランジスタセルの数だけの複数のワイヤで外部へ引き出すことが開示される。これ以外にも、1つの電極から複数本のワイヤを引き出すことが行われている。   For example, in Patent Document 1, in a high-frequency high-power transistor having a plurality of transistor cells as one chip, a collector pad layer is provided on a ceramic substrate, and the transistor chip is fixed to the chip by die bonding. It is disclosed that a plurality of wires corresponding to the number of transistor cells are led out from the base electrode and the emitter electrode. In addition to this, a plurality of wires are drawn from one electrode.

特開平５−２６７９５６号公報Japanese Patent Laid-Open No. 5-267956

近年、パワーデバイスの高性能化、すなわち、通電損失を少なくし、高周波スイッチング動作を可能とすることが進展し、電力装置についても高出力化、小型化が進んできている。例えば、インバータ回路については、この１０年余りの間で出力密度（Ｗ／ｃｍ3）は１０倍に向上している。 In recent years, progress has been made in improving the performance of power devices, that is, reducing energization loss and enabling high-frequency switching operations, and power devices have also been increased in output and size. For example, in the case of an inverter circuit, the power density (W / cm 3 ) has improved 10 times over the past 10 years.

このようにデバイスが大電力を小さな容積の中で処理できるようになると、デバイス内の体積あたりの発熱も増加し、これがデバイスの温度上昇を招く。これにより、いくつかの課題が生ずる。   When the device can handle high power in a small volume in this way, the heat generation per volume in the device also increases, which leads to an increase in the temperature of the device. This creates several problems.

１つは、一般的に半田接合やワイヤボンディング等の接合部位の信頼性、例えばパワーサイクルテストや冷熱サイクルテスト等の信頼性は、温度差が大きいほど低くなるので、デバイスの温度上昇が大きいと、接合部位の長期的信頼性が低下する。   One is that generally the reliability of a bonding part such as solder bonding or wire bonding, for example, the reliability of a power cycle test or a thermal cycle test becomes lower as the temperature difference is larger. In addition, the long-term reliability of the bonded portion is reduced.

次に、パワーデバイスは小型化が進展するといっても、それ自体相当な大きさのチップサイズである。これに高出力化が加わって、そのチップ内での温度差が相当大きくなる。デバイスの最大駆動条件は、チップ内における最高温度の部位で決まってしまうので、温度上昇分布の不均一を考慮して許容最高動作温度を低くして使用せざるを得なくなる。   Next, even if the power device is said to be miniaturized, it has a chip size that is considerably large. In addition to the increased output, the temperature difference within the chip becomes considerably large. Since the maximum drive condition of the device is determined at the highest temperature part in the chip, the allowable maximum operating temperature must be lowered in consideration of uneven temperature rise distribution.

また、デバイスの温度上昇による破壊、特にパワーデバイスは取り扱う電力が大きいため自己発熱による破壊が発生しやすくなる。   In addition, destruction due to temperature rise of the device, in particular, power devices handle a large amount of power, so that destruction due to self-heating tends to occur.

さらに、高出力化の効果を、チップの縮小に生かしてコストダウンを図るときには、チップ面積が減少し、電流を取り出すためのワイヤ等の接続部材の数に制約が生じ、少ないワイヤ等で接続しようとすると、接続点あたりの電流密度が大きくなり、上記の課題がより大きなものとなってきている。   Furthermore, when cost reduction is achieved by taking advantage of the higher output to reduce the size of the chip, the chip area is reduced, the number of connecting members such as wires for taking out current is limited, and connections should be made with fewer wires. As a result, the current density per connection point is increased, and the above-described problems are becoming greater.

このように大電流用半導体素子を囲む技術進展により、より高密度の電力を取り扱うようになってきたにもかかわらず、従来技術では、単に、チップの下部より電極を取り出し、上部電極から適当な数のワイヤ等を接続するだけである。   Despite the progress of technology surrounding high-current semiconductor elements in this way, higher-density electric power has been handled, but in the prior art, the electrode is simply taken out from the lower part of the chip and an appropriate electrode is taken from the upper electrode. Just connect a few wires and so on.

本発明の目的は、大電力用の半導体素子において、温度上昇分布をより均一にすることにより、半田接合やワイヤボンディング等の接合部位の信頼性を高めるとともに、パワーデバイスの駆動条件における最高動作温度を高く設定可能にする半導体装置を提供することである。   The object of the present invention is to increase the reliability of the bonding part such as solder bonding and wire bonding by making the temperature rise distribution more uniform in the semiconductor element for high power, and at the maximum operating temperature in the driving condition of the power device. It is an object of the present invention to provide a semiconductor device that can set a high value.

本発明に係る半導体装置は、基板に半導体素子の下部電極を配置し、この半導体素子の上部接触領域に設けられた上部電極層に電流印加用の接続部材を複数接続する半導体装置であって、前記半導体素子の上部電極層の平面内全体に前記接続部材を離散的に接続し、半導体素子に電流を印加する際に前記上部電極層中の内部抵抗の発熱によって生じる半導体素子全体の温度上昇分布が、前記平面内全体において略均一化するようにしたことを特徴とする。   A semiconductor device according to the present invention is a semiconductor device in which a lower electrode of a semiconductor element is disposed on a substrate, and a plurality of connection members for current application are connected to an upper electrode layer provided in an upper contact region of the semiconductor element, A temperature rise distribution of the entire semiconductor element caused by heat generation of internal resistance in the upper electrode layer when the connection member is discretely connected to the entire plane of the upper electrode layer of the semiconductor element and a current is applied to the semiconductor element. Is substantially uniform over the entire plane.

また、本発明に係る半導体装置は、前記半導体素子の上部電極層の平面を、前記接続部材を接続する方向に略垂直な方向について、各々略同一面積を有する第１エリア及び第２エリアに仮想的に２分し、前記接続部材を、各々隣り合う接続部材同士が異なるエリアに接続されるように接続することが好ましい。   In the semiconductor device according to the present invention, the plane of the upper electrode layer of the semiconductor element may be virtually divided into a first area and a second area having substantially the same area in a direction substantially perpendicular to a direction in which the connection member is connected. It is preferable that the connection members are connected in such a manner that adjacent connection members are connected to different areas.

また、本発明に係る半導体装置は、上部電極層はアルミニウムであり、上部電極層全体に印加される電流と上部電極層の厚みとの比が、１０Ａ／μｍ以上であることを特徴とする。   In the semiconductor device according to the present invention, the upper electrode layer is aluminum, and the ratio of the current applied to the entire upper electrode layer to the thickness of the upper electrode layer is 10 A / μm or more.

また、本発明に係る半導体装置において、接続部材は、ワイヤボンディング用のワイヤであることが好ましい。   In the semiconductor device according to the present invention, the connecting member is preferably a wire bonding wire.

本発明に係る半導体装置によれば、半導体素子内の温度上昇分布をより均一にし、温度上昇の最高値を抑制することができる。   According to the semiconductor device of the present invention, the temperature rise distribution in the semiconductor element can be made more uniform, and the maximum value of the temperature rise can be suppressed.

本発明は、大電流を取り扱う場合に、上部電極におけるワイヤボンディングの接続配置がチップ内の温度上昇に影響するのかどうか、をシミュレーションし、その結果、ワイヤボンディングの上部電極内の配置条件によりチップ内の温度上昇がかなり異なる、との知見を得たことにもとづく。したがって、最初に、シミュレーションの内容と、そのようになる理由のモデルを説明し、次にそれを裏付ける実測結果及び具体的な大電流用の半導体素子の構成等について述べる。   The present invention simulates whether or not the connection arrangement of the wire bonding in the upper electrode affects the temperature rise in the chip when handling a large current. Based on the knowledge that the temperature rise of the water is quite different. Therefore, first, the contents of the simulation and the model of the reason for that will be described, and then the actual measurement results and the specific configuration of the semiconductor element for large current will be described.

シミュレーションの対象としては、車両用インバータ回路を構成する要素の１つである大電流用ダイオードを用いた。図１は、車両用インバータ回路１０の構成を示す図である。車両用インバータ回路１０は、大電流用ＩＧＢＴ１２と大電流用ダイオード１４とを並列接続して１組としたものを６つ用いて構成され、周知の接続法により、車両用電池１６と、車両用モータ８の各相に接続される。   As a simulation target, a high-current diode, which is one of the elements constituting the vehicle inverter circuit, was used. FIG. 1 is a diagram showing a configuration of a vehicle inverter circuit 10. The inverter circuit 10 for a vehicle is configured by using six of a large current IGBT 12 and a large current diode 14 that are connected in parallel to form one set, and the vehicle battery 16 and the vehicle are connected by a known connection method. Connected to each phase of the motor 8.

大電流用ダイオード１４は、ｐｎ接合の一方側がチップの下面全面の下部電極層に接続され、他方側がチップの上面の大部分に接触する上部電極層に接続される構成である。つまり、モデル的には、チップの上面全体と下面全体との間に流れる大電流をｐｎ接合の整流特性に従って整流する素子である。そして、この大電流用ダイオード１４は、回路基板に搭載され、下部電極層は回路基板のダイボンディングパッドに例えば、半田付けあるいは金−シリコン共晶等により電気的接続が行われ、上部電極層には、回路基板のリード端子との間でワイヤボンディングにより複数のワイヤで接続される。   The large current diode 14 is configured such that one side of the pn junction is connected to the lower electrode layer on the entire lower surface of the chip, and the other side is connected to the upper electrode layer in contact with most of the upper surface of the chip. That is, in terms of a model, it is an element that rectifies a large current flowing between the entire top surface and the entire bottom surface of the chip according to the rectifying characteristics of the pn junction. The large current diode 14 is mounted on the circuit board, and the lower electrode layer is electrically connected to the die bonding pad of the circuit board, for example, by soldering or gold-silicon eutectic. Are connected to the lead terminals of the circuit board by a plurality of wires by wire bonding.

通常の電流レベルを取り扱っている感覚からは、このような構成のダイオード素子では、上部電極層及び下部電極層が導体であるので、そのどの部位に電流が印加されても、導体中は電流が均一となり、半導体素子の上面全体と下面全体との間に電流が流れる、と考えられる。つまり、上部電極層のどこにワイヤを接続しても、電流の流れ方は同じで、したがって、ダイオード内部の温度上昇も同じと考えられる。シミュレーションは、そのことが大電流の下でも同様かどうかを確かめるものである。   From the sense of handling a normal current level, in the diode element having such a configuration, the upper electrode layer and the lower electrode layer are conductors. It becomes uniform, and it is considered that current flows between the entire upper surface and the entire lower surface of the semiconductor element. That is, no matter where the wire is connected in the upper electrode layer, the current flows in the same way, and therefore the temperature rise inside the diode is considered to be the same. Simulation confirms whether this is the same even under high current.

ワイヤボンディングの接続配置によるチップ内の温度上昇分布を計算するには、電流によるジュール熱を考慮したシミュレーションを行う必要がある。ここでは、半導体のプロセス・デバイスシミュレーションツールの提供で知られるＩＳＥ社の電気−熱−機械シミュレータであるＳＯＬＩＤＩＳ（２Ｄ，３Ｄ ＴＨＥＲＭＯ−ＥＬＥＣＴＲＯ−ＭＥＣＨＡＮＩＣＡＬ ＳＩＭＵＲＡＴＩＯＮ ＴＯＯＬ）を使用した。   In order to calculate the temperature rise distribution in the chip due to the connection arrangement of wire bonding, it is necessary to perform a simulation in consideration of Joule heat due to current. Here, SOLIDIS (2D, 3D THERMO-ELECTRO-MECHANICAL SIMULATION TOOL), which is an electro-thermo-mechanical simulator of ISE, known for providing semiconductor process and device simulation tools, was used.

図２は、シミュレータ２０の構成を示す図である。このシミュレータ２０の基本部分は計算を行う計算カーネル２２と、表示処理を行うグラフィカルフロントエンド２４である。ユーザは、シミュレーション実行内容を示すコマンドファイルであるソリューションコントロール２６と、構造ファイルであるイニシャルグリッド２８を事前に定義する。表示に必要なファイルは、グラフィクスセットアップ３０とポストスクリプト出力３２である。その他は、データファイル等である。   FIG. 2 is a diagram illustrating a configuration of the simulator 20. The basic part of the simulator 20 is a calculation kernel 22 that performs calculation and a graphical front end 24 that performs display processing. The user defines in advance a solution control 26 which is a command file indicating the execution contents of the simulation and an initial grid 28 which is a structure file. Files necessary for display are a graphics setup 30 and a postscript output 32. Others are data files and the like.

シミュレーションは、対象物を計算単位のグリッドに区切り、所定の電気的、熱的境界条件を設定し、次の式（１）の伝熱方程式を解くことで行われる。

Figure 2006066704
ここで、ρは密度、ｃは比熱容量、κは熱伝導率、Ｈは熱源を示す。ここで熱源の項をジュール熱
Figure 2006066704
として、更に次の式（２）の電流連続の項を入れて計算する。
Figure 2006066704
 ここで、Ｊは電流で、
Figure 2006066704
σは電気伝導度、ψは電位を示す。したがって、式（１）、式（２）を同時計算するように熱的電気的結合の定義をコマンドファイル上で宣言しておく。 The simulation is performed by dividing the object into grids of calculation units, setting predetermined electrical and thermal boundary conditions, and solving the heat transfer equation of the following equation (1).
Figure 2006066704
 Here, ρ is density, c is specific heat capacity, κ is thermal conductivity, and H is a heat source. Where the heat source term is Joule heat
Figure 2006066704
Further, the calculation is performed by adding a term of current continuity in the following equation (2).
Figure 2006066704
 Where J is the current,
Figure 2006066704
σ represents electric conductivity, and ψ represents electric potential. Therefore, the definition of thermal electrical coupling is declared on the command file so that the expressions (1) and (2) are calculated simultaneously.

図３は、検討した大電流用の半導体装置（モジュール）の上面構造図である。ここでは５５ｍｍ×３９ｍｍの放熱板／ハウジングケース４０の上に、３５ｍｍ×１９ｍｍの回路基板４２が取り付けられ、回路基板４２上に大電流用ダイオードであるチップ４４が配置される。回路基板４２には、チップの下部電極からの電流を外部に取り出す電流出力口４６が設けられる。詳細な平面配置の寸法は図３の通りである。   FIG. 3 is a top structural view of the semiconductor device (module) for large current examined. Here, a circuit board 42 of 35 mm × 19 mm is mounted on a heat sink / housing case 40 of 55 mm × 39 mm, and a chip 44 which is a large current diode is disposed on the circuit board 42. The circuit board 42 is provided with a current output port 46 for taking out the current from the lower electrode of the chip to the outside. The dimensions of the detailed planar arrangement are as shown in FIG.

図４は、検討した大電流用の半導体装置（モジュール）の断面図である。ここでは、放熱板／ハウジングケース４０として、厚さ６ｍｍのアルミニウムからなるハウジングケースの上に厚さ３ｍｍの放熱板を積層したものとし、その間には図示されていないグリースが６５μｍ厚みで置かれる。その上に回路基板４２が搭載される。   FIG. 4 is a cross-sectional view of the high-current semiconductor device (module) studied. Here, it is assumed that a heat radiating plate having a thickness of 3 mm is laminated on a housing case made of aluminum having a thickness of 6 mm as the heat radiating plate / housing case 40, and a not-shown grease is placed between them with a thickness of 65 μm. A circuit board 42 is mounted thereon.

放熱板／ハウジングケース４０の上の構成は、図４に示すように、下層側から順に、厚さ２００μｍの下部半田層、４００μｍのアルミニウム層、７００μｍのセラミック層、４００μｍのアルミニウム層、２００μｍの上部半田層、２００μｍのシリコンチップ層となる。回路基板４２は、アルミニウム−セラミック−アルミニウム積層のいわゆるアルミニウム貼りセラミック回路基板で、ＤＢＡ（Ｄｉｒｅｃｔ Ｂｏｎｄ Ａｌｕｍｉｎｉｕｍ）基板と呼ばれる。この回路基板４２の下部及び上部に半田層を設け、それぞれ放熱板／ハウジングケース４０及びチップ４４と接合する。チップ４４の上は、１．５ｍｍの空気層とした。   As shown in FIG. 4, the upper structure of the heat sink / housing case 40 consists of a lower solder layer having a thickness of 200 μm, an aluminum layer having a thickness of 400 μm, a ceramic layer having a thickness of 700 μm, an aluminum layer having a thickness of 400 μm, and an upper portion having a thickness of 200 μm. It becomes a solder layer and a 200 μm silicon chip layer. The circuit board 42 is a so-called aluminum-laminated ceramic circuit board having an aluminum-ceramic-aluminum laminate, and is called a DBA (Direct Bond Aluminum) board. A solder layer is provided on the lower and upper portions of the circuit board 42 and joined to the heat sink / housing case 40 and the chip 44, respectively. A 1.5 mm air layer was formed on the chip 44.

図５は、チップ４４の平面図である。チップ４４は、平面寸法が６．５ｍｍ×６．５ｍｍ、厚みが２００μｍのシリコンｐｎダイオードである。チップ４４の下面は、図４で説明したように、全面が上部半田層により、回路基板４２のアルミニウム層と接合される。チップ４４の上面は、周辺部に０．５ｍｍの余裕をとり、平面寸法５．５ｍｍ×５．５ｍｍ、厚さ５μｍのアルミニウムの上部電極層４８が設けられる。つまり、シリコン層は、この５．５ｍｍ×５．５ｍｍの面積で、厚さ５μｍのアルミニウム上部電極層４８と接続されていることになる。   FIG. 5 is a plan view of the chip 44. The chip 44 is a silicon pn diode having a planar dimension of 6.5 mm × 6.5 mm and a thickness of 200 μm. The lower surface of the chip 44 is bonded to the aluminum layer of the circuit board 42 by the upper solder layer as described above with reference to FIG. The upper surface of the chip 44 is provided with an upper electrode layer 48 made of aluminum having a margin of 0.5 mm in the periphery, a plane dimension of 5.5 mm × 5.5 mm, and a thickness of 5 μm. In other words, the silicon layer has an area of 5.5 mm × 5.5 mm and is connected to the aluminum upper electrode layer 48 having a thickness of 5 μm.

チップ４４の上部電極層４８には、複数のワイヤがボンディングされるが、ボンディングによる上部電極層４８の上における各接続部５０のそれぞれの大きさは、０．５ｍｍ×１ｍｍとする。この接続部５０が、チップ４４の電流の入力部（印加部）となる。   A plurality of wires are bonded to the upper electrode layer 48 of the chip 44, and the size of each connection portion 50 on the upper electrode layer 48 by bonding is 0.5 mm × 1 mm. The connection unit 50 serves as a current input unit (application unit) of the chip 44.

図６は、シミュレーションに用いた主なパラメータの値を示すものである。ただし、シリコンの電気伝導度は、実際のデバイス特性に合うように修正した。また、半導体デバイス全体の放熱性の条件としては、図４において上部は、１．５ｍｍの空気層を挟んで一定の温度になるものとし、下部は、放熱板／ハウジングケース４０全体で熱伝導率を２１０Ｗ／ｍ2Ｋ）とした。 FIG. 6 shows the values of main parameters used in the simulation. However, the electrical conductivity of silicon was modified to match the actual device characteristics. As for the heat dissipation condition of the entire semiconductor device, the upper part in FIG. 4 is assumed to have a constant temperature across an air layer of 1.5 mm, and the lower part is the thermal conductivity of the entire heat sink / housing case 40. Was 210 W / m 2 K).

このような条件の下で、チップ４４のデバイスとしてのオン電圧等を参考にし、シリコンの電気伝導度を変化させて、式（１）、（２）を実行し、シミュレーションを行う。図７はその様子を示す図で、図７（ａ）は上記の配置構成の斜視図、（ｂ）は回路基板４２上の電流分布、（ｃ）は半導体装置全体の温度上昇分布を模式的に示すものである。この例では、チップ４４のほぼ中央において温度上昇が最も高くなっていることが示される。   Under such conditions, the on-voltage etc. as the device of the chip 44 is referred to, the electric conductivity of silicon is changed, the expressions (1) and (2) are executed, and the simulation is performed. 7A and 7B are views showing the state, FIG. 7A is a perspective view of the above arrangement, FIG. 7B is a current distribution on the circuit board 42, and FIG. 7C is a schematic temperature increase distribution of the entire semiconductor device. It is shown in In this example, it is shown that the temperature rise is highest at the center of the chip 44.

つぎに、チップの温度上昇分布のみに注目し、上部電極層４８の上の接続部５０、すなわち電流印加部の配置を変化させてみた。図８の上段に、シミュレーションに用いた、接続部５０の配置パターンの例を示す。パターン１は、５つの接続部５０を上部電極層４８のほぼ中央に一列に配置したものである。ワイヤボンディングでいえば、５本のワイヤを上部電極層４８のほぼ中央に並んでボンディングする１列ボンディングに相当する。パターン２は、５つの接続部５０を上部電極層４８の平面内で、離散的にジグザク状に配置したものである。ワイヤボンディングでいえば、２本のワイヤを上部電極層４８の中央から手前側にボンディングし、３本のワイヤを上部電極層４８の中央から奥側にボンディングする２列ボンディングに相当する。パターン３は、１０個の接続部５０を、手前側に５つ、奥側に５つ、２列に分けて上部電極層４８に配置したものである。ワイヤボンディングでいえば、１０本のワイヤをこのようにボンディングすることもできるが、こみいった作業になる。そこで、１本のワイヤで手前側にボンディングした後ワイヤを切らずにそのままワイヤを延ばし、奥側をもう一度ボンディングするいわば２段ボンディングを行うことで、５本のワイヤで実現することもできる。   Next, paying attention only to the temperature rise distribution of the chip, the arrangement of the connection part 50 on the upper electrode layer 48, that is, the current application part was changed. The upper part of FIG. 8 shows an example of the arrangement pattern of the connection portions 50 used in the simulation. In the pattern 1, five connection portions 50 are arranged in a line at substantially the center of the upper electrode layer 48. Speaking of wire bonding, this corresponds to one-line bonding in which five wires are bonded in line at the approximate center of the upper electrode layer 48. In pattern 2, five connection portions 50 are discretely arranged in a zigzag pattern in the plane of the upper electrode layer 48. Speaking of wire bonding, this corresponds to two-row bonding in which two wires are bonded from the center of the upper electrode layer 48 to the front side, and three wires are bonded from the center of the upper electrode layer 48 to the back side. In the pattern 3, ten connection portions 50 are arranged on the upper electrode layer 48 in five rows on the front side, five on the back side, and two rows. In the case of wire bonding, ten wires can be bonded in this way, but this is a complicated operation. Therefore, after bonding to the near side with a single wire, the wire is extended without cutting the wire, and the back side is bonded again, so that it can be realized with five wires.

図８の下段には、上段の配置に対応するチップ４４の温度上昇分布のシミュレーション結果が模式的に示されている。すなわち、パターン１のときは、チップ４４の中央部が最も温度上昇が大きいが、パターン２では、温度上昇分布が２分され、温度上昇が最も高くなるところの温度（最高温度上昇）もパターン１に比べると低くなることがわかる。パターン３では、さらに温度分布が平坦化する。   The lower part of FIG. 8 schematically shows the simulation result of the temperature rise distribution of the chip 44 corresponding to the upper arrangement. That is, in the case of pattern 1, the temperature rise is greatest at the center of the chip 44, but in pattern 2, the temperature rise distribution is divided into two and the temperature at which the temperature rise is highest (maximum temperature rise) is also the pattern 1. It turns out that it becomes low compared with. In pattern 3, the temperature distribution is further flattened.

図９は、図８の３つの接続部配置パターンのそれぞれについて、電流値を変化させたときの、チップ内の最高温度上昇を比較して示したものである。電流値としては、チップ全体としての電流を、５０Ａ，１００Ａ，１５０Ａと変化させた。このシミュレーション結果から、いずれの電流値においても、パターン２の最高温度上昇は、パターン１のそれよりも低く、パターン３の最高温度上昇は、さらに低くなっていることがわかる。図１０は、図９におけるパターン１とパターン２の結果をグラフ化したもので、明らかに、上部電極層４８内における接続部５０の配置条件で、チップ４４の最高温度上昇の値が異なることがわかる。   FIG. 9 shows a comparison of the maximum temperature rise in the chip when the current value is changed for each of the three connection portion arrangement patterns of FIG. As the current value, the current of the entire chip was changed to 50A, 100A, and 150A. From this simulation result, it can be understood that the maximum temperature rise of the pattern 2 is lower than that of the pattern 1 and the maximum temperature rise of the pattern 3 is further lower at any current value. FIG. 10 is a graph of the results of pattern 1 and pattern 2 in FIG. 9. Obviously, the maximum temperature rise value of the chip 44 varies depending on the arrangement condition of the connection portion 50 in the upper electrode layer 48. Recognize.

上記のように、通常の電流レベルを取り扱っている感覚からは、上部電極層のどの部位に電流が印加されても、導体中は電流が均一となり、チップ内部に一様に電流が流れてチップ内部の温度上昇も同じと考えられる。これに対し、シミュレーションでは、上部電極層内の電流印加部位、つまり接続部の配置により、チップの温度上昇分布が異なることがわかった。図１１と図１２は、そのメカニズムの１つのモデルである。図８の温度分布のシミュレーション結果では、どの配置パターンでもチップの周辺部の温度上昇が中央部に比べ低い。これは、図１１に示すように、チップ４４の端では熱流（ヒートフラックス）５２が四方八方に広がるため、熱抵抗が低くなるためと考えることができる。したがって、仮にチップ４４内部で均一に発熱が生じたとしても、チップ４４のコーナー部の温度上昇が最も低く、チップ４４重心部の温度上昇が最も高くなるものと考えられる。   As described above, from the sensation of handling a normal current level, no matter where the current is applied to the upper electrode layer, the current is uniform in the conductor, and the current flows uniformly inside the chip. The internal temperature rise is considered to be the same. On the other hand, in the simulation, it was found that the temperature rise distribution of the chip differs depending on the current application site in the upper electrode layer, that is, the arrangement of the connection portion. 11 and 12 are one model of the mechanism. In the simulation result of the temperature distribution in FIG. 8, the temperature rise in the peripheral portion of the chip is lower than that in the central portion in any arrangement pattern. As shown in FIG. 11, it can be considered that the heat flow (heat flux) 52 spreads in all directions at the end of the chip 44, so that the thermal resistance becomes low. Therefore, even if heat is uniformly generated inside the chip 44, it is considered that the temperature rise at the corner of the chip 44 is the lowest and the temperature rise at the center of gravity of the chip 44 is the highest.

もう１つは、上部電極層４８及びチップの内部のシリコンデバイスにおける抵抗分布の存在である。図１２に示すように、ワイヤ５４が上部電極層４８に接続される接続部５０から電流が印加され、上部電極層４８を介し、シリコンデバイス内部に流れる。上部電極層４８にも抵抗成分５６があり、シリコンデバイスにも抵抗成分５８があるので、接続部５０から電流が広がるにつれ電圧降下が生ずるが、その大きさは、抵抗成分５６，５８の大きさと流れる電流の大きさで決まる。上記のシミュレーションでは、チップ４４と回路基板４２との間は１００μｍの半田層と２００μｍのアルミニウム層であり、チップ４４の上部電極層４８は５μｍのアルミニウム層である。したがって、チップ４４の下部電極層側の抵抗は、上部電極層４８及びシリコンデバイスの抵抗に比べ無視できる。一方、上部電極層４８は、通常の電流レベルならば格別、大電流となると、その抵抗成分５６の分布が無視できなくなり、シリコンデバイスに注入される電流分布が接続部５０の配置の影響を受け、その結果、チップ４４内部の温度上昇分布が相違してくるものと考えられる。   The other is the presence of resistance distribution in the upper electrode layer 48 and the silicon device inside the chip. As shown in FIG. 12, a current is applied from the connection portion 50 where the wire 54 is connected to the upper electrode layer 48, and flows into the silicon device via the upper electrode layer 48. Since the upper electrode layer 48 also has the resistance component 56 and the silicon device also has the resistance component 58, a voltage drop occurs as the current spreads from the connection portion 50. The magnitude of the resistance component 56, 58 is the magnitude of the resistance component 56, 58. It depends on the magnitude of the current that flows. In the above simulation, a 100 μm solder layer and a 200 μm aluminum layer are provided between the chip 44 and the circuit board 42, and an upper electrode layer 48 of the chip 44 is a 5 μm aluminum layer. Therefore, the resistance on the lower electrode layer side of the chip 44 is negligible compared to the resistance of the upper electrode layer 48 and the silicon device. On the other hand, when the upper electrode layer 48 has a normal current level and becomes extremely large, the distribution of the resistance component 56 cannot be ignored, and the current distribution injected into the silicon device is affected by the arrangement of the connection portions 50. As a result, the temperature rise distribution inside the chip 44 is considered to be different.

このように、シミュレーションによれば、ワイヤボンディングの上部電極層内の配置条件によりチップ内の温度上昇がかなり異なる、との知見を得ることができた。この結果を実際に大電流用ダイオードにワイヤボンディングし、電流を印加し、温度上昇分布を調べてみたところ、後に詳述するが、よい一致を見た。   Thus, according to the simulation, it has been found that the temperature rise in the chip varies considerably depending on the arrangement conditions in the upper electrode layer of wire bonding. This result was actually wire-bonded to a high-current diode, current was applied, and the temperature rise distribution was examined. As will be described in detail later, good agreement was found.

このことから、一般的な電流レベルの半導体素子と異なり、電流が大きいために、上部電極層の抵抗の場所的分布の影響を受け、上部電極内における複数の接続部材の平面配置条件に依存して半導体素子の温度上昇分布が定まるような大電流用の半導体素子では、上部電極内における複数の接続部材の平面配置を工夫することで、温度上昇を抑制することが可能となることがわかる。大電流の１つの目安は、例えば、上部電極層４８が５μｍのアルミニウムの場合、図９の電流５０Ａである。   Therefore, unlike a general semiconductor element having a current level, since the current is large, it is affected by the local distribution of the resistance of the upper electrode layer and depends on the planar arrangement conditions of a plurality of connecting members in the upper electrode. Thus, it can be seen that in a semiconductor element for large current in which the temperature rise distribution of the semiconductor element is determined, the temperature rise can be suppressed by devising the planar arrangement of the plurality of connecting members in the upper electrode. One standard for the large current is, for example, the current 50A in FIG. 9 when the upper electrode layer 48 is 5 μm of aluminum.

具体的には、図８のパターン２のように、上部電極層の平面内全体に離散的に接続部を配置することで、一列に配置するのに比べ、最高温度上昇を抑制できる。ここで平面内全体に離散的とは、一列に配置することに対比するもので、例えばジグザク状に配置することである。また、図８のパターン３のように、各ワイヤの接続方向に略垂直な方向について各々略同一の面積を有する第１エリアと第２エリアに仮想的に２分し、各ワイヤを各々隣り合うワイヤ同士が異なるエリアに接続することで、一列に配置するのに比べ、最高温度上昇をさらに抑制できる。この配置は、各ワイヤのそれぞれが上部電極層との間で複数の接続部を形成するものである。   Specifically, as shown in pattern 2 in FIG. 8, the maximum temperature rise can be suppressed by disposing the connection portions discretely in the entire plane of the upper electrode layer as compared to arranging them in a line. Here, the term “discrete over the entire plane” is contrasted with arranging in a single line, for example, arranging in a zigzag pattern. Further, as shown in pattern 3 in FIG. 8, the wires are virtually divided into a first area and a second area each having substantially the same area in a direction substantially perpendicular to the connection direction of the wires, and the wires are adjacent to each other. By connecting the wires to different areas, the maximum temperature rise can be further suppressed as compared to arranging them in a line. This arrangement is such that each wire forms a plurality of connecting portions with the upper electrode layer.

以下に、実際の大電流用の半導体装置の構成等につき、図面を用いて詳細に説明する。以下の説明は、上記のシミュレーションの結果を確認するために行ったデバイス製作に基づくものであり、シミュレーションに用いたモデルと、寸法等をほぼ合わせてある。つまり、図３、図４で説明したように、放熱板／ハウジングケースの上に、ＤＢＡ回路基板を配置し、その上に６．５ｍｍ角で厚みが２００μｍの大電流用ダイオードのチップを取り付け、チップの上部電極層に複数のワイヤを接続して、大電流用の半導体装置としたものである。   Hereinafter, the configuration and the like of an actual semiconductor device for large current will be described in detail with reference to the drawings. The following description is based on the device fabrication performed for confirming the result of the above-mentioned simulation, and the model used for the simulation is substantially matched with the dimensions. That is, as described with reference to FIGS. 3 and 4, the DBA circuit board is disposed on the heat sink / housing case, and a 6.5 mm square and 200 μm thick diode chip for high current is mounted thereon. A plurality of wires are connected to the upper electrode layer of the chip to obtain a semiconductor device for large current.

図１３（ａ）は、シミュレーションにおけるパターン２をワイヤボンディングにより実現する様子を示す図である。なお、比較のためにパターン１に対応するものを図１３（ｂ）に示す。以下において、図３から図５、図１２と同様の要素には同一の符号を付し、詳細な説明を省略する。   FIG. 13A is a diagram illustrating a state in which the pattern 2 in the simulation is realized by wire bonding. For comparison, a pattern corresponding to pattern 1 is shown in FIG. In the following, the same elements as those in FIGS. 3 to 5 and 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

図１３（ａ）において、チップ４４は、大電流用ダイオードで、その寸法は上記のように６．５ｍｍ角、厚みは２００μｍである。上部電極層４８は、５．５ｍｍ角の面積で、直接ダイオードデバイスのシリコンに接触しており、厚みが５μｍのアルミニウムで構成される。上部電極層４８の上には、５本のワイヤ５４が接続部５０において接続される。ワイヤ５４は、直径が３００〜５００μｍのアルミニウムを主成分とするワイヤボンディング用ワイヤで、超音波ワイヤボンディング装置等で上部電極層４８にボンディングされる。ボンディング後のワイヤ５４と上部電極層４８との間の接続部５０の大きさは、図１３（ａ）のＸ方向に約１ｍｍ、Ｙ方向に約０．５ｍｍ程度である。   In FIG. 13A, a chip 44 is a large current diode, and its dimensions are 6.5 mm square and the thickness is 200 μm as described above. The upper electrode layer 48 has an area of 5.5 mm square, is in direct contact with the silicon of the diode device, and is made of aluminum having a thickness of 5 μm. On the upper electrode layer 48, five wires 54 are connected at the connection portion 50. The wire 54 is a wire bonding wire mainly composed of aluminum having a diameter of 300 to 500 μm, and is bonded to the upper electrode layer 48 by an ultrasonic wire bonding apparatus or the like. The size of the connecting portion 50 between the wire 54 after bonding and the upper electrode layer 48 is about 1 mm in the X direction and about 0.5 mm in the Y direction in FIG.

５本のワイヤ５４は、チップ４４の上部電極層４８において、２本と３本の２列となるように、いわゆるジグザク状に接続部５０を配置してボンディングされる。具体的には、５本のワイヤ５４において、そのＹ方向のピッチを約１ｍｍとし、Ｘ方向の列のオフセット量を例えば約２〜３ｍｍ程度とすることができる。このジグザグ配置により、図８のパターン２と同様のものとできる。なお、図１３（ｂ）は、５本のワイヤ５４をＹ方向に沿って１列としたもので、図１３（ａ）のＸ方向の列オフセット量をゼロにした配置で、図８のパターン１に相当する。   The five wires 54 are bonded in the upper electrode layer 48 of the chip 44 by arranging the connection portions 50 in a so-called zigzag shape so as to form two rows and two rows. Specifically, in the five wires 54, the pitch in the Y direction can be set to about 1 mm, and the offset amount of the rows in the X direction can be set to, for example, about 2 to 3 mm. By this zigzag arrangement, it can be the same as the pattern 2 in FIG. FIG. 13B shows five wires 54 arranged in one row along the Y direction, and the arrangement shown in FIG. Corresponds to 1.

図１３（ａ），（ｂ）の構成の大電流用ダイオードについて、実際に電流を印加したときのチップ４４の温度分布を実測し、図８から図１０で説明したシミュレーション結果と比較した。条件は以下のとおりである。すなわち、初期のチップ温度は２０℃、印加電流は、５本のワイヤ５４の合計で６０〜１００Ａの間で設定し、１ｓｅｃをオン時間、１９ｓｅｃをオフ時間とし、これを繰り返した。チップ４４の温度は赤外温度計を用いて測定し、電流印加のオン・オフを繰り返して温度が定常状態となったときのデータを採取した。   With respect to the large current diode having the configuration shown in FIGS. 13A and 13B, the temperature distribution of the chip 44 when the current was actually applied was measured and compared with the simulation results described with reference to FIGS. The conditions are as follows. That is, the initial chip temperature was set to 20 ° C., the applied current was set to 60 to 100 A in total for the five wires 54, 1 sec was set as the on time, and 19 sec was set as the off time. The temperature of the chip 44 was measured using an infrared thermometer, and data was collected when the temperature was in a steady state by repeatedly turning on and off the current application.

図１４は、図１３（ａ），（ｂ）の２つについて、印加電流１００Ａのときの実測温度上昇分布の様子と、図８で説明したシミュレーション結果の計算温度上昇分布の様子を比較して示したものである。明らかに、パターン１の場合とパターン２の場合で温度上昇分布が異なるのがわかり、パターン２の場合には温度上昇分布が２分されるのに対し、パターン１ではチップの中央部に集まって温度上昇が起こる。この様子は、計算結果とよく一致する。   FIG. 14 compares the measured temperature rise distribution when the applied current is 100 A and the calculated temperature rise distribution of the simulation result described in FIG. 8 for two of FIGS. 13 (a) and 13 (b). It is shown. Obviously, it can be seen that the temperature rise distribution differs between pattern 1 and pattern 2. In pattern 2, the temperature rise distribution is divided into two, whereas in pattern 1, it gathers at the center of the chip. A temperature rise occurs. This situation agrees well with the calculation result.

図１５は、実測の温度上昇分布について、印加電流を変化させ、温度上昇の最も大きいところの温度上昇（最高温度上昇）がどのように変わるかを見たものである。これからも、明らかにパターン２のほうがパターン１に比べ最高温度上昇の値が低くなる。また、図１５の実測曲線の形は、図１０の計算曲線の形によい一致を示す。このように、実測温度上昇分布と、計算温度上昇分布とは定性的によい一致をしており、この結果から、実測の温度上昇分布においても、上部電極層の平面内の接続部の配置条件により、相違が出ることがわかる。   FIG. 15 shows how the temperature rise (maximum temperature rise) where the temperature rise is greatest changes with respect to the actually measured temperature rise distribution by changing the applied current. From now on, the value of the maximum temperature rise is clearly lower in the pattern 2 than in the pattern 1. Further, the shape of the actual measurement curve in FIG. 15 shows a good agreement with the shape of the calculation curve in FIG. In this way, the measured temperature rise distribution and the calculated temperature rise distribution are in good qualitative agreement. From this result, even in the measured temperature rise distribution, the arrangement condition of the connection portion in the plane of the upper electrode layer It can be seen that there is a difference.

したがって、大電流用の半導体素子において、上部電極層の平面内で接続部をジグザグ配置することで、一列に接続部を配置するよりも温度上昇分布を平坦にでき、また最高温度上昇の値を抑制することができる。次に、大電流用の半導体素子について、さらに信頼性を向上させることができる方法について述べる。   Therefore, in a semiconductor device for large current, by arranging the connecting portions in a zigzag manner in the plane of the upper electrode layer, the temperature rise distribution can be made flat compared to arranging the connecting portions in a single row, and the maximum temperature rise value can be increased. Can be suppressed. Next, a method capable of further improving the reliability of a semiconductor element for large current will be described.

まず、接続部５０の面積を大きくすることで、信頼性を向上させることができる。図１６は、接続部５０の拡大図で、ワイヤ５４は、ボンディング装置のツールにより押しつぶされ、長さＬ、幅Ｗの大きさの略長楕円領域で、上部電極層４８との間で接続部５０を形成し、この領域で電流が印加される。接続部５０の面積の大きさは、図１７に示すように超音波探傷法により得ることができる。すなわち、ワイヤ５４により接続部５０が形成されたチップ４４を、適当な液体媒体槽６０の中に配置し、裏側から超音波プローブ６２により超音波を送信し、反射波を受け取ってこれを画像処理し超音波探傷表示装置６４に表示する。接続部５０とそれ以外のところでは超音波の反射の様相が異なるので、その相違から接続部５０の輪郭を求め、その面積を得ることができる。   First, the reliability can be improved by increasing the area of the connecting portion 50. FIG. 16 is an enlarged view of the connection portion 50, and the wire 54 is crushed by the tool of the bonding apparatus and is a substantially elliptical region having a length L and a width W, and is connected to the upper electrode layer 48. 50 and current is applied in this region. The size of the area of the connecting portion 50 can be obtained by an ultrasonic flaw detection method as shown in FIG. That is, the chip 44 in which the connection part 50 is formed by the wire 54 is placed in an appropriate liquid medium tank 60, ultrasonic waves are transmitted from the back side by the ultrasonic probe 62, and reflected waves are received and processed. And displayed on the ultrasonic flaw detection display device 64. Since the aspect of ultrasonic reflection is different between the connecting portion 50 and other portions, the contour of the connecting portion 50 can be obtained from the difference and the area thereof can be obtained.

接続部５０の面積が大きいほうが、接続部５０における電流密度を低下させることができるので好ましい。その形状はボンディング装置のツール形状やボンディング条件で変えることができるが、一般的には長さＬが幅Ｗに対して大きくなる。その比は、例えば、剥離強度等の基準で評価でき、例えば、長さＬは、幅Ｗの２．４倍以上あることが好ましい。   A larger area of the connection part 50 is preferable because the current density in the connection part 50 can be reduced. The shape can be changed depending on the tool shape of the bonding apparatus and bonding conditions. Generally, the length L is larger than the width W. The ratio can be evaluated by criteria such as peel strength, and for example, the length L is preferably 2.4 times the width W or more.

図１８は、接続部の面積が、大電流の半導体素子の冷熱サイクルテストの進展に従いどのように変化するかを示す図である。横軸は冷熱サイクルテストのサイクル数、縦軸は接続部面積である。このように、冷熱サイクルテストを繰り返すと、次第に接続部の面積が減少してくることがわかる。接続部の面積が減れば、接続部における電流密度が高くなり、そこでの発熱が大きくなり、チップ全体の温度上昇が高くなる。したがって、冷熱サイクルテストが所定レベルの繰り返し数を合格するためにも、また、チップ全体の温度上昇を抑制するためにも、接続部の初期面積は大きいほうがよい。その初期面積の大きさは、冷熱サイクルを合格するためのサイクル数のときにおける接続部の面積減少率と、接続部での発熱等からくる最小面積の条件等から求めることができる。例えば、最小面積を０．５ｍｍ×０．５ｍｍ＝０．２５ｍｍ2とし、冷熱サイクル合格サイクル数での面積減少率を初期の０．５とすると、初期の接続部の面積は、０．５ｍｍ2以上あることが必要となる。 FIG. 18 is a diagram showing how the area of the connection portion changes in accordance with the progress of the thermal cycle test of the high-current semiconductor element. The horizontal axis represents the number of cycles of the thermal cycle test, and the vertical axis represents the connection area. Thus, it can be seen that the area of the connection portion gradually decreases when the cooling / heating cycle test is repeated. If the area of the connection portion is reduced, the current density at the connection portion is increased, heat generation therein is increased, and the temperature rise of the entire chip is increased. Therefore, it is better that the initial area of the connection portion is large so that the thermal cycle test passes a predetermined number of repetitions and also the temperature rise of the entire chip is suppressed. The size of the initial area can be obtained from the area reduction rate of the connection portion when the number of cycles for passing the cooling cycle, the minimum area condition resulting from the heat generation at the connection portion, and the like. For example, assuming that the minimum area is 0.5 mm × 0.5 mm = 0.25 mm 2 and the area reduction rate in the number of passing cycles of the cooling and heating cycle is 0.5 at the initial stage, the area of the initial connection portion is 0.5 mm 2. It is necessary to have the above.

次に、図１９に示すように、各ワイヤ５４について上部電極層４８上で２つの接続部７０，７２を形成することで、チップ４４全体の温度上昇分布をより均一にできる。これは、図８のパターン３に相当する接続部７０，７２の配置だからである。具体的には、上部電極層４８の平面内で、図１９に示すＸ方向の２箇所のところでそれぞれ５箇所の接続部を設ける。ワイヤボンディング作業では、−Ｘ方向からワイヤ５４を＋Ｘ方向に運んできて、まず上部電極層４８の左側の方で１つ目の接続部７０を形成し、そのままワイヤ５４を切断せずに一旦上方にあげつつ＋Ｘ方向に運び、上部電極層４８の右側のほうで下方に下ろしてそこで２つ目の接続部７２を形成し、そこでワイヤ５４を切断する。   Next, as shown in FIG. 19, by forming two connection portions 70 and 72 on the upper electrode layer 48 for each wire 54, the temperature rise distribution of the entire chip 44 can be made more uniform. This is because the connection portions 70 and 72 corresponding to the pattern 3 in FIG. 8 are arranged. Specifically, in the plane of the upper electrode layer 48, five connection portions are provided at two locations in the X direction shown in FIG. In the wire bonding operation, the wire 54 is carried in the + X direction from the −X direction, and firstly the first connection portion 70 is formed on the left side of the upper electrode layer 48, and the wire 54 is not cut as it is. Then, it is carried down in the + X direction and lowered downward on the right side of the upper electrode layer 48 to form the second connection portion 72 there, and the wire 54 is cut there.

つまり、電流印加は、５本のワイヤ５４に分担されて行われるが、１本のワイヤ５４では、それぞれ２つの接続部７０，７２によってさらに分担されて上部電極層４８、すなわちチップ４４に電流が印加されることになる。したがって、図８で、図９で説明したように、チップ４４の温度上昇分布がより平坦化し、最高温度上昇の値がより抑制される。また、接続部７０，７２における電流密度が低くなるので、接続部７０，７２における発熱も抑制できる。   In other words, the current application is performed by being shared by the five wires 54, but in the single wire 54, the current is further shared by the two connection portions 70 and 72, and the current is applied to the upper electrode layer 48, that is, the chip 44. Will be applied. Therefore, in FIG. 8, as described with reference to FIG. 9, the temperature rise distribution of the chip 44 is further flattened, and the maximum temperature rise value is further suppressed. Moreover, since the current density in the connection parts 70 and 72 becomes low, the heat generation in the connection parts 70 and 72 can also be suppressed.

２つの接続部７０，７２の間では、あとでボンディングされる２列目の接続部７２のほうに電流が流れにくくなる。したがって、２列目の接続部７２の接続部面積を、１列目の接続部７０の接続部面積より大きめにすることが好ましい。   Between the two connection portions 70 and 72, the current hardly flows to the connection portion 72 in the second row to be bonded later. Therefore, it is preferable to make the connection area of the connection part 72 in the second row larger than the connection part area of the connection part 70 in the first row.

また、図１９に示す１列目の接続部７０と２列目の接続部７２との間のワイヤループは、高さＨと、列間の間隔Ｓの比、（Ｈ／Ｓ）を大きくするほうが信頼性を向上させることができる。すなわち、図２０は、（Ｈ／Ｓ）を変化させて、冷熱サイクルテストの進展により接続部の面積減少の様子を見た図であるが、（Ｈ／Ｓ）が大きいほど、接続部の面積減少は抑制される。ただし、あまりループを高くすると、切断が起こるので、それ以内の（Ｈ／Ｓ）にする必要がある。   In addition, the wire loop between the connection part 70 in the first row and the connection part 72 in the second row shown in FIG. 19 increases the ratio of the height H to the spacing S between the rows, (H / S). The reliability can be improved. That is, FIG. 20 is a diagram showing a state in which the area of the connection portion is decreased by changing the (H / S) and progressing in the thermal cycle test. The larger the (H / S), the larger the area of the connection portion. The decrease is suppressed. However, if the loop is made too high, cutting occurs, so it is necessary to make it within (H / S).

このように、大電流用の半導体素子における接続部の配置、本数、その面積等を工夫することで、温度上昇を抑制し、信頼性を向上させることができるが、図２に説明したシミュレータ等を用い、シミュレーションと実測とを組み合わせることで、さらに性能のよい大電流用の半導体装置を得ることができる。図２１は、シミュレータを用いて、温度上昇分布等を最適化する方法のフローチャートである。   In this way, by devising the arrangement, number, area, and the like of the connection portions in the semiconductor element for large current, the temperature rise can be suppressed and the reliability can be improved. Using a combination of simulation and actual measurement, a semiconductor device for large current with better performance can be obtained. FIG. 21 is a flowchart of a method for optimizing a temperature rise distribution or the like using a simulator.

最初に、シミュレータの初期境界条件を設定する（Ｓ１０）。具体的には、図３、図４、図６等の初期設定を行う。次に、接続部の配置を設定する（Ｓ１２）。具体的には、図５に示すように、上部電極層４８の平面内での接続部５０の配置状態を設定する。例えば図８のパターン２、パターン３等のように接続部の本数と配置位置の設定をする。これに加え、図１８、図２０等で説明した接続部面積の知識を加えることもできる。   First, an initial boundary condition of the simulator is set (S10). Specifically, the initial settings of FIG. 3, FIG. 4, FIG. Next, the arrangement of the connecting portions is set (S12). Specifically, as shown in FIG. 5, the arrangement state of the connection portions 50 in the plane of the upper electrode layer 48 is set. For example, the number of connection portions and the arrangement position are set as in pattern 2 and pattern 3 in FIG. In addition to this, it is also possible to add knowledge of the connection area described with reference to FIGS.

そして、シミュレーションを実行する（Ｓ１４）。具体的には、上記式（１）、（２）等を解き、その結果をチップ内の温度上昇分布データとして出力する。シミュレーションの結果を見て、温度上昇が所望のように抑制されているかを判断し（Ｓ１６）、ＮＧのときは再びＳ１２へ戻り、接続部の設定をやり直し、シミュレーションを改めて実行する。シミュレーション上で温度上昇が所望のように抑制され、ＯＫとなると、そのシミュレーションモデルに従った大電流用の半導体素子を実際に試作する（Ｓ１８）。そして、実際に電流印加等の駆動を行い、チップの温度上昇を実測する（Ｓ２０）。その結果を見て、温度上昇が所望のように抑制されているかを判断し（Ｓ２２）、ＮＧのときは再びＳ１２へ戻り、接続部の設定をやり直し、シミュレーション等を改めて実行する。   Then, a simulation is executed (S14). Specifically, the above equations (1) and (2) are solved, and the result is output as temperature rise distribution data in the chip. By looking at the result of the simulation, it is determined whether or not the temperature rise is suppressed as desired (S16). If it is NG, the process returns to S12 again, the setting of the connecting portion is performed again, and the simulation is executed again. When the temperature rise is suppressed as desired in the simulation and becomes OK, a semiconductor device for large current according to the simulation model is actually prototyped (S18). Then, actual driving such as current application is performed to actually measure the temperature rise of the chip (S20). By looking at the result, it is determined whether or not the temperature rise is suppressed as desired (S22). If it is NG, the process returns to S12 again, the connection portion is set again, and the simulation is executed again.

このように、シミュレーションと実測とを繰り返すことで、シミュレーションの精度が次第に上がってくると、Ｓ１８の段階がそのままで大電流用の半導体装置の製作に移行できる。こうして、電流が大きいために、上部電極層の抵抗の場所的分布の影響を受け、上部電極内における複数の接続部材の平面配置条件に依存して半導体素子の温度上昇分布が定まる大電流用の半導体素子について、最適の接続部材の平面配置条件を定めることができる。   In this way, by repeating the simulation and the actual measurement, when the accuracy of the simulation gradually increases, it is possible to proceed to manufacture of a semiconductor device for large current without changing the step S18. Thus, since the current is large, the temperature rise distribution of the semiconductor element is determined depending on the planar arrangement conditions of the plurality of connecting members in the upper electrode due to the influence of the local distribution of the resistance of the upper electrode layer. The optimal planar arrangement condition of the connecting member can be determined for the semiconductor element.

上記において、チップは、大電流用ダイオードとしたが、シミュレーション結果からわかるように、デバイスの種類はダイオードに限られず、半導体素子の上部接触領域に設けられる上部電極層に複数の電流印加用接続部材が接続され、電流が大きいために、上部電極層の抵抗の場所的分布の影響を受け、上部電極内における複数の接続部材の平面配置条件に依存して半導体素子の温度上昇分布が定まる大電流用の半導体素子であればよい。例えば、大電流が上部電極と下部電極との間で流れるラテラル型半導体素子であれば、ｐｎ接合が１つのものに限られない。あるいは、チップの上面に複数の種類の電極が設けられる半導体素子であっても、電流を出し入れする上部電極層が、半導体素子の上部接触領域に直接設けられ、電流が大きいために、上部電極層の抵抗の場所的分布の影響を受け、上部電極内における複数の接続部材の平面配置条件に依存して半導体素子の温度上昇分布が定まるものであれば、同様に本発明が実施できる。   In the above, the chip is a large current diode, but as can be seen from the simulation results, the type of device is not limited to the diode, and a plurality of current application connecting members are provided on the upper electrode layer provided in the upper contact region of the semiconductor element. Is connected, and the current is large, so that the temperature rise distribution of the semiconductor element is determined depending on the planar arrangement conditions of the plurality of connecting members in the upper electrode due to the influence of the local distribution of the resistance of the upper electrode layer Any semiconductor element may be used. For example, the pn junction is not limited to one as long as it is a lateral type semiconductor element in which a large current flows between the upper electrode and the lower electrode. Alternatively, even in a semiconductor element in which a plurality of types of electrodes are provided on the upper surface of the chip, since the upper electrode layer for taking in and out the current is directly provided in the upper contact region of the semiconductor element and the current is large, the upper electrode layer The present invention can be similarly implemented as long as the temperature rise distribution of the semiconductor element is determined depending on the planar arrangement conditions of the plurality of connection members in the upper electrode under the influence of the local distribution of resistance.

また、チップの上部電極層に接続されるのはワイヤとして説明したが、シミュレーションの結果からわかるように、上部電極層内における複数の接続部の平面配置条件で温度上昇分布が決まるのであるから、ワイヤ以外の接続部材であってもよい。例えば、ビーム状のリードで接続してもよく、バンプを用いて接続してもよい。   In addition, the wire connected to the upper electrode layer of the chip has been described as a wire, but as can be seen from the simulation results, the temperature rise distribution is determined by the planar arrangement conditions of the plurality of connecting portions in the upper electrode layer. A connecting member other than a wire may be used. For example, it may be connected with a beam-like lead or may be connected using a bump.

本発明に係る実施の形態の半導体装置が適用される車両用インバータ回路の構成を示す図である。It is a figure which shows the structure of the inverter circuit for vehicles to which the semiconductor device of embodiment which concerns on this invention is applied. 本発明に係る実施の形態のシミュレーションにおいて、シミュレータの構成を示す図である。It is a figure which shows the structure of a simulator in the simulation of embodiment which concerns on this invention. 本発明に係る実施の形態のシミュレーションにおいて、検討した大電流用の半導体装置の上面構造図である。It is the upper surface structure figure of the semiconductor device for large currents examined in the simulation of the embodiment concerning the present invention. 本発明に係る実施の形態のシミュレーションにおいて、検討した大電流用の半導体装置の断面図である。It is sectional drawing of the semiconductor device for large currents examined in the simulation of embodiment which concerns on this invention. 本発明に係る実施の形態のシミュレーションにおいて、検討したチップの平面図である。It is a top view of the chip | tip examined in the simulation of embodiment which concerns on this invention. 本発明に係る実施の形態のシミュレーションにおいて、用いた主なパラメータの値を示すものである。The values of main parameters used in the simulation of the embodiment according to the present invention are shown. 本発明に係る実施の形態のシミュレーションの様子を示す図で、（ａ）は配置構成の斜視図、（ｂ）は回路基板上の電流分布、（ｃ）は半導体装置全体の温度上昇分布を模式的に示すものである。It is a figure which shows the mode of simulation of embodiment which concerns on this invention, (a) is a perspective view of arrangement | positioning structure, (b) is a current distribution on a circuit board, (c) is a temperature rise distribution of the whole semiconductor device. It is shown as an example. 本発明に係る実施の形態のシミュレーションにおいて、接続部の配置と温度上昇分布の関係を示す図である。It is a figure which shows the relationship between arrangement | positioning of a connection part, and temperature rise distribution in the simulation of embodiment which concerns on this invention. 本発明に係る実施の形態のシミュレーションにおいて、接続部の配置により、電流値に対するチップ内の最高温度上昇が異なる様子を示す図である。It is a figure which shows a mode that the maximum temperature rise in a chip | tip with respect to an electric current value changes with simulation of embodiment which concerns on this invention by arrangement | positioning of a connection part. 図９におけるパターン１とパターン２の結果をグラフ化したものである。FIG. 10 is a graph of the results of pattern 1 and pattern 2 in FIG. 9. 本発明に係る実施の形態のシミュレーションの結果に対するモデルの１つを説明する図である。It is a figure explaining one of the models with respect to the result of the simulation of embodiment which concerns on this invention. 本発明に係る実施の形態のシミュレーションの結果に対するモデルの他の１つを説明する図である。It is a figure explaining other one of the models with respect to the result of the simulation of an embodiment concerning the present invention. 本発明に係る実施の形態において、上部電極層内でジグザク状にワイヤボンディングを行う様子を１列の配置と比較して示す図である。In embodiment which concerns on this invention, it is a figure which shows a mode that wire bonding is performed zigzag in the upper electrode layer compared with arrangement | positioning of 1 row. 本発明に係る実施の形態において、接続部の配置の違いにより、実測温度上昇分布が異なる様子をシミュレーション結果と比較して示す図である。In embodiment which concerns on this invention, it is a figure which shows a mode that measured temperature rise distribution differs by the difference in arrangement | positioning of a connection part with a simulation result. 本発明に係る実施の形態において、接続部の配置により、電流値に対するチップ内の最高温度上昇が異なる様子を示す図である。In embodiment which concerns on this invention, it is a figure which shows a mode that the highest temperature rise in a chip | tip with respect to an electric current value changes with arrangement | positioning of a connection part. 接続部の拡大図である。It is an enlarged view of a connection part. 接続部の面積の大きさを超音波探傷法により得る様子を示す図である。It is a figure which shows a mode that the magnitude | size of the area of a connection part is obtained by the ultrasonic flaw detection method. 接続部の面積が、大電流用の半導体素子の冷熱サイクルテストの進展に従いどのように変化するかを示す図である。It is a figure which shows how the area of a connection part changes according to progress of the thermal cycle test of the semiconductor element for large currents. 他の実施の形態において、各ワイヤについて上部電極層上で２つの接続部を形成する様子を示す図である。In other embodiment, it is a figure which shows a mode that two connection parts are formed on an upper electrode layer about each wire. 図９における（Ｈ／Ｓ）を変化させて、冷熱サイクルテストの進展によりどのように接続部の面積が減少するかを示す図である。It is a figure which shows how the area of a connection part reduces by progress of a thermal cycle test by changing (H / S) in FIG. シミュレータを用いて、温度上昇分布等を最適化する方法のフローチャートである。It is a flowchart of the method of optimizing temperature rise distribution etc. using a simulator.

符号の説明Explanation of symbols

８ 車両用モータ、１０ 車両用インバータ回路、１４ 大電流用ダイオード、１６ 車両用電池、２０ シミュレータ、４０ ハウジングケース、４２ 回路基板、４４ チップ、４６ 電流出力口、４８ 上部電極層、５０，７０，７２ 接続部、５２ 熱流（ヒートフラックス）、５４ ワイヤ、５６，５８ 抵抗成分。   8 Vehicle Motor, 10 Vehicle Inverter Circuit, 14 Large Current Diode, 16 Vehicle Battery, 20 Simulator, 40 Housing Case, 42 Circuit Board, 44 Chip, 46 Current Output Port, 48 Upper Electrode Layer, 50, 70, 72 connections, 52 heat flow (heat flux), 54 wires, 56, 58 resistance components.

Claims (4)

基板に半導体素子の下部電極を配置し、この半導体素子の上部接触領域に設けられた上部電極層に電流印加用の接続部材を複数接続する半導体装置であって、
前記半導体素子の上部電極層の平面内全体に前記接続部材を離散的に接続し、半導体素子に電流を印加する際に前記上部電極層中の内部抵抗の発熱によって生じる半導体素子全体の温度上昇分布が、前記平面内全体において略均一化するようにしたことを特徴とする半導体装置。 A semiconductor device in which a lower electrode of a semiconductor element is disposed on a substrate, and a plurality of connection members for applying current are connected to an upper electrode layer provided in an upper contact region of the semiconductor element,
A temperature rise distribution of the entire semiconductor element caused by heat generation of internal resistance in the upper electrode layer when the connection member is discretely connected to the entire plane of the upper electrode layer of the semiconductor element and a current is applied to the semiconductor element. Is substantially uniform over the entire plane. 前記半導体素子の上部電極層の平面を、前記接続部材を接続する方向に略垂直な方向について、各々略同一面積を有する第１エリア及び第２エリアに仮想的に２分し、前記接続部材を、各々隣り合う接続部材同士が異なるエリアに接続されるように接続することを特徴とする請求項１に記載の半導体装置。   The plane of the upper electrode layer of the semiconductor element is virtually divided into a first area and a second area each having substantially the same area in a direction substantially perpendicular to a direction in which the connection member is connected, and the connection member is 2. The semiconductor device according to claim 1, wherein the connection members adjacent to each other are connected so as to be connected to different areas. 上部電極層はアルミニウムであり、上部電極層全体に印加される電流と上部電極層の厚みとの比が、１０Ａ／μｍ以上であることを特徴とする請求項１又は請求項２に記載の半導体装置。   3. The semiconductor according to claim 1, wherein the upper electrode layer is made of aluminum, and a ratio of a current applied to the entire upper electrode layer to a thickness of the upper electrode layer is 10 A / μm or more. apparatus. 接続部材は、ワイヤボンディング用のワイヤであることを特徴とする請求項１又は請求項２に記載の半導体装置。

The semiconductor device according to claim 1, wherein the connection member is a wire for wire bonding.

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Cited By (9)

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JP2008186957A (en) * 2007-01-29 2008-08-14 Honda Motor Co Ltd Semiconductor device and manufacturing method thereof
WO2012062300A3 (en) * 2010-10-12 2012-07-12 Technische Universität Berlin Thick-wire bond arrangement and method for producing same
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US9418916B2 (en) 2013-01-25 2016-08-16 Fuji Electric Co., Ltd. Semiconductor device
WO2016142372A1 (en) * 2015-03-12 2016-09-15 Infineon Technologies Bipolar Gmbh & Co. Kg Power semiconductor module with improved bonding connection structure
JP2017017105A (en) * 2015-06-29 2017-01-19 株式会社デンソー Semiconductor device
JP2020503688A (en) * 2016-12-28 2020-01-30 シーメンス アクチエンゲゼルシヤフトＳｉｅｍｅｎｓ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ Semiconductor module having first and second connection elements for connecting semiconductor chips and manufacturing method
US11270970B2 (en) 2019-10-21 2022-03-08 Fuji Electric Co., Ltd. Semiconductor device
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JP2008186957A (en) * 2007-01-29 2008-08-14 Honda Motor Co Ltd Semiconductor device and manufacturing method thereof
WO2012062300A3 (en) * 2010-10-12 2012-07-12 Technische Universität Berlin Thick-wire bond arrangement and method for producing same
US9992861B2 (en) 2010-10-12 2018-06-05 Technische Universität Berlin Heavy-wire bond arrangement and method for producing same
US9418916B2 (en) 2013-01-25 2016-08-16 Fuji Electric Co., Ltd. Semiconductor device
EP2802007A1 (en) * 2013-05-08 2014-11-12 ABB Technology AG Power semiconductor module
WO2016142372A1 (en) * 2015-03-12 2016-09-15 Infineon Technologies Bipolar Gmbh & Co. Kg Power semiconductor module with improved bonding connection structure
JP2017017105A (en) * 2015-06-29 2017-01-19 株式会社デンソー Semiconductor device
JP2020503688A (en) * 2016-12-28 2020-01-30 シーメンス アクチエンゲゼルシヤフトＳｉｅｍｅｎｓ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ Semiconductor module having first and second connection elements for connecting semiconductor chips and manufacturing method
JP7026688B2 (en) 2016-12-28 2022-02-28 シーメンス アクチエンゲゼルシヤフト Semiconductor module and manufacturing method including first and second connecting elements for connecting semiconductor chips
US11837571B2 (en) 2016-12-28 2023-12-05 Siemens Aktiengesellschaft Semiconductor module comprising a first and second connecting element for connecting a semiconductor chip, and also production method
US11270970B2 (en) 2019-10-21 2022-03-08 Fuji Electric Co., Ltd. Semiconductor device
JP7380071B2 (en) 2019-10-21 2023-11-15 富士電機株式会社 semiconductor equipment
EP3993034A1 (en) * 2020-10-28 2022-05-04 Renesas Electronics Corporation Semiconductor device

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