JP6471130B2 - 半導体装置およびセキュリティシステム - Google Patents
半導体装置およびセキュリティシステム Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 110
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- G—PHYSICS
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3226—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using a predetermined code, e.g. password, passphrase or PIN
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
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- G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Semiconductor Integrated Circuits (AREA)
- Storage Device Security (AREA)
- Quality & Reliability (AREA)
Description
図の例では、アドレス1の動作情報は、高温で動作されたとき「0」であるが、室温および低温で動作されたとき「1」である。また、アドレス5の動作情報は、低温で動作されたとき「1」であるが、室温および高温で動作されたとき「0」である。さらにアドレスCの動作情報は、低温で動作されたとき「0」であるが、室温および高温で動作されたとき「1」である。
200:半導体装置
210:入出力部
220:制御部
230:コード生成用回路
240:不揮発性記憶部
242:コード情報
Claims (16)
- 基板上に形成された回路または回路素子を複数の動作環境で動作させたときの固有情報を生成する生成手段であって、当該固有情報は、複数の動作環境の各々においてnビットの動作情報を含む、前記生成手段と、
前記複数の動作環境で動作されたときのnビットの動作情報を演算処理することで、複数の動作環境で動作させたときに同じ結果を生じる安定情報と、前記複数の動作環境で動作させたときに異なる結果を生じる不定情報とを識別する識別情報を検出する検出手段と、
前記検出手段の検出結果に基づき、前記安定情報および前記不定情報を含むnビットのコード列と、当該コード列に含まれる不定情報を識別する前記識別情報とを含むコード情報を生成し、当該コード情報を不揮発性の記憶領域に記憶する記憶手段と、
前記コード情報を読出し、読み出した前記コード情報を外部へ出力可能な読出し手段と、
を有する半導体装置。 - 半導体装置はさらに、前記記憶手段に記憶された前記コード情報を消去する消去手段を含む、請求項1に記載の半導体装置。
- 前記消去手段は、外部からの要求に応答して前記コード情報を消去する、請求項2に記載の半導体装置。
- 前記読出し手段は、前記消去手段により前記コード情報が消去された後に、外部から固有情報の要求があったとき、前記生成手段により生成された前記コード情報を外部へ出力する、請求項1に記載の半導体装置。
- 前記記憶手段は、コンフィギュレーションレジスタに設定されたアドレスに従い前記コード情報を記憶する、請求項1ないし4いずれか1つに記載の半導体装置。
- 前記複数の動作環境は、異なる環境温度での動作を含む、請求項1に記載の半導体装置。
- 前記複数の動作環境は、異なる電源電圧での動作を含む、請求項1に記載の半導体装置。
- 前記生成手段は、複数の動作環境で動作可能な回路を含み、当該回路は、nビットの固有情報を生成し、前記検出手段は、nビットの中から前記不定情報のビット位置を識別する、請求項1に記載の半導体装置。
- 前記安定情報は、前記複数の動作環境で動作されたとき全てが「0」または「1」のいずれかであり、前記不定情報は、前記複数の動作環境で動作されたとき「0」と「1」とを含む、請求項1ないし4いずれか1つに記載の半導体装置。
- 前記生成手段は、テストモードのときに複数の動作環境で動作される、請求項1ないし5いずれか1つに記載の半導体装置。
- 前記生成手段は、一対のインバータを有するn組のインバータ回路と、一対のインバータの出力電圧を比較するn組の比較回路と、n組の比較回路の比較結果に基づくnビットの固有情報を生成する生成部とを含み、一対のインバータのゲートには、インバータに供給される電圧の1/2の電圧が供給される、請求項1に記載の半導体装置。
- 請求項1ないし12いずれか1つに記載の半導体装置と、当該半導体装置と接続可能なホスト装置とをシステムであって、
ホスト装置は、
半導体装置から受け取った前記コード情報を格納する格納手段と、
前記コード情報に基づき半導体装置の認証を行う認証手段とを含む、システム。 - 前記認証手段は、前記識別情報に基づき前記コード情報の中から前記安定情報を抽出し、抽出された安定情報に基づき半導体装置の認証を行う、請求項12に記載のシステム。
- ホスト装置は、前記コード情報を格納した後、半導体装置に対して前記コード情報の削除を要求する手段を含む、請求項12または13に記載のシステム。
- 前記認証手段は、前記抽出された安定情報を変化させる手段を含む、請求項13に記載のシステム。
- 前記変化させる手段は、前記抽出された安定情報にランダム性を与える、請求項15に記載のシステム。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016182782A JP6471130B2 (ja) | 2016-09-20 | 2016-09-20 | 半導体装置およびセキュリティシステム |
CN201710754786.XA CN107844715B (zh) | 2016-09-20 | 2017-08-29 | 半导体装置及安全系统 |
KR1020170114748A KR102037576B1 (ko) | 2016-09-20 | 2017-09-07 | 반도체 장치 및 보안 시스템 |
TW106130790A TWI645703B (zh) | 2016-09-20 | 2017-09-08 | 半導體裝置及安全系統 |
US15/710,358 US10554422B2 (en) | 2016-09-20 | 2017-09-20 | Semiconductor device and security system |
US16/725,345 US11075770B2 (en) | 2016-09-20 | 2019-12-23 | Semiconductor device and security system |
US16/725,486 US11070384B2 (en) | 2016-09-20 | 2019-12-23 | Semiconductor device and security system |
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JP2016182782A JP6471130B2 (ja) | 2016-09-20 | 2016-09-20 | 半導体装置およびセキュリティシステム |
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JP6471130B2 true JP6471130B2 (ja) | 2019-02-13 |
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JP (1) | JP6471130B2 (ja) |
KR (1) | KR102037576B1 (ja) |
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TW (1) | TWI645703B (ja) |
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