JP6437767B2 - Synchronization establishment system and synchronization establishment method - Google Patents

Description

  The present invention relates to a synchronization establishment system and a synchronization establishment method, and more particularly to a synchronization establishment system and a synchronization establishment method in the case where a duplexed circuit is included.

  A general exchange includes a time-division switch circuit, a circuit having an interface connected to a public network (hereinafter referred to as a trunk circuit), a circuit having an interface for connecting a digital telephone, an analog telephone, an IP telephone, and the like (hereinafter referred to as a trunk circuit). And a control circuit for connecting the time-division switch circuit and the line / trunk circuit (hereinafter referred to as a multiple control circuit).

  The time-division switch circuit has a time-division switch function for controlling a speech path, and controls transmission / reception of pulse code modulation (PCM) data such as voice data, switch control of a speech, and the like. The time-division switch circuit further generates a clock serving as a reference for transmission / reception of PCM data, and generates and outputs a frame head indicating the head of a frame of PCM data. On the other hand, the multiplex control circuit distributes the clock, frame head, PCM data, etc. input from the time division switch circuit to each line / trunk circuit.

  Therefore, in the exchange, the reliability of the exchange is improved by duplicating the time division switch circuit and the multiplex control circuit. On the other hand, when the time-division switch circuit and the multiplex control circuit are duplicated, when switching between the active system and the standby system, PCM data errors due to switching are minimized, and voice noise is suppressed (data loss is prevented). There is a need. For example, Patent Documents 1 and 2 disclose techniques for suppressing the occurrence of data errors in PCM data at the time of system switching in an exchange in which a time division switch circuit and a multiplex control circuit are duplicated.

  Patent Document 1 discloses various synchronizations for extracting data of its own channel directly from four reference clocks output from a master device such as a time division switch circuit and a multiplex control circuit in a slave device such as a line / trunk circuit. A technique is disclosed in which a system is switched at an appropriate timing by generating a signal to suppress occurrence of a data error.

  On the other hand, in Patent Document 2, when an ACT (activation) bit for identification is added to a fixed-length data unit (cell) that has passed through the active system, data is acquired from both the active system and the standby system. A technique for discriminating between an active system and a standby system is disclosed. By selecting the data to which the ACT bit is added in the slave device, it is possible to appropriately acquire the data without causing a data error even when the system is switched.

Japanese Patent Laid-Open No. 5-111083 Japanese Patent Laid-Open No. 9-064885

  However, in the slave device, when generating various synchronization signals for extracting the data of the own channel directly from the reference clock output from the master device, the system is switched in consideration of the situation of the four reference clocks. Convenience is bad because it is necessary.

  On the other hand, when the ACT bit for identification is added to the data unit, the data unit is shared by the PCM data and the ACT bit, and the bit rate is lowered. In order to maintain the bit rate, it is necessary to add a data unit (signal line) for ACT bits separately, which increases the circuit scale.

  The present invention relates to a synchronization establishment system and a synchronization establishment method in which a main device circuit is duplicated, and even when the main device circuit system is switched at a desired timing, the control load and the circuit scale are not increased. It is an object of the present invention to provide a synchronization establishment system and synchronization establishment method that can minimize errors.

  In order to achieve the above object, a synchronization establishment system according to the present invention includes a first control circuit, a second control circuit, and a plurality of interface circuits connected to one of the control circuits. The first control circuit and the second control circuit respectively generate clock output means for generating and outputting a reference clock, frame head generation means for generating a frame head indicating the head of the frame, and at predetermined intervals using the reference clock. Adjustment signal generating means for generating an adjustment signal and inserting and outputting the signal at a predetermined position of the frame head. Each of the plurality of interface circuits is counted up each time a reference clock is input, and the adjustment signal is input. Synchronization with a control circuit connected using a bit counter that is cleared when the adjustment signal is input and a ch counter that is counted up each time an adjustment signal is input and cleared when the frame head is input. take.

  In order to achieve the above object, a synchronization establishment method according to the present invention is a synchronization establishment method in a first control circuit and a second control circuit, and a plurality of interface circuits connected to one of the control circuits. In the control circuit, a reference clock is generated and output, a frame head indicating the head of the frame is generated, an adjustment signal is generated at a predetermined interval using the reference clock, and inserted into a predetermined position of the frame head. In the interface circuit, the bit counter is counted up every time the reference clock is input and cleared when the adjustment signal is input, and is counted up every time the adjustment signal is input, and the frame head is input. Thus, the ch counter that is cleared is synchronized with the control circuit connected based on the channel counter.

  According to the aspect of the present invention described above, in the synchronization establishment system and the synchronization establishment method in which the main apparatus circuit is duplicated, even when the main apparatus circuit system is switched at a desired timing, the control load and the circuit scale are reduced. Data errors can be minimized without increasing the size.

1 is a system configuration diagram of a synchronization establishment system 10 according to a first embodiment. It is a block block diagram of the exchange 100 which concerns on 2nd Embodiment. 6 is a timing chart of various signals generated in the exchange 100 according to the second embodiment.

<First Embodiment>
A first embodiment according to the present invention will be described. FIG. 1 shows a system configuration diagram of a synchronization establishment system according to the present embodiment. 1, the synchronization establishment system 100 includes a first control circuit 20, a second control circuit 30, and a plurality of interface (I / F) circuits 40a, 40b,... Connected to one of the control circuits. The In FIG. 1, the first control circuit 20 is connected to a plurality of interface circuits 40 and set to the operational system. On the other hand, the second control circuit 30 is set as a standby system.

  The first control circuit 20 and the second control circuit 30 include clock generation units 21 and 31, frame head generation units 22 and 32, and adjustment signal generation units 23 and 33, respectively. The clock generation means 21 and 31 generate and output a reference clock. The frame head generation means 22 and 32 generate a frame head indicating the head of the frame. The adjustment signal generators 23 and 33 generate an adjustment signal for each time slot using the reference clock, and insert and output the adjustment signal at a predetermined position of the frame head.

  In this embodiment, the clock generation means 21 and 31 generate and output a 1-bit reference clock, and the frame head generation means 22 and 32 generate a frame head every 125 μs. On the other hand, when the transmission / reception data is composed of a plurality of channels of 8 bits, the adjustment signal generation means 23 and 33 generate an adjustment signal for each 8 bits and adjust the adjustment signal at a timing at which the adjustment signal is arranged 1 bit before the frame head. The signal is inserted into the frame head and output.

  Each of the plurality of interface circuits 40a, 40b,... Is connected to one of the control circuits and a client such as a public network, digital telephone, analog telephone, or IP telephone. Each of the interface circuits 40 is counted up every time a reference clock is input, and is cleared by inputting an adjustment signal. The interface circuit 40 is counted up every time an adjustment signal is input, and a frame head is input. By using the channel counter that is cleared by this, the connected control circuit is synchronized.

  In this embodiment, the interface circuit 40 recognizes that the adjustment signal has been input and clears the bit counter after 1 bit when a single pulse is input to the signal line to which the frame head on which the adjustment signal is superimposed is input. . On the other hand, when a continuous pulse is input on this signal line, the interface circuit 40 recognizes that the adjustment signal and the frame head are input, and after 1 bit when the leading pulse is input, the interface circuit 40 sets the bit counter and the ch counter. Clear at the same time.

  In the synchronization establishment system 100 configured as described above, the connection between the control circuits 20 and 30 and the plurality of interface circuits 40 is switched by the switching unit 50. In the present embodiment, the first control circuit 20 and the second control circuit 30 generate a reference clock with the same timing, but a shift occurs in the reference clock due to individual differences or the like. Therefore, when the connection between the control circuits 20 and 30 and the plurality of interface circuits 40 is switched when switching between the active system and the standby system, the reference circuit shifts (hereinafter referred to as glitch noise) in the interface circuit 40. Arise.

  At this time, when synchronizing with the connection destination control circuit using only the reference clock and the frame head, if a glitch noise occurs when switching the system from the active system to the standby system, the interface circuit 40 inputs the next frame head. Until this time, the reference clock deviation cannot be corrected over a maximum of 125 μs. On the other hand, when synchronization with the connected control circuit is performed by the reference clock, the adjustment signal, and the frame head, even when glitch noise occurs, the bit counter is cleared with a maximum of 8 bits and the deviation of the reference clock is eliminated. The

  Therefore, in the synchronization establishment system 100 according to the present embodiment, even when the reference clock is shifted due to system switching, the shift of the reference clock is eliminated with a maximum of 8 bits without increasing the control load or the circuit scale. Data errors can be minimized.

  In the present embodiment, the example in which the control circuits 20 and 30 superimpose the adjustment signal on the frame head for each time slot (every 8 bits) has been described, but the present invention is not limited to this. The adjustment signal may be superimposed on the frame head, for example, every 16 bits or every 32 bits according to the frequency or influence of the reference clock deviation.

<Second Embodiment>
A second embodiment will be described. In the present embodiment, an exchange used in a telephone system or the like will be described. A general exchange has a duplex structure of an active system and a standby system, and switches from the active system to the standby system when an abnormality occurs in the active system or when planned switching is performed.

  FIG. 2 shows a block configuration diagram of the exchange 100 according to the present embodiment. In FIG. 2, the exchange 100 includes time division switch circuits 210 and 220, multiple control circuits 310 and 320, a plurality of line circuits 400a, 400b,... And a plurality of trunk circuits 500a, 500b,.

  At the time of normal operation, the time division switch circuit 210 and the multiplex control circuit 310 are set to the operating system and are connected to the plurality of line circuits 400 and the plurality of trunk circuits 500. On the other hand, the time division switch circuit 220 and the multiplex control circuit 320 are set to the standby system. Here, there are two types of duplexing, a hot standby system and a cold standby system. In the present embodiment, the hot standby method is applied, the standby system is waiting in the operating state, and continuously operates by maintaining the operating state as it is when switching from the active system. Therefore, the standby time division switch circuit 220 and the multiplex control circuit 320 also perform the same processing as the operation time division switch circuit 210 and the multiplex control circuit 310. However, since the time division switch circuit 220 and the multiplex control circuit 320 are not connected to the line circuit 400 and the trunk circuit 500, various signals are not transmitted / received. Hereinafter, when it is not necessary to distinguish between them, they are simply referred to as a time division switch circuit 200, a multiplex control circuit 300, a line circuit 400, and a trunk circuit 500.

  When PCM data is input from the multiplex control circuit 300, the time division switch circuit 200 connects the PCM data transmission source line and the transmission destination line, and inputs the input PCM data via the multiplex control circuit 300. Send to destination. The time-division switch circuit 200 further generates and outputs a clock and a frame head, which are timing references for transmitting / receiving PCM data. The clock is output every 1 bit. On the other hand, the frame head is a signal representing the head of the frame, and is output every 125 μs.

  The multiplexing control circuit 300 multiplexes the PCM data input from the connected line circuit 400 and trunk circuit 500 and transmits the multiplexed data to the time division switching circuit 200. Further, when the PCM data is received from the time division switch circuit 200, the multiplexing control circuit 300 performs demultiplexing and transmits the received PCM data to the transmission destination line circuit 400 and trunk circuit 500. The multiplex control circuit 300 according to the present embodiment further generates a TS (Time Slot) bit corresponding to the speed of the PCM data using the clock input from the time division switch circuit 200, and is positioned 1 bit before the frame head. Superimpose as follows. The TS bit will be described later.

  The line circuit 400 is connected to a terminal or the like and the active multiple control circuit 310. When the line circuit 400 receives various data such as audio data from a connected terminal or the like, the line circuit 400 converts the received data into a digital signal and transmits the digital signal to the multiplexing control circuit 310 as PCM data. On the other hand, when receiving the PCM data from the multiplex control circuit 310, the line circuit 400 converts the received data into an analog signal and outputs the analog signal to a connected terminal or the like.

  The trunk circuit 500 is connected to a public line or the like and the active multiple control circuit 310. When the trunk circuit 500 receives various data such as voice data from a connected public line or the like, the trunk circuit 500 converts the received data into a digital signal and transmits it to the multiplexing control circuit 310 as PCM data. On the other hand, when the trunk circuit 500 receives PCM data from the multiplex control circuit 310, the trunk circuit 500 converts the received data into an analog signal and outputs it to a connected public line or the like.

  The line circuit 400 and the trunk circuit 500 according to the present embodiment determine the transmission / reception timing of the PCM data based on the clock generated in the time division switch circuit 210 and the frame head on which the TS bits are superimposed. A method for determining transmission / reception timing of PCM data will be described later.

  In the exchange 100 configured as described above, when voice data is transmitted from a terminal connected to the line circuit 400a toward a public line connected to the trunk circuit 500a, the line circuit 400a receives from the terminal. Audio data is converted into a digital signal and transmitted to the multiplexing control circuit 310 as PCM data. The multiplexing control circuit 310 multiplexes the PCM data output from the plurality of line circuits 400 and transmits the multiplexed data to the time division switching circuit 210.

  When the time division switch circuit 210 receives PCM data from the line circuit 400 a via the multiplex control circuit 310, the time division switch circuit 210 connects the transmission source line and the transmission destination line and passes the received PCM data via the multiplex control circuit 310. To the destination trunk circuit 500a.

  When receiving the PCM data from the time division switch circuit 210, the multiplexing control circuit 310 performs demultiplexing and transmits the received PCM data to the transmission destination trunk circuit 500a. The trunk circuit 500a decodes the received PCM data and transmits the voice data to the connected public line. Note that voice data is transmitted from the public line to the terminal in the same manner.

  Next, the line circuit 400 and the trunk circuit 500 determine PCM data transmission / reception timing based on the clock and frame head generated in the time division switch circuit 210 and the TS bit generated in the multiplex control circuit 300. A method will be described.

  As described above, the multiplex control circuit 300 according to the present embodiment generates TS bits corresponding to the speed of the PCM data, and superimposes them so as to be positioned one bit before the frame head. For example, when the PCM clock is 8.192 MHz and 64 kbps PCM data is handled for 128 channels (= 125 μs / ((1 / 8.192 MHz) · 8 bits)) by a 125 μs frame, the multiplex control circuit 300 has one frame. The TS bit is transmitted 128 times at a transmission interval (8-bit width) of 976 ns.

  In addition, as shown in FIG. 2, the exchange 100 normally has one clock (CLK) for generating transmission / reception timing of PCM data, one frame head (FH) indicating the head of one frame of PCM data, A total of four signal lines, two for PCM data transmission and reception (PCM), are arranged. The multiplex control circuit 300 superimposes the generated TS bit at a timing arranged one bit before the frame head on the signal line for the frame head, and outputs it.

  FIG. 3 shows the relationship between the clock, TS bit, and frame head and the bit position and ch position of PCM data. In FIG. 3, a clock (CLK) is output every 1 bit, and a frame head (FH) is generated and output every 125 μs.

  The line circuit 400 and the trunk circuit 500 generate a bit counter based on the clock generated in the time division switch circuit 210 and a ch counter based on the frame head in which the TS bit received from the multiplex control circuit 310 is inserted. The bit counter is updated when a clock is input, and is cleared after 1 bit when a TS bit is input. On the other hand, the ch counter is updated 1 bit after the TS bit is input and cleared when the frame head is input.

  The multiplex control circuit 310 inserts TS bits 8 bits at a time according to the configuration of PCM data, so that the bit counter is counted from 0 to 7, as shown in FIG. On the other hand, the ch counter is counted up to the number of channels of the system, and when the 128ch PCM data is handled by the 125 μs frame, the ch counter is counted from 0 to 127. The line circuit 400 and the trunk circuit 500 recognize the position of PCM data to be transmitted / received based on the values of the bit counter and the ch counter.

  Here, by superimposing the TS bit on the frame head at a timing arranged 1 bit before the frame head, when a continuous pulse is input in the line circuit 400 and the trunk circuit 500, the TS bit and the frame head are changed. By defining the input as being input, the line circuit 400 and the trunk circuit 500 can recognize the TS bit and the input of the frame head. Then, by clearing the bit counter and updating the ch counter after 1 bit of the TS bit input in the line circuit 400 and the trunk circuit 500, the bit counter and the ch counter can be cleared simultaneously when the frame head is input. it can. When the TS bit is superimposed on the frame head at the timing of being placed 1 bit before the frame head, both can be handled by one signal line, resulting in a decrease in bit rate, addition of a signal line, etc. Can be avoided.

  Next, the operation when switching between the active system and the standby system will be described. Switching between the active system and the standby system is performed by processing from a CPU not shown in FIG. When the active system and the standby system are switched by an instruction from the CPU (not shown), the connection destinations of the plurality of line circuits 400 and the plurality of trunk circuits 500 are the time division switch circuit 210 and the multiplex control circuit 310 that are the active system, The time-division switch circuit 220 and the multiplex control circuit 320 are changed to the standby system.

  Here, during normal operation, the standby time division switch 220 and the multiplexing control circuit 320 also generate a clock and a frame head on which TS bits are superimposed, as in the active system. However, the time division switch circuit 210 and the time division switch circuit 220 generate the same clock and frame head, but the device delay in the time division switches 210 and 220, the time division switch circuits 210 and 220, There is a difference between the two clocks due to delays in the signal lines connecting the multiplex control circuits 310 and 320, respectively. In addition, there are device delays within the multiplex control circuits 310,320. Accordingly, when switching from the multiplex control circuit 310 to the multiplex control circuit 320 at the time of system switching, glitch noise is generated in the line circuit 400 and the trunk circuit 500.

  When the glitch noise is applied to the clock, the bit counter in the line circuit 400 and the trunk circuit 500 becomes abnormal. When a short pulse of glitch noise occurs once, the bit counter advances by one from the normal state, and the recognized bit position is shifted by one. In the case of counting with only the clock and the frame head, the frame head arrives only every 125 μs, so that the 1-bit shift is continued for a maximum of 125 μs until the next frame head arrives.

  On the other hand, in the exchange 100 according to the present embodiment, since TS bits are inserted every 8 bits, even when a glitch noise occurs and the bit counter advances by 1 and a bit shift occurs, TS When the bit arrives, it is cleared within 8 bits, and the ch counter counts up normally. That is, when the glitch noise occurs, the ch counter when the switching occurs becomes abnormal, but the data abnormality is resolved within a maximum of 8 bits and becomes normal from the next channel.

  In the above-described embodiment, the example in which the glitch noise generated when switching between the active system and the standby system has been described has been described. However, the exchange 100 described above can eliminate the glitch noise generated by the external noise. Is also effective. Even when an external glitch noise occurs, misrecognition of the bit position or ch position occurs due to the internal counter being counted more than usual.

  In the above embodiment, since the TS bit is transmitted every time slot (8 bits) and the ch counter is cleared, the misrecognition of bits due to external noise and the misrecognition of ch are eliminated within 8 bits. Will be recognized normally. However, if the external noise is not a few bits wide but occurs for a long period exceeding several channels, the abnormality cannot be resolved within 8 bits. In this case, the normal bit position and ch position can be recognized within 8 bits after the external noise is eliminated.

  The present invention can be suitably applied to, for example, an exchange whose reliability is improved by unifying a line circuit and duplicating a time division switch circuit and other control circuits.

  The present invention is not limited to the above-described embodiment, and design changes and the like within a range not departing from the gist of the present invention are included in the present invention.

DESCRIPTION OF SYMBOLS 10 Synchronization establishment system 20 1st control circuit 21 Clock generation means 22 Frame head generation means 23 Adjustment signal generation means 30 2nd control circuit 31 Clock generation means 32 Frame head generation means 33 Adjustment signal generation means 40a, 40b, ..., Interface circuit 100 switch 200, 210, 220 time division switch circuit 300, 310, 320 multiple control circuit 400 line circuit 500 trunk circuit

Claims (7)

A first control circuit and a second control circuit;
A plurality of interface circuits connected to one of the control circuits;
A synchronization establishment system comprising:
The first control circuit and the second control circuit are respectively
Clock generation means for generating and outputting a reference clock; and
Frame head generating means for generating a frame head indicating the head of the frame;
An adjustment signal generating means for generating an adjustment signal at predetermined intervals using the reference clock, and inserting and outputting the adjustment signal at a predetermined position of the frame head;
With
Each of the plurality of interface circuits is
A bit counter that is counted up each time the reference clock is input and is cleared when the adjustment signal is input;
A ch counter that is counted up each time the adjustment signal is input and is cleared when the frame head is input;
Ri taken synchronization with the connected control circuit by using,
When the plurality of interface circuits transmit / receive PCM data composed of a plurality of channels consisting of 8 bits,
The adjustment signal generating means includes
The adjustment signal is generated every 8 bits,
Insert at a timing that is arranged 1 bit before the frame head,
A synchronization establishment system characterized by that. The interface circuit is
1 bit after the adjustment signal is input, the bit counter is cleared and the ch counter is counted up.
The synchronization establishment system according to claim 1, wherein: The clock generation means outputs the reference clock every 1 bit,
The frame head generating means outputs a frame head every 125 μs,
The interface circuit is
When the reference clock and the frame head are input,
Count up the bit counter and clear the ch counter.
The synchronization establishment system according to claim 1 or 2, characterized in that The control circuit that is not the plurality of interface circuits,
Generate the reference clock, frame head and adjustment signal, but do not output.
Synchronization establishment system according to any one of claims 1 to 3, characterized in that. The first control circuit and the second control circuit;
The plurality of interface circuits;
Further comprising switching means for switching the connection of
Synchronization establishment system according to any one of claims 1 to 4, characterized in that. The control circuit includes:
A time division switch circuit including the clock generation means and the frame head generation means;
A multiplex control circuit including the adjustment signal generating means;
With
The plurality of interface circuits include
Includes a line circuit connected to the terminal device and a trunk circuit connected to the public line.
Synchronization establishment system according to any one of claims 1 to 5, characterized in that. A first control circuit and a second control circuit;
A plurality of interface circuits connected to one of the control circuits;
Synchronization establishment method in which
In the control circuit,
Generate and output a reference clock,
Generate a frame head that indicates the beginning of the frame,
An adjustment signal is generated at predetermined intervals using the reference clock, inserted into a predetermined position of the frame head, and output.
In the interface circuit,
A bit counter that is counted up each time the reference clock is input and is cleared when the adjustment signal is input;
A ch counter that is counted up each time the adjustment signal is input and is cleared when the frame head is input;
To synchronize with the connected control circuit based on
When the plurality of interface circuits transmit / receive PCM data composed of a plurality of channels consisting of 8 bits,
The adjustment signal is generated every 8 bits,
Insert at a timing that is arranged 1 bit before the frame head,
A method for establishing synchronization .

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