JP2001197051A - Synchronous circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous circuit constitution which enables normal forward protection up to an error rate of 10-1 and surely seizes a synchronizing signal in a short hunting time even in the case of a step-out. SOLUTION: This circuit has a frame signal matching circuit which makes an input signal match with a synchronous signal pattern and assures a correct matching including a case wherein the input signal is within a prescribed inter- code distance from the synchronous signal pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous circuit,
In particular, the present invention relates to a synchronous circuit applicable to a data signal having a high error rate.

[0002]

2. Description of the Related Art Super FEC (Forward E
rror correction) is to add an error correction signal to data to enable error correction even for S / N deterioration of light of about 7 dB, thereby increasing a transmission distance or a repeater interval.

[0003] Such a super FEC (Forward Err)
or Correction), it is attempted to apply the present invention to signal transmission up to an error rate of about 2 × 10 ⁻² .

[0004] Therefore, such FEC is 10 ^-1.
When the forward protection is normally applied up to the error rate and the synchronization is lost, it is required that the hunting be performed in a short hunting time and the synchronization signal be reliably captured at the location of the synchronization signal.

[0005] The synchronization signal has a fixed frame pattern and is inserted into the data signal at a predetermined cycle.

FIG. 1 shows a configuration example of a data signal, and FIG. 2 shows a general configuration example of a corresponding synchronous circuit.
In FIG. 1, a constant synchronization pattern is inserted at intervals of M = 10 ⁵ bits as a frame synchronization signal.

In FIG. 2, a digital signal sequence DATA in which a frame synchronizing signal of the synchronizing pattern is inserted is input to a frame signal collating circuit 1 in synchronization with a clock signal CLK.

The input digital signal sequence is compared with a predetermined frame synchronization pattern, and a logical H signal is output from the frame signal matching circuit 1 when they match.

On the other hand, the frame signal pattern position generating circuit 2 counts the clock signal and outputs a timing signal indicating a timing corresponding to the position of the synchronization signal in the synchronization pattern.

The coincidence circuit 3 judges whether the output of the frame signal collation circuit 1 and the timing signal from the frame signal pattern position generation circuit 2 match or not, and when they match, inputs a logic H signal to the hunting control circuit 4. .

When the output of the matching circuit 3 is logic L, that is, when the mismatch is determined and when the forward protection is off, the hunting control circuit 4 outputs the frame signal pattern position generating circuit 2.
Block the input of the clock CLK. Thus, the counting of the counter in the frame signal pattern position generating circuit 2 is stopped.

As a result, the timing corresponding to the generation position of the synchronization signal output from the frame signal pattern position generation circuit 2 is shifted.

Further, the front / rear protection circuit 5 is for avoiding pseudo loss of synchronization or recovery of synchronization. That is, the matching circuit 3 detects whether the matching and mismatching have continued for a predetermined number of times, detects a deterministic loss of synchronization or a synchronization state, and outputs a detection signal.

Until now, such a synchronous circuit has been used exclusively for 1
This corresponds to a signal having an error rate of 0 ^-4 or less.

[0015]

For this reason, in such a conventional synchronous circuit configuration, a super FEC (for FEC) for transmitting a signal up to the above-mentioned error rate of about 2 × 10 ^{−2 is used.}
ward Error Correction).

Accordingly, it is an object of the present invention to provide a synchronous circuit configuration which can normally perform forward protection up to an error rate of 10 ^-1 and can reliably capture a synchronous signal in a short hunting time even when synchronization is lost. Is to provide.

[0017]

A synchronization circuit according to the present invention for solving the above-mentioned problems has a frame signal collation circuit for collating an input signal with a synchronization signal pattern, wherein the input signal is a signal having a predetermined relationship with the synchronization signal pattern. It is characterized in that the collation is correct, including the case where it is within the distance between codes.

Preferably, the frame signal matching circuit includes a shift register for shifting the input signal by a predetermined number of bits, and a ROM addressed by the predetermined number of bits of the input signal shifted by the shift register. In the ROM, logic "1" is written at an address position addressed by a synchronization signal and an input signal within a predetermined distance from the frame synchronization signal, and logic "0" is written at other address positions. It is characterized by the following.

Preferably, the input signal has a multi-frame configuration, and the synchronization signal includes a frame synchronization signal having the same pattern in each frame and a multi-frame synchronization signal indicating the order of the multi-frame. And

Preferably, the frame synchronization signal has a common pattern for each frame.

Still preferably, the input signal is synchronized with a frame synchronization signal, and then with a multi-frame synchronization signal.

Further, preferably, an error correction code is used for the multi-frame signal, and an inter-code distance is set to (2d
When +1) or more, a code having an inter-code distance within d from the multi-frame synchronization signal is set as a synchronization signal.

Preferably, an initial value of a PN pattern is different according to the multi-frame signal.

Further features of the present invention will become apparent from the following description of embodiments of the present invention.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components will be described with the same reference numerals or reference symbols.

The basic configuration of the synchronization circuit according to the present invention is the same as the configuration described with reference to FIG.

In the synchronous circuit according to the present invention, the frame signal matching circuit 1 is configured as shown in FIG. 3 as an embodiment.

The shift register 10 comprises a 16-bit shift register 10 and a ROM 11 for reading data using the output of the shift register 10 as an address. An address of 2 ¹⁶ = 1.024 is associated with a frame synchronization signal to be collated. Therefore, the capacity of the ROM 11 is (address 1,024) × (data 1 bit).

When a frame synchronization signal and a signal from the frame synchronization signal to the inter-code distance 5 are correct as the synchronization signal, the output data D _{0 is} stored in the ROM address (A _{0 to} A ₁₆ ) corresponding to the inter-code distance 5 or less. , And 0 is written in other cases.

For example, [0000000000000000
When 00] is referred to as synchronizing signal pattern, [0000000000000001] and the pattern ₁₆ C ₁ ways of changing the order [0000000000000011] and the pattern ₁₆ C ₂ ways of changing the order [0000000000000111] and the pattern ₁₆ C ₃ ways of changing the order [0000000000001111 ] and the pattern ₁₆ C ₄ ways of changing the order [0000000000011111] and the pattern ₁₆ C ₅ as changed order is the correct answer as a code distance 5 within the synchronizing signal.

Here, from the above, the inter-symbol distance means that a pattern different from the synchronization pattern by N bits is the inter-symbol distance N.
Say the sign.

Then, the above ₁₆ C ₀ , ₁₆ C ₁ , ₁₆ C ₂ , ₁₆
1 is written in the address position of the ROM 11 corresponding to C ₃ , ₁₆ C ₄ , and ₁₆ C ₅ , and 0 is written in other addresses.

In this manner, whether the 16-bit data DATA entered in the shift register 10 is correct or incorrect as a synchronization signal can be obtained from the data output D0 of the ROM 11.

Here, the frame signal matching circuit 1 having the above configuration can allow a signal having an error rate of 10 ^-1 as a synchronization signal. However, it is important whether or not the requirements for the other circuit elements in FIG. 2 constituting the synchronous circuit can be satisfied.

The number of front protection stages, hunting time, and number of rear protection stages, which are constituent elements of a synchronous circuit, will be discussed below.

Consider the following requirements in the frame configuration shown in FIG.

[Frame Configuration] Bit rate: 10 Gb / s Frame length M: 10 μs (10 ⁵ bits: speed 10 G) Synchronous pattern: 16 bits or 32 bits (centralized type) Error resistant rate: 10 ^-1

[The number of forward protection stages] The role of forward protection is to prevent synchronization from being lost even at 10 ^-1 while capturing a synchronization signal. If the error rate is 10 ^-1 and the synchronization pattern is 16 bits, it must be considered that an average of 1.6 code errors occur for one synchronization pattern.

Assuming that such an error occurs, it is necessary to recognize that a code having a certain inter-code distance (5 permissible errors in the above embodiment) with respect to the synchronization pattern is also a synchronization pattern. .

Here, as described above, the distance between codes is
A pattern different from the synchronization pattern by N bits is referred to as a code having a code distance N.

The inter-symbol distance and the number of synchronization protection stages for 16-bit and 32-bit synchronization patterns are obtained as follows.

Among the a bits, the probability Pi that the i bit is wrong is Pi = aCi (0.1) ⁱ (1-0.1) ^ai (Equation 1).

Of the a bits, the error occurrence probability of b bits or less is

(Equation 1)

Of the a bits, the error occurrence probability of (b + 1) bits or more is

(Equation 2)

FIG. 4 shows that a = 16 bits (FIG. 4A), 32 bits
The calculation example of the error probability (Equation 1), the error occurrence probability of b bits or less (Equation 2), and the error occurrence probability of b bits or more (Equation 3) when the number of bits (FIG. 4B) is set is shown.

At an error rate of 10 ^-1 as the strength of the forward protection, the probability that the forward protection is lost in one year is set to one or less.

According to the requirements presupposed above, the number of times the synchronization pattern is checked in one year is 60 seconds × 60 minutes × 24 hours × 365 days / (10 × 1
In the case of 0 ⁻⁶ ) = 3.154 × 10 ¹² 10 Gb / s and 10 ⁵ bits per frame, the frame synchronization is 10 μs.

The condition that the forward protection does not come off is that the number of protection stages is n.
Then, when the number of errors allowed for n consecutive times is exceeded,
The probability is

(Equation 3) In the case of a 16-bit synchronization pattern, 0 bit error tolerance n ≧ 130 4 bit error tolerance n ≧ 8 5 bit error tolerance n ≧ 6 In the case of a 32 bit synchronization pattern, 7 bit error tolerance n ≧ 7.

Therefore, the number n of front protection stages may be set in accordance with the above. Then, in the configuration of FIG.
The number of stages of the shift register constituting the rear protection circuit 5 is a value n set as described above.

As described above, as the number of forward protection stages increases, the required number of forward protection stages decreases as the allowable number of errors increases. The number of bits of the synchronization signal can be designed to be 16 bits or 32 bits.

[Hunting time] Next, the hunting time will be considered. The hunting time is determined by the match circuit 3
When it is determined that there is no match, the time for performing a shift to search for a frame signal.

If a 16-bit synchronization pattern is used and the probability that an input signal is determined to be a synchronization signal at the time of hunting is r, the probability r when a 5-bit error is allowed is: r = (16C0 + 16C1 + 16C2 + 16C3 + 16C4 + 16C5) × (0.5) ¹⁶ = (1 + 16 + 120 + 560 + 1,820 + 4,368) x (0.5) ¹⁶ = 0.10506.

For example, 16C0 is the number of patterns without error, 16C1 is the number of patterns with one error, and 16C2 is the number of patterns with two errors.

Further, the probability S of not being determined to be a synchronization signal is S
= 1-r.

Here, the number of bits L required for 1-bit shift when the frame length is M bits is obtained.

FIG. 5 is a diagram for explaining expected shift time values for hunting. In FIG. 5, 1
If the synchronization signal is not determined in the second synchronization pattern matching (〇 mark), the expected time required for 1-bit shift is S
× 1.

Further, the frame is cycled once to shift one bit.
Time required to shift (shift by M + 1 bits)
Is S · r (M + 1), and the frame is cycled twice and 1 bit
Required for data shift (shift by 2M + 1 bits)
Expected time is Sr^Two(M + 1). L = S + Sr (M + 1) + Sr^Two(2M + 1) +... = S (1 + r + r)^Two+ R^Three+...) + SMr (1 + 2r)
+ 3r^Two+ 4r^Three+...) = S / (1-r) + S · M · r / (1-r)^Two = 1 + M · r / S ≒ M · r The worst condition for reaching the synchronization pattern is (M−1)
A shift of the set is required. Worst case required for synchronization
The number of bits is (M−1) · L ≒ M · L r = 0.10506, M = 10^FiveML ≒ M^Two・ R = 1.05 × 10⁹ T = 10^-TenOver time, MLT = 0.105 seconds. 7-bit error using 32-bit synchronization pattern
When allowed, r = (32C0 + 32C1 + 32C2 + 32C3 + 32C4 + 32C
5 + 32C6 + 32C7) × (0.5)³² = (1 + 32 + 496 + 3,5960 + 201,376 + 906,192 + 3,365,85
6) x (0.5)³²  = 1.051 x 10^-3 MLT = 1.05 × 10^-3Second

As described above, the hunting time increases as the allowable number of errors increases. When the number of bits of the synchronization signal is changed from 16 to 32, the hunting time is shortened. The allowable number of errors and the number of frame bits are determined in consideration of such a viewpoint.

[Backward protection] What is required for the backward protection is that the backward protection is not accidentally applied during hunting and that the backward protection is reliably applied when the synchronization pattern is reached.

The probability t that the rear protection is applied at one position other than the synchronization signal is t = rm when the number of the rear protection stages is ^m.
It is.

[0061] worst (M-1) condition not to apply backward protection during hunting because it is necessary to bit shift t (M-1) = r ^m (M-1) <1.

When the number of bits of the synchronization signal is 16 and the allowable number of errors is 5 bits, r = 0.10506. Therefore, m ≧ 6. When the number of bits of the synchronization signal is 32 and the number of allowable errors is 7 bits, r = 1.051 × Since it is 10 ^-3 , m ≧ 2.

After reaching the synchronization signal, the probability that the backward protection will not be applied is based on the assumption that the number of bits of the synchronization signal is 16 and the error tolerance is 5 bits.

(Equation 4) This is to slip once every 50 times and hunt for two frames. When the number of bits of the synchronization signal is 32 and the error tolerance is 7 bits,

(Equation 5)

Therefore, as for the number of backward protection stages, the larger the allowable number of errors, the smaller the number of backward protection stages.
In addition, the slip rate at the position of the synchronization signal is also reduced. From this viewpoint, the number of rear protection stages is set.

As a specific configuration of the rear protection circuit,
The forward / backward protection circuit 5 in FIG. 2 may be constituted by the shift registers, and a predetermined number of logic stages opposite to the case of the forward protection may be detected from the shift registers of the number of forward protection stages.

As described above, the frame signal collation circuit 1 which allows a signal having a predetermined inter-code distance as a synchronizing signal is configured. On the other hand, the number of forward protection stages, the hunting time, and the number of backward protection stages are the same as in the conventional configuration. It was proved that it could be configured.

In the frame signal collation circuit 1, the number of synchronization signal bits (the number of protection stages) can be the same or different for forward protection and backward protection.

Further, regarding the front protection and the rear protection, it is possible to make the distance between codes that are correct as a synchronization signal different.

Here, consider applying the synchronization circuit of the present invention to a multi-frame signal. In this case, the frame configuration of the multi-frame signal is as shown in FIG.

One frame of the signal sequence is composed of M bits,
The frame synchronization signal FSS is composed of 16 bits, the multiframe synchronization signal MFS is composed of 15 bits, and the multiframe is eight frames.

Here, the frame synchronization signal FSS is common to each frame, and the multi-frame synchronization signal MFS
Indicates the order of the multi-frame. The multi-frame synchronization signal MF inserted into the multi-frame signal having such a configuration
FIG. 7 is a block diagram showing a configuration example of a multi-frame generation circuit on the transmission side that generates S.

The system comprises a 3-bit counter 20 for inputting a frame signal, and a ROM 21 for outputting 15-bit data using the 3-bit output of the counter 20 as an address. The ROM 8 stores (address 8) × (data 1
5 bits).

BCH (15,
5) The code is calculated in advance. Then, 0 to 7 are written in the ROM 21 in correspondence with the addresses. Therefore, the BCH (15, 5) code at the address position specified by the 3-bit output of the multiframe counter 7 is RO
It is read from M21.

This is inserted at the position of the multi-frame synchronization signal MFS of the multi-frame signal shown in FIG.

FIG. 8 shows a configuration example of a synchronization circuit corresponding to such a multi-frame signal.

A circuit for synchronizing a multi-frame signal is connected in parallel with the synchronization circuit for the synchronization pattern shown in FIG.

That is, in addition to the circuit shown in FIG. 2, a multi-frame synchronization signal (MFS) matching circuit 6, a second matching circuit 7, a second hunting circuit 8, and a second forward circuit. It has a rear protection circuit 9.

The frame signal matching circuit 1, matching circuit 3, hunting control circuit 4, and front / rear protection circuit 5 are the same as those described with reference to FIG.

The frame signal pattern position generating circuit 2
A timing signal at a frame signal position common to each frame is output and input to the first matching circuit 3, and a timing signal at a Nalchi frame synchronization signal position indicating the order of multiframes is generated. To enter.

FIG. 9 is a block diagram showing an example of the configuration of the multi-frame signal matching circuit 6. The 15-bit shift register 12 to which the multi-frame signal DT and the clock CLK are input, and the timing signal of the multi-frame signal position from the frame signal pattern position generation circuit 2 are input.
3-bit counter 13 for counting this and ROM
14.

The eight address values (A ₁₅ , A ₁₆ , A ₁₇ ) of the ROM 14 obtained from the 3-bit counter (multi-frame position timing counter) 13 correspond to the order of multi-frames (for eight frames).

The addresses A _{0 to} A ₁₄ of the ROM ₁₄ , which are the 15-bit outputs of the 15-bit shift register 12, are made to correspond to the multi-frame synchronization pattern.

The ROM ₁₄ stores in the ROM ₁₄ a signal having an inter-symbol distance of 3 or less from the multi-frame synchronization signal corresponding to the multi-frame order (A ₁₅ , A ₁₆ , A ₁₇ ) so as to be a multi-frame synchronization signal. 1 is stored for the pattern within, and 0 is stored for other patterns.

Therefore, 1 is obtained as the data output D0 of the ROM 14 when the answer is correct and 0 when the answer is incorrect as the multiframe synchronization signal.

Here, as the order of the synchronization processing, after synchronizing with the frame synchronization pattern common to each frame by the configuration of the upper half of FIG. 8, the multi-frame synchronization signal corresponding to the order of the multi-frame is obtained. Synchronize. Thereby, the synchronization pull-in time can be shortened.

Further, an error correction code is used for a multi-frame synchronization signal corresponding to the multi-frame order,
The distance between codes is (2d + 1) or more. At the time of checking the multi-frame synchronization signal, it is possible to treat codes within d as correct signals as synchronization signals and set forward protection and backward protection.

Here, in FIG. 8, the number of stages of the forward / backward protection circuit 9 and the number of stages of the hunting control circuit 8 constituted by a shift register for performing forward protection, hunting control and backward protection for a multi-frame synchronization signal will be examined. I do.

[Frame Configuration] Here, the frame configuration shown in FIG. 10 is used as a specific configuration example of the multi-frame shown in FIG.

The overhead byte inserted in the frame is used for communication of the state of the apparatus and is synchronized with the FEC frame, and often has a fixed pattern. In the present invention, by changing the PN pattern by scrambling this portion, it is possible to avoid erroneous synchronization with the FEC overhead.

In the frame structure shown in FIG. 10, the multi-frame synchronization signal MFS has 0,
The signals 1, 2, 3,... Are transmitted, and the initial state of scrambling according to the values is taken, and the initial values are made different.

The scramble range is different from the overhead byte by changing the initial value of the overhead byte, the payload, and the scramble which is the additional bit syndrome for FEC, thereby preventing malfunction.

Here, the portion shown as the other overhead in FIG. 10 described above is a portion used for communication between FECs. In a conventional SDH signal, the method of using this part is predetermined. This is sufficient when used in a standardized way of use, but new demands arise every year as to how to operate the device, and new ideas arise.

To cope with this, the communication signal between the FECs can be flexibly coped with a change in the usage by defining a higher-level protocol without determining the usage in the frame configuration.

[0094] In the above, the frame structure further includes an overhead for communication between FECs, and the overhead can be used as at least one or more clear channels.

[Forward Protection] Here, since the multi-frame synchronization signal is extracted before descrambling and error correction processing, protection is necessary. The period of the multi-frame synchronization signal must be greater than the number of forward protection stages of the frame synchronization signal. Under this condition, the forward protection can be released even if the backward protection is applied by the overhead byte.

When a 16-bit synchronization error pattern and an error-permissible inter-symbol distance of 5 are used, six stages of forward protection are performed. When a 32-bit synchronization error pattern and an error-permissible inter-symbol distance of seven are used, seven stages of forward protection are performed. Eight frames are sufficient.

Next, the expression format of the scramble period signal will be considered.

When the error rate is 10 ^-1 and 0 to 7 are simply binary codes, there is no problem in forward protection, and in backward protection, the inter-code distance differs for each pattern and processing is difficult.

For this reason, the 3-bit code of 0 to 7 is converted into a 15-bit BCH (15, 5) code. When this process is performed, the distance between the respective codes becomes the inter-code distance of 5.

For a 15-bit multi-frame synchronization signal, the error occurrence rate at which i-bit is erroneous is as follows: Pi = ₁₅ Ci (0.1) ⁱ (1-0.1) ^15-i

(Equation 6) The probability of occurrence of errors of (b + 1) bits or more is

(Equation 7)

FIG. 11 shows a calculation example of the error probability (Pi) for b = 0 to 3, the error occurrence probability of b bits or less, and the error occurrence probability of b bits or more.

Since the inter-symbol distance is 3, the answer is correct up to a 3-bit error. The number of protection stages n that causes synchronization to be lost once or less per year in a matching circuit configured with 3-bit error tolerance is:

(Equation 8)

[Backward Protection and Hunting Time] Considering the hunting time, multi-frame synchronization is performed after frame synchronization is established in order to shorten the hunting time. By doing so, the hunting is performed in units of one frame, and a shift of seven frames at the worst.

During the hunting, if the probability that a portion other than the synchronization signal is determined to be a synchronization signal is r, the synchronization signal does not match unless the error is at least 4 bits.

(Equation 9) In the above equation (M−1) · L of the FEC synchronous circuit, M =
As M = 8, (M−1) · L = (M−1) (1 + M · r / S) = 7 × (1 + 8 × 0.00555 / (1−0.00555) = 7.712 ≒ 8 It is reliably drawn in at about 8 frames.

Next, the number m of rear protection stages is determined. Back protection must not be applied during hunting. r ^m × (8-
1) <1, m ≧ 1 One step of rear protection is sufficient. Also the slip rate is low enough

(Equation 10)

As described above, the PN pattern is set for each frame.
A multi-frame is formed so as to take different initial values according to the multi-frame synchronization signal. Then, by synchronizing a common synchronization pattern frame in each frame and forming a multi-frame synchronization signal with an error correction code, it is possible to increase the synchronization pull-in speed reliably.

[0107]

The embodiments of the present invention are described above with reference to the drawings.
As described, 10 ^-1Error rate of
Forward protection and synchronization is lost
Hunts and synchronizes with a short hunting time
Meets the need to reliably capture the synchronization signal at the point of the signal
It is possible to provide a synchronous circuit that can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a frame signal configuration.

FIG. 2 is a block diagram illustrating a general configuration example of a synchronization circuit.

FIG. 3 is a block diagram illustrating a configuration example of a receiving-side frame signal matching circuit 1 of FIG. 1 applied to a synchronization circuit according to the present invention;

FIG. 4 is a diagram illustrating a calculation example of an error probability and an error occurrence probability under predetermined conditions.

FIG. 5 is a diagram illustrating an expected shift time for hunting.

FIG. 6 is a diagram illustrating an example of a multi-frame signal.

7 is a diagram illustrating an example of a multi-frame synchronization signal generation circuit on the transmission side corresponding to the multi-frame signal in FIG. 6;

FIG. 8 is a block diagram illustrating a configuration example of a synchronization circuit corresponding to a multi-frame signal.

9 is a block diagram showing a configuration example of a frame signal matching circuit 6 on the receiving side corresponding to the multi-frame signal shown in FIG. 6 according to the present invention in the synchronization circuit shown in FIG.

FIG. 10 is a diagram illustrating overhead bytes in a multi-frame signal.

FIG. 11 shows an error probability (Pi) for a 15-bit multiframe synchronization signal, an error occurrence probability of b bits or less, and
9 shows an example of calculating an error occurrence probability of b bits or more.

[Explanation of symbols]

 1 Frame signal matching circuit 2 Frame signal pattern position generating circuit 3, 7 Matching circuit 4, 8 Hunting circuit 5, 9 Forward / backward protection circuit 6 Multi-frame signal matching circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J065 AA02 AC02 AD03 AE02 AF02 AH18 5K014 BA05 CA02 EA07 5K028 AA14 MM17 NN01 NN02 NN05 NN13 SS27 SS28 5K047 AA11 GG34 HH01 HH02 HH12 HH22 HH57 MM29 MM14MM

Claims (8)

[Claims] 1. A frame signal matching circuit for matching an input signal with a synchronization signal pattern, wherein the matching is correct, including when the input signal is within a predetermined distance between the synchronization signal pattern and the code. A synchronous circuit. 2. The frame signal matching circuit according to claim 1, wherein the frame signal matching circuit includes a shift register for shifting the input signal by a predetermined number of bits, and a ROM addressed by the predetermined number of bits of the input signal shifted by the shift register. In the ROM, logic “1” is written at an address position addressed by a synchronization signal and an input signal within a predetermined code distance from the frame synchronization signal, and logic “0” is written at other address positions. Synchronous circuit characterized by being embedded. 3. The system according to claim 1, wherein the input signal has a multi-frame configuration, and the synchronization signal includes a frame synchronization signal having the same pattern in each frame;
A synchronization circuit comprising a multi-frame synchronization signal indicating a multi-frame order. 4. The synchronization circuit according to claim 3, wherein the frame synchronization signal has a common pattern for each frame. 5. The method according to claim 3, wherein the input signal is synchronized with a frame synchronization signal.
Next, a synchronization circuit for synchronizing with a multi-frame synchronization signal. 6. The multi-frame signal according to claim 3, wherein:
When the inter-code distance is equal to or more than (2d + 1), a code having an inter-code distance less than d from the multiframe synchronization signal is used as a synchronization signal. 7. The synchronizing circuit according to claim 3, wherein an initial value of a PN pattern is different according to the multi-frame signal. 8. The synchronization circuit according to claim 3, wherein said frame has a communication overhead between FECs, and said overhead is used as at least one or more clear channels.