JP2016072842A - Signal transmission device for time-division multiplexing, time-division multiplexing signal receiving device and time-division multiplexing signal transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission device for time-division multiplexing, a time-division multiplexing signal receiving device and a time-division multiplexing signal transmission system, in which a receiving device in common properly takes in a signal for time-division multiplexing, the signal being transmitted from a plurality of transmission devices at different timings, even if a clock speed is high considering from a propagation delay in a highway.SOLUTION: One time slot from a transmission device comprises a front side dummy bit stream, a start bit stream, a transmission data body, and a rear side dummy bit stream. The transmission device transmits each bit of a time slot in synchronous with a clock from a receiving device. The receiving device monitors the arrival of a start bit stream using a window pulse in synchronous with the clock, the arrival being predicted from a time slot of the transmission device, and extracts a transmission data body on the basis of the detection of the start bit stream.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a time division multiplexing signal transmission apparatus, a time division multiplexing signal reception apparatus, and a time division multiplexing signal transmission system, and can be applied to, for example, transmission of time division multiplexed signals in a private branch exchange (PBX). .

  Private branch exchanges have different configurations depending on the scale of the organization such as the company that uses the private branch exchange, so that the number of lines (external lines and extensions) to be implemented varies, so that the degree of freedom of the number of lines to be implemented can be increased. Yes. For example, a private branch exchange for the organization can be configured by providing an arbitrary number of housing-like units, and each unit also has an upper board that mainly performs processing common to lines (for example, signaling processing), It has an arbitrary number (or 1) of sub-boards up to the upper limit number for processing. Each sub-board is a board determined by, for example, a combination of an application for an analog line or an ISDN line and a corresponding number of lines (8 lines, 16 lines, 32 lines). However, each lower board has the same configuration as described later with respect to signal exchange with the upper board.

  FIG. 5 is an explanatory diagram showing a mounting image in the unit of the upper board and the lower board.

  A back board 2 is provided on the back side of the unit 1. By fitting the convex connectors of the upper board 3 and the lower boards 4-1 to 4-N into the concave connectors of the back board 2, the upper board is mounted. 3 and lower boards 4-1 to 4-N are attached to the backboard 2. For example, the upper substrate 3 is attached to the right end in the left-right direction of the backboard 2, and the lower substrates 4-1 to 4 -N are attached to the left side of the upper substrate 3. The mounting position of the back board 2 on the upper board 3 is fixed, but the number of lower boards attached to the back board 2 can be any number up to the upper limit number (for example, 20). The position can be changed. FIG. 5 shows a case where the same number of lower substrates 4-1 to 4-N as the upper limit number N are attached. The lower substrate 4-1 is provided at the farthest end when viewed from the upper substrate 3, and the lower substrate 4-N is provided at the closest end when viewed from the upper substrate 3.

  Between the upper substrate 3 and the lower substrates 4-1 to 4-N in the same unit 1, the downward direction from the upper substrate 3 to the lower substrates 4-1 to 4-N is also lower. Also in the upstream direction from N to the upper circuit board 3, transmission data (audio signal) is exchanged by time division multiplexing (TDM) (for transmission of time division multiplexed signals, for example, Patent Literature 1). 1 and Patent Document 2).

  The upper board 3 inserts transmission data to the lower board 4-n in a time slot determined for the lower board 4-n (n is 1 to N) and sends it to the highway in the downstream direction. The clock is also sent in synchronization, and the lower board 4-n takes in the transmission data inserted in the time slot determined for itself using the transmitted clock. Here, since the transmission data and the clock are synchronized, the lower board 4-n can appropriately capture the transmission data.

  When the timing captured based on the clock transmitted from the upper substrate 3 becomes the time slot in the upward direction determined for itself, the lower substrate 4-n is based on the clock transmitted from the upper substrate 3, In that time slot, data to be transmitted to the upper board 3 is inserted and transmitted to the highway FHW in the upstream direction (only the highway in the upward direction is shown in FIG. 5). During this transmission in the upward direction, no clock is transmitted from the lower substrate 4-n to the upper substrate 3, and the upper substrate 3 is connected to the lower substrate 4-n based on the internally generated clock. The transmission data sent to the highway (hereinafter referred to as the upstream highway) FHW is taken in.

  Since the transmission method of the transmission data in the upward direction is as described above, the transmission data that has reached the upper substrate 3 is not synchronized with the clock internally generated by the upper substrate 3. However, conventionally, transmission data can be captured without any problem even in such an asynchronous manner.

  FIG. 6 is an explanatory diagram showing the reason why the upper board 3 can appropriately capture transmission data asynchronous with the clock in the conventional private branch exchange unit.

  The amount of synchronization deviation between the transmission data from the lower board 4-n reaching the upper board 3 and the clock generated internally by the upper board 3 is approximately the propagation delay of the clock given from the upper board 3 to the lower board 4-n. And the propagation delay of transmission data from the lower board 4-n to the upper board 3 is reflected. The propagation delay varies depending not only on the distance of the upstream highway FHW between the upper board 3 and the lower board 4-n but also on the number and arrangement of lower boards connected to the upstream highway FHW. A case where the propagation delay between the upper board 3 and the lower board 4-n when the upper limit number (maximum number) of the lower boards 4-1 to 4-N is connected to the upstream highway FHW is smaller than the number of connections. Greater than propagation delay. Further, even when the same number of lower boards are connected to the upstream highway FHW, the propagation delay varies depending on the arrangement of the lower boards because the impedance and the like seen from the highway side differs for each lower board.

  FIG. 6 (A1) shows one cycle (for example, 122 ns) of a clock internally generated by the upper board 3, and FIG. 6 (A2) shows ideal received data (assumed assumptions) synchronized with the clock. Data and no such received data exists).

  6 (B1) to 6 (B3) each show a case where the lower board is fully attached to the backbird, and the lower board at the nearest end in the case where the arrangement of the lower board has the smallest propagation delay. Transmission data from the board 4-1, transmission data from the lower board at the middle position (lower board 4-10 or 4-11 if N is 20), and the farthest lower board 4-N Represents a 1-bit period of the transmission data, and is shifted from the clock by times Tss, Tsm, and Tsl, respectively. The three types of transmission data are transmitted in different time slots because they are time-division multiplexed. To make it easier to understand the synchronization deviation with the clock, FIG. 6 (B1) to (B3) Assuming that the period of the clock for receiving the transmission data is the same, one bit period of each transmission data is represented (FIG. 6 (C1) to (C3), FIG. 7 (B1) to (B3), FIG. The same applies to (C1) to (C3). FIG. 6 (B4) shows a one-bit period (see FIG. 6 (B1)) of transmission data from the nearest lower substrate 4-1 with the smallest synchronization deviation with the clock and the largest synchronization deviation with the clock. A common period (a common timing period that can be captured by a clock) with a 1-bit period (see FIG. 6B3) of transmission data from the lower-end lower substrate 4-N is shown.

  6 (C1) to (C3) are the cases in which the lower substrate is fully attached to the backbird, and the most proximal end in the case where the lower substrate has the largest propagation delay. Represents the 1-bit period of the transmission data from the lower board 4-1 of the transmission, the transmission data from the lower board at the middle position, and the transmission data from the lower board 4-N at the farthest end. They are shifted by times Tbs, Tbm, and Tbl, respectively. FIG. 6C4 shows the one-bit period (see FIG. 6C1) of the transmission data from the nearest lower substrate 4-1 with the smallest synchronization deviation with the clock and the largest synchronization deviation with the clock. A common period with a 1-bit period (see FIG. 6 (C3)) of transmission data from the lower-end lower substrate 4-N is shown.

  Within the common period shown in FIG. 6 (B4) and the common period shown in FIG. 6 (C4), the length of the upstream highway FHW and the like are generally designed so that transmission data received by the upper board 3 can be taken based on the clock. Therefore, the upper board 3 can appropriately capture the uplink transmission data asynchronous with the clock.

JP 2000-196620 A JP 2001-274817 A

  Recently, it has been studied to increase the number of lines handled by each lower board without changing the size or outer shape of the unit or lower board. In order to increase the number of lines handled by the lower board, it is necessary to increase the number of time slots related to one lower board 4-n in the time division multiplexed signal. In other words, it is necessary to increase the number of time slots accommodated on the highway. If the number of time slots accommodated on the highway is increased without changing the clock speed, the time slot interval of the same lower board becomes longer, which is a serious problem for an audio signal for which real-time communication is desired by eliminating communication delay as much as possible. For this reason, even if the number of time slots accommodated on the highway is increased, the clock speed is increased (for example, about 6 times) so that the time slot interval of the same channel is the same as before.

  However, since only the clock speed is increased without changing the size or external shape of the unit or lower board, the upper board 3 is more likely to be unable to capture transmission data asynchronous with the clock from the upstream highway FHW. It was.

  FIG. 7 is an explanatory view of this problem and corresponds to FIG. 6 described above.

  When the clock becomes high speed (for example, one cycle is 20.4 ns), the 1-bit period of transmission data flowing through the upstream highway is also shortened (for example, see FIG. 7A2).

  Even if the clock becomes high speed (hereinafter, the high-speed clock may be referred to as a high-speed clock), the transmission data from the lower board 4-n reaching the upper board 3 and the high speed generated internally by the upper board 3 The amount of synchronization deviation from the clock generally reflects the propagation delay of the high-speed clock given from the upper substrate 3 to the lower substrate 4-n and the propagation delay of the transmission data from the lower substrate 4-n to the upper substrate 3. The amount of synchronization deviation related to the high-speed clock is almost the same as the amount of synchronization deviation related to the previous clock (before high speed). . That is, when the clock is made high speed, the 1-bit period is shortened, whereas the transmission data from the lower board 4-n reaching the upper board 3 and the amount of synchronization deviation between the high-speed clock generated internally by the upper board 3 Is the same as before.

  Therefore, when the lower board is fully attached to the backbird and the arrangement of the lower board is the arrangement with the smallest propagation delay, transmission from the nearest lower board 4-1 with the smallest synchronization deviation with the high-speed clock is performed. A 1-bit period of data (see FIG. 7B1), a 1-bit period of transmission data from the farthest lower-level board 4-N having the largest synchronization deviation with the high-speed clock (see FIG. 7B3), and The common period (see FIG. 7B4) is short. In addition, when the lower board is fully attached to the back bird and the arrangement of the lower board is the arrangement in which the propagation delay is the largest, the transmission from the lower-most board 4-1 with the smallest synchronization deviation with the high-speed clock is performed. 1-bit period of data (see FIG. 7 (C1)), 1-bit period of transmission data from the farthest lower-level board 4-N having the largest synchronization deviation with the high-speed clock (see FIG. 7 (C3)), The common period (see FIG. 7 (C4)) is short. There is very little time in common between the two common periods (FIG. 7 shows the case where there is none).

  In such a case, even if the timing of the high-speed clock is adjusted so that the transmission data from each lower board in any situation can be appropriately captured, the lower board can be replaced by the additional arrangement or replacement of the lower board. It is easily changed to a state where the transmission data cannot be taken in.

  Further, as described above, if the timing of the high-speed clock is not adjusted, there is a possibility that the transmission data from the lower board cannot be taken in even when the lower board is initially mounted.

  Therefore, when the clock speed is high as viewed from the propagation delay on the highway, the common receiver can properly capture the time division multiplexing signals transmitted from multiple transmitters at different timings. A division multiplexing signal transmission apparatus, a time division multiplexing signal reception apparatus, and a time division multiplexing signal transmission system are desired.

  The first aspect of the present invention inserts a serial signal in a time division multiplexing time slot assigned to the time division multiplexing signal transmitter in synchronization with the clock from the time division multiplexing signal receiver, and In a signal transmission device for time division multiplexing that is sent to a serial signal transmission path to a multiplexed signal receiving device, it has serial signal generating means for generating the serial signal including a transmission data body and a start bit string located on the front side thereof. Features.

  According to a second aspect of the present invention, each of a plurality of time division multiplexing signal transmission apparatuses synchronizes with a clock from the time division multiplexing signal reception apparatus, and time division multiplexing time allocated to the time division multiplexing signal transmission apparatus. In a time division multiplex signal receiving apparatus for inserting a serial signal into a slot and receiving a signal sent to a serial signal transmission path to the time division multiplex signal receiving apparatus, (1) each of the time division multiplex signal transmitting apparatuses is Window information storage means for storing for each time-division multiplexing signal transmitter the information of the significant period of the window pulse for detecting the start bit string in the transmitted serial signal, and (2) the serial signal of the time slot coming from now The information of the time division multiplexing signal transmitter according to the above is extracted from the window information storage means and synchronized with the internally generated clock. A start bit string detecting means for detecting a start bit string by setting a window width for detecting a start bit string and having a period that is an integral multiple of the clock cycle; and (3) a start bit string in response to detection of the start bit string. And transmission data fetching means for fetching the transmission data main body following.

  According to a third aspect of the present invention, a serial signal is inserted into a time slot of an assigned time division multiplex in synchronization with a single time division multiplex signal receiving apparatus and a clock from the time division multiplex signal receiving apparatus. In a time division multiplex signal transmission system comprising a plurality of time division multiplex signal transmission devices to be transmitted to a serial signal transmission path to a time division multiplex signal reception device, (1) as each time division multiplex signal transmission device, The time division multiplexing signal transmitter of 1 of the present invention is applied, and the time division multiplexed signal receiver of the second aspect of the present invention is applied as the time division multiplexed signal receiver.

  According to the present invention, a time division multiplexing signal transmission device, a time division multiplexing signal reception device, and a common reception device that can appropriately capture time division multiplexing signals transmitted from a plurality of transmission devices at different timings, and A time division multiplex signal transmission system can be realized.

It is explanatory drawing which shows the time slot structure in 1st Embodiment. It is a block diagram which shows the specific structural example of the signal transmission apparatus for time division multiplexing of 1st Embodiment. It is a block diagram which shows the specific structural example of the time division multiplex signal receiver of 1st Embodiment. It is a block diagram which shows the structure of the time division multiplex signal receiver of 2nd Embodiment. It is explanatory drawing which shows the mounting image in the unit of a high-order board | substrate and a low-order board | substrate. It is explanatory drawing of the reason the conventional high-order board | substrate can take in the uplink transmission data asynchronous with a clock appropriately. When a clock is made high-speed, it is explanatory drawing of the reason the conventional high-order board | substrate cannot take in the uplink transmission data asynchronous with a clock appropriately.

(A) First Embodiment Hereinafter, a first embodiment in which a time division multiplexing signal transmitting apparatus, a time division multiplexing signal receiving apparatus, and a time division multiplexing signal transmission system according to the present invention are applied to a private branch exchange will be described. The description will be given with reference.

  The time division multiplexing signal transmission apparatus of the first embodiment is mounted on the lower board of the private branch exchange, and the time division multiplexing signal reception apparatus of the first embodiment is mounted on the upper board of the private branch exchange. The arrangement of the lower boards and the upper boards in the private branch exchange is as shown in FIG. 5 described above, and the reference numerals shown in FIG. 5 are also used as appropriate in the description of the first embodiment.

(A-1) Configuration of one time slot according to the first embodiment The private branch exchange according to the first embodiment includes a unit in the unit without changing the size or external shape of the unit or the lower board in the private branch exchange. The clock speed of (1) is higher than before (for example, about 6 times). Therefore, if no measures are taken, the above-described problems occur in transmission of upstream transmission data from the lower board to the upper board.

  Therefore, in the first embodiment, the structure of one time slot from the lower board to the upper board is shown in FIG. 1, and the time slot having such a structure is mounted on the lower board so that it can be exchanged appropriately. The time division multiplexing signal transmission device and the time division multiplexing signal reception device mounted on the upper substrate are configured as described later.

  As shown in FIG. 1A, one time slot TS (..., TS- (n + 1), TS-n,...) In the uplink time division multiplexed signal in the first embodiment is a first predetermined value. Transmission data body DAT having the number of bits, start bit string ST having a second predetermined number of bits provided at the head of transmission data body DAT, and front dummy bit string having a third predetermined number of bits provided in front of start bit string ST It is composed of FDMY and a rear dummy bit string BDMY of the fourth predetermined number of bits provided on the rear side of the transmission data body DAT.

  The transmission data body DAT is 64 bits, for example. When the transmission source lower board 4-n handles channels of multiples of 8, the above-described 64 bits are a bit string of 8 channels of 8 bits per channel.

  The start bit string ST is a mixture of a high logic level “1” and a low logic level “0” (hereinafter, the expression of a high logic level and a low logic level is omitted). It becomes. As shown in FIGS. 7C1 to 7C3 described above, the transmission data from the lower board 4-n that has reached the upper board 3 is one bit period of the high-speed clock with respect to the high-speed clock generated by the upper board 3. A longer out of sync may occur. Therefore, if nothing is done, it may happen that the bit taken by the upper board 3 as the first bit of the transmission data (that is, the first bit of the time slot) is not the first bit.

  Therefore, in the first embodiment, the start bit string ST is provided in front of the transmission data body DAT so that the upper substrate 3 can detect the start timing of the transmission data body DAT. As will be described later, since the dummy bit strings FDMY and BDMY are all “1”, a bit string in which “1” and “0” are mixed is applied as the start bit string ST.

  The upper substrate 3 of the first embodiment has a significant window pulse (“0” level as shown in FIG. 1B) for each time slot TS (..., TS- (n + 1), TS-n,...). Level) WP (..., WP- (n + 1), WP-n,...) Is set and the arrival of the start bit string ST is monitored.

  As described above, the amount of synchronization shift with respect to the clock of adjacent time slots (for example, TS- (n + 1), TS-n) in the time-division multiplexed signal in the uplink direction is not the same due to the difference in propagation delay. The time division multiplexing signal (time slot TS- (n + 1)) from the lower board 4- (n + 1) and the time division multiplexing signal (time slot TS-n) from the lower board 4-n are overlapped or empty. It is ideal to reach the upper substrate 3 without occurring, but such an ideal situation does not occur due to the difference in the amount of synchronization deviation described above. In other words, adjacent time slots that have reached the upper board 3 overlap, and there is a possibility that several bits on the end side of one time slot and several bits on the other start side are destroyed by collision.

  For example, if only the start bit string ST is added, the start bit string ST may overlap with the data at the end of the previous time slot due to the mounting condition in one unit, and may be destroyed.

  Therefore, in the first embodiment, all “1” dummy bit strings FDMY and BDMY are provided. The dummy bit string may be provided on at least one of the front side or the rear side, but in the first embodiment, the dummy bit string is provided both before and after. For example, a 2-bit dummy bit string FDMY is provided on the front side, and a 4-bit dummy bit string BDMY is provided on the rear side.

  In the first embodiment, the driver unit that drives the serial signal line from the lower substrate 4-n connected to the upstream highway FHW is set to high impedance, and the output side of the driver is pulled up, thereby providing a dummy. The bit “1” is realized. Thus, for example, even if a dummy bit from a certain lower board and a valid bit (transmission data body or start bit string bit) of another lower board overlap on the upstream highway FHW, the logical level on the upstream highway FHW Becomes the logic level of the effective bits of the other lower boards, and can prevent the effective bits of the other lower boards from being destroyed.

  Note that the window width of the window pulse WP (..., WP− (n + 1), WP−n,...) Shown in FIG. 1B is the sum of the number of bits in the front dummy bit string FDMY and the number of bits in the start bit string ST. It has a width corresponding to the number of bits.

  For example, when the transmission data body DAT is 64 bits, the start bit string ST is 2 bits, the front dummy bit string FDMY is 2 bits, and the rear dummy bit string BDMY is 4 bits, the number of bits in one time slot is 72 bits, The speed of the high-speed clock is determined based on the fact that a 72-bit bit value is inserted in the period. That is, the speed of the high-speed clock is determined based not on the speed of the high-speed clock based on the fact that only 64 bits of data are inserted in one time slot but also on the start bit string and dummy bit string. .

(A-2) Configuration of First Embodiment The time division multiplexing signal transmitter of the first embodiment mounted on the lower board 4-n is at the timing of the uplink time slot related to the lower board mounted. As long as it has a configuration capable of generating and transmitting a bit string of the time slot TS shown in FIG. 1, the specific configuration is not limited.

  FIG. 2 is a block diagram illustrating a specific configuration example of the time division multiplexing signal transmission apparatus according to the first embodiment. FIG. 2 shows a time division multiplexing signal transmission apparatus 10 (in FIG. 2, the symbol branch number “-n” is omitted) mounted on a certain lower board 4-n.

  In the following description, it is assumed that one time slot is 72 bits in total, that is, transmission data body DAT is 64 bits, start bit string ST is 2 bits, front dummy bit string FDMY is 2 bits, and rear dummy bit string BDMY is 4 bits. . 3 will be described later, assuming that one time slot is 72 bits in total.

  The time division multiplexing signal transmitter 10 includes a shift register unit 11, a start bit string register 12, a driver unit 13, a pull-up resistor 14, a pull-up switch 15, and a transmission timing control unit 16.

  Here, the time division multiplexing signal transmitter 10 is connected to one end of the serial signal line 17 (FHW-n), and the other end of the serial signal line 17 is connected to the upstream highway FHW (the main body thereof). That is, the serial signal line 17 is a branch line of the upstream highway FHW that connects the time division multiplexing signal transmitter 10 (10-n) to the upstream highway FHW (the main body).

  The shift register unit 11 is provided for parallel / serial conversion. Under the control of the transmission timing control unit 16, the start bit string ST and the transmission data body DAT are input (set) in parallel. A shift operation is performed based on a clock from the transmission timing control unit 16 to serially output the start bit string ST and the transmission data body DAT.

  The start bit string register 12 holds a 2-bit start bit string ST (for example, “10”), and the held start bit string ST is set at the head side of the shift register unit 11 described above.

  The driver unit 13 is controlled by the transmission timing control unit 16 to a high impedance or controlled to a serial data passing state, and a start bit string given from the shift register unit 11 when the serial data is passing. The ST and the transmission data body DAT are sent out to the serial signal line 17.

  The pull-up resistor 14 is for pulling up the serial signal line 17, and the pull-up switch 15 is turned on under the control of the transmission timing control unit 16 to connect the pull-up resistor 14 to the serial signal line 17. To perform pull-up. Here, the pull-up switch 15 is turned on only during the period of the front dummy bit string FDMY and the rear dummy bit string BDMY.

  The transmission timing control unit 16 controls each unit of the time division multiplexing signal transmission apparatus 10 so that the serial signal line 17 transmits the time slot TS having the configuration shown in FIG. Specific control by the transmission timing control unit 16 will be clarified in the description of the operation described later.

  The time division multiplexing signal receiving apparatus according to the first embodiment mounted on the upper board is time-division multiplexed that arrives via the upstream highway FHW, in which time slots having the configuration shown in FIG. It is only necessary to have a configuration capable of receiving a signal by applying a high-speed clock generated internally, and the specific configuration is not limited.

  FIG. 3 is a block diagram illustrating a specific configuration example of the time division multiplexed signal receiving apparatus according to the first embodiment.

  The time division multiplex signal receiver 20 includes a clock generation unit 21, a receiver unit 22, a data shift register unit 23, an ST detection shift register unit 24, a start bit string register 25, a 2-bit comparison unit 26, a window pulse generation unit 27, Each sub-board window information storage unit 28 and reception timing control unit 29 are provided.

  The clock generation unit 21 generates a clock that is transmitted to the downlink highway in synchronization with the time-division multiplexed signal in the downlink direction and that is applied to capture of the time-division multiplexed signal in the uplink direction from the uplink highway FHW. Therefore, the clock generation unit 21 is a component of the time division multiplexed signal reception device 20 and a component of a downlink transmission device (not shown).

  The receiver unit 22 receives the time-division multiplexed signal (serial signal) in the upstream direction that has arrived from the upstream highway FHW and takes it in. The serial signal received by the receiver unit 22 is supplied to the data shift register unit 23 and the ST detection shift register unit 24.

  The data shift register unit 23 can hold 64 bits provided for serial / parallel conversion. The data shift register unit 23 takes in the serial data received by the receiver unit 22 based on the clock, and the 64 bits held in the data shift register unit 23 are illustrated at the timing when the 64 bits of the transmission data body become. The data is not output in parallel to the data acquisition unit.

  The ST detection shift register unit 24 takes in the serial data received by the receiver unit 22 based on the clock and holds the two most recent bits. The 2 bits held in the ST detection shift register unit 24 are used to determine whether or not the 2 bits are a start bit string ST. Although different from FIG. 3, the ST detection shift register unit 24 may also operate only with a window width described later.

  The start bit string register 25 holds the start bit string ST as a comparison target in order to detect the start bit string ST in the received serial data.

  The 2-bit comparison unit 26 uses the window pulse generated from the window pulse generation unit 27 to display the most recent 2 bits held in the ST detection shift register unit 24 and the start bit sequence ST held in the start bit sequence register 25. The comparison is performed in synchronization with the clock in the WP significant level period (window width), and a comparison result indicating whether or not the most recent 2 bits are the start bit string ST is given to the reception timing control unit 29.

  The window pulse generation unit 27 generates a window pulse WP having a 4-bit window width for detecting a start bit string ST of a time slot TS that will come from now under the control of the reception timing control unit 29. is there. The window pulse WP has a window width intended for 4 bits of the front dummy bit string FDMY and the start bit string ST.

  The window information storage unit 28 for each lower board starts the window width (significant level period) in the generated window pulse for each lower board 4-1 to 4 -N, in other words, for each time slot of the upstream time division multiplexed signal. Is stored. For example, the reception start timing of the time slot TS-n from a certain lower board 4-n is X clock periods from the ideal timing (timing synchronized with the clock) determined by counting the clocks generated by the clock generation unit 21. (X is 0 or a positive integer, and if the amount of deviation is not an integer, it is the closest integer). If it is delayed, the window pulse is significantly delayed by an X clock period from the ideal timing. Is stored in the window information storage unit 28 for each lower board. This information may be the same content, but is information determined for each of the lower substrates 4-1 to 4-N.

  In the case of the first embodiment, the designer or the private branch exchange installer stores the window information for each lower board based on the propagation delay between the upper board 3 and the lower board 4-n. The unit 28 is set in advance.

  The reception timing control unit 29 can appropriately capture the transmission data body DAT inserted in the time slots TS-1 to TS-N from the lower boards 4-1 to 4-N, which arrives from the upstream highway FHW. Each part of the time division multiplex signal receiving apparatus 20 is controlled so that it can be performed. Specific control by the reception timing control unit 29 will be clarified in the description of the operation described later.

(A-3) Operation of the First Embodiment The operation of the time division multiplexing signal transmitter 20 of the first embodiment having the specific configuration example shown in FIG. 2 and the specific configuration example in FIG. The operation of the time division multiplex signal receiver 30 of the first embodiment showing the above will be described in order.

  The higher-order board 3 transmits a control signal (or a control signal that notifies the start timing of the uplink time slot) that notifies the start timing of the entire time-division multiplexed signal in the uplink direction or a high-speed clock generated by the clock generator 21. As appropriate, the data is sent to the lower substrates 4-1 to 4-N.

  The transmission timing control unit 16 of the lower board 4-n (hereinafter, description of the branch number “-n” is omitted) to which such a control signal and clock are given is set to the timing of the next time slot TS from itself. Recognizing the period until it is determined (which can be specified by the clock count), first, the start register ST and the transmission data body DAT are set in the shift register unit 11 at a predetermined timing before the next time slot TS. At this time, the driver unit 13 is set to high impedance and the pull-up switch 15 is turned off.

  At the start timing of the time slot TS, the transmission timing control unit 16 turns on the pull-up switch 15 for two clock cycles in synchronization with the reception clock while keeping the driver unit 13 in a high impedance state. , The upstream highway FHW) is loaded with a 2-bit front dummy bit string FDMY.

  Subsequently, the transmission timing control unit 16 sets the driver unit 13 in a state in which the serial signal line 17 can be driven, turns off the pull-up switch 15, and sets the start bit string set in the shift register unit 11 based on the reception clock. ST and 64 bits of transmission data body DAT are serially output in order. Since the driver unit 13 is ready to drive the serial signal line 17, the start bit string ST serially output from the shift register unit 11 and the 64 bits of the transmission data body DAT are serial signal line 17 (accordingly, the upstream highway FHW). ) Sequentially.

  When the serial output from the shift register unit 11 is completed, the transmission timing control unit 16 immediately switches the driver unit 13 to high impedance, turns on the pull-up switch 15 in synchronization with the reception clock, and turns it on for four clock cycles. The 4-bit rear dummy bit string BDMY is placed on the line 17 (accordingly, the upstream highway FHW).

  When the transmission operation related to the current time slot is completed as described above, the transmission timing control unit 16 turns off the pull-up switch 15 while keeping the driver unit 13 in a high impedance state, and the serial signal line 17 (accordingly, the upstream line). The bit value cannot be transmitted to the highway (FHW) (the logical connection with the serial signal line 17 is cut off), and a standby state is prepared for a new time slot.

  Next, the operation of the time division multiplexed signal receiving apparatus 30 of the first embodiment in which the time slots TS-1 to TS-N sequentially transmitted from the lower boards 4-1 to 4-N arrive will be described.

  As described above, the upper substrate 3 is generated by the control signal (or the control signal notifying the start timing of the uplink time slot) or the clock generation unit 21 that notifies the start timing of the entire time division multiplexed signal in the uplink direction. A high-speed clock is appropriately sent to the lower substrates 4-1 to 4-N.

  Such a control signal and clock are also given to the reception timing control unit 29, and the reception timing control unit 29 performs the current processing based on the start timing specified by the control signal, the number of clock counts from the start timing, and the like. You can recognize the time slot you are serving.

  The reception timing control unit 29 determines that the elapsed time from the time slot TS- (n-1) currently being received is a predetermined period (the number of clock counts since the start bit string of the time slot being received is detected). The window information for the lower board 4-n related to the next time slot TS-n is fetched from the window information storage unit 28 for each lower board, and the window pulse WP determined according to the fetched window information is used as the window pulse. It controls so that the production | generation part 27 produces | generates.

  The serial signal (time division multiplexed signal) on the upstream highway FHW is received by the receiver unit 22 and then given to the data shift register unit 23 and the ST detection shift register unit 24. The data is serially taken into the shift register unit 23 and the ST detection shift register unit 24.

  The ST detection shift register unit 24 can hold only the two most recently input bits, and discards past inputs. The 2 bits held in the ST detection shift register unit 24 are output in parallel to the 2-bit comparison unit 26. Further, the 2-bit start bit string ST held in the start bit string register 25 is also output in parallel to the 2-bit comparison unit 26.

  In the 2-bit comparison unit 26, when the window pulse WP is significant (when it is the window width), the 2-bit comparison unit 26 holds the latest 2 bits held in the ST detection shift register unit 24 and the start bit string register 25. The received start bit string ST is compared in synchronization with the clock, and when the two bits completely match, a comparison result indicating detection of the start bit string ST is given to the reception timing control unit 29.

  At this time, the reception timing control unit 29 recognizes that the transmission data portion DAT in the time slot TS-n is serially input thereafter, and 64 bits that have arrived thereafter accumulate in the data shift register unit 23. At the timing, the data shift register unit 23 is instructed to perform parallel output, and the processing unit (not shown) to which the parallel output transmission data portion DAT is given is instructed.

  As described above, the reception timing control unit 29 relates to the next time slot TS- (n + 1) at a predetermined timing during a period in which the transmission data portion DAT of the time slot TS-n is sequentially serially input. Processing is performed so that window information about the lower substrate 4- (n + 1) is fetched from the window information storage unit 28 for each lower substrate.

(A-4) Effects of First Embodiment According to the first embodiment, since the start bit string is included in the time slot in the upward direction from the lower board to the upper board, the number and arrangement of lower boards are arranged. For example, the timing at which the time slot from each lower board reaches the upper board and the amount of synchronization deviation with the clock are different for each lower board, and the time when the synchronization deviation amount is larger than one cycle of the clock. Even if there is a slot, the upper board can appropriately capture the transmission data body from each lower board.

  Further, according to the first embodiment, when at least one of the start bit string and the front side or rear side of the group of transmission data bodies overlaps with the bit value of another time slot on the upstream highway FHW, the bit value is Since the dummy bit that can be added to the bit value of the upstream highway FHW is added as it is, the bit value in one time slot (the bit value of the start bit string and the transmission data body) is changed to the bit value in the other time slot. It is possible to prevent destruction.

  In order to achieve the above effects, the number of lines handled by each lower board is increased without changing the size or outer shape of the unit or lower board. The transmission data main body can be appropriately transmitted from one to the upper board.

(B) Second Embodiment Next, a second embodiment in which the time division multiplexing signal transmitting apparatus, time division multiplexing signal receiving apparatus and time division multiplexing signal transmission system according to the present invention are applied to a private branch exchange will be described. Will be described with reference to FIG.

  The second embodiment mainly differs from the first embodiment in the internal configuration and function of the time division multiplex signal receiving apparatus.

  FIG. 4 is a block diagram showing the configuration of the time division multiplexed signal receiving apparatus according to the second embodiment. The same or corresponding parts as those in FIG. 3 according to the first embodiment are given the same or corresponding reference numerals. Show.

  The time division multiplexed signal receiving apparatus 20A of the second embodiment includes a clock generation unit 21, a receiver unit 22, a data shift register unit 23, an ST detection shift register unit 24, a start bit string register 25, a 2-bit comparison unit 26, In addition to the window pulse generation unit 27, the lower substrate-specific window information storage unit 28, and the reception timing control unit 29, the lower substrate-specific window information formation unit 30, the propagation delay measurement unit 31 and the propagation delay / window information conversion unit 32 are provided.

  The window information forming unit 30 for each lower board automatically detects, for example, a change in the lower board when instructed by the operator that the lower board has been increased or decreased or the arrangement of the lower board has been changed. Window information to be stored in the window information storage unit 28 for each lower substrate is overwritten in the window information storage unit 28 for each lower substrate.

  The window information forming unit 30 for each lower board propagates the propagation delay between the lower board 4-n and the upper board 3 from which window information is to be formed (the round-trip propagation delay may be a one-way propagation delay in the upward direction). Measurement is performed by the delay measuring unit 31. The propagation delay measuring unit 31 measures the propagation delay between the lower board 4-n and the upper board 3 by applying an existing method for measuring the propagation delay between two communication elements. The propagation delay / window information conversion unit 32 stores window information indicating how many clock cycles are shifted from the ideal timing to start the window width for each propagation delay range. The window information forming unit 30 for each lower board extracts window information associated with the range to which the measured propagation delay belongs, and forms window information as window information about the lower board 4-n to be updated. It overwrites the corresponding part of the window information storage unit 28 for each lower substrate.

  In the above, the case where the information in the window information storage unit 28 for each lower board is updated has been described. However, the above-described operation may be executed when information is written in the window information storage unit 28 for each lower board for the first time. .

  According to the second embodiment, the timing of the window width of the window pulse WP can be reviewed.

  As a result, even if the lower board is increased or decreased or the arrangement of the lower board is changed, the upper board can appropriately capture the transmission data body from each lower board.

(C) Other Embodiments In the description of each of the above embodiments, various modified embodiments have been mentioned, and further modified embodiments as exemplified below can be given.

  In the above embodiments, the time slot configurations of all the lower boards are the same. However, the number of bits of the front and rear dummy bit strings may be changed depending on the lower boards.

  In the second embodiment, the window width timing of the window pulse WP is reviewed. However, in addition to this, the number of bits in the dummy bit string may be reviewed. For example, the propagation delay / window information conversion unit 32 may store the window information and the number of bits of the dummy bit string for each propagation delay range, and obtain the number of bits of the dummy bit string. The number of bits of the obtained dummy bit string is notified to the corresponding lower board via the control signal line or the like, and the serial signal line is set to “1” only for a period corresponding to the number of bits of the dummy bit string notified by the lower board. A pull-up operation may be performed.

  The start bit string and the front and rear dummy bit strings described above use the expression “bit string”, but may be composed of only one bit.

  In each of the above embodiments, the case where the present invention is applied to the time division multiplex transfer from the lower board to the upper board of the private branch exchange is shown, but the application of the present invention is not limited to this, and a plurality of transmissions The present invention can be widely applied to any time division multiplexing signal transmission system in which a common receiving device takes in signals for time division multiplexing transmitted from devices at different timings.

TS: Time slot, DAT: Transmission data body, ST: Start bit string, FDMY: Front dummy bit string, BDMY ... Rear dummy bit string,
DESCRIPTION OF SYMBOLS 10 ... Signal transmission apparatus for time division multiplexing, 11 ... Shift register part, 12 ... Start bit string register, 13 ... Driver part, 14 ... Pull-up resistor, 15 ... Pull-up switch, 16 ... Transmission timing control part, 17 ... Serial signal line,
DESCRIPTION OF SYMBOLS 20, 20A ... Time division multiplexed signal receiver, 21 ... Clock generation part, 22 ... Receiver part, 23 ... Data shift register part, 24 ... ST detection shift register part, 25 ... Start bit string register, 26 ... 2-bit comparison 27: Window pulse generator, 28 ... Sub-substrate window information storage unit, 29 ... Reception timing control unit, 30 ... Sub-substrate window information formation unit, 31 ... Propagation delay measurement unit, 32 ... Propagation delay / window information Conversion part.

Claims (5)

In synchronization with the clock from the time division multiplex signal receiver, a serial signal is inserted into the time division multiplex time slot assigned to the time division multiplex signal transmitter, and serial to the time division multiplex signal receiver. In the signal transmission device for time division multiplexing to be sent to the signal transmission path,
A signal transmission apparatus for time division multiplexing, comprising serial signal generation means for generating the serial signal including a transmission data body and a start bit string located in front of the transmission data body. The serial signal generation means generates the serial signal in which a dummy bit string is located on at least one of the front side of the start bit string and the rear side of the transmission data body,
The bit value on the serial signal transmission line when each bit value of the dummy bit string overlaps the start bit string or the transmission data body sent from another time division multiplexing signal transmission device on the serial signal transmission line 2. The signal transmission apparatus for time division multiplexing according to claim 1, wherein the start bit string transmitted from another signal transmission apparatus for time division multiplexing or the bit value of the transmission data body is generated. . Each of the plurality of time division multiplexing signal transmitters inserts a serial signal in a time division multiplexing time slot assigned to the time division multiplexing signal transmitter in synchronization with the clock from the time division multiplexing signal receiver. In the time division multiplex signal receiving device for receiving the signal sent to the serial signal transmission path to the time division multiplex signal receiving device,
Window information storage means for storing, for each time division multiplexing signal transmitter, information on a significant period of a window pulse for detecting a start bit string in the serial signal transmitted by each of the time division multiplexing signal transmitters;
Information on the time division multiplexing signal transmission device related to the serial signal of the time slot coming from now is extracted from the window information storage means, and has a period that is an integral multiple of the cycle of the clock in synchronization with the internally generated clock. A start bit string detecting means for detecting a start bit string by setting a window width for detecting the start bit string;
A time division multiplexed signal receiving apparatus comprising: transmission data fetching means for fetching a transmission data body following the start bit string in response to detection of the start bit string. Propagation delay / window information storage means for storing a range to which a propagation delay between any of the above signal transmission devices for time division multiplexing belongs, and information of a significant period of a window pulse associated with the range,
Propagation delay measuring means for measuring the propagation delay between any of the above time division multiplexing signal transmitters,
Based on the measured propagation delay, information on the significant period of the window pulse associated with the range to which the propagation delay belongs is obtained, and the time division multiplexing signal in which the propagation delay is measured in the window information storage means The time division multiplexed signal receiving apparatus according to claim 3, further comprising window information writing means for describing information of the transmitting apparatus. A serial signal is inserted into the assigned time division multiplexing time slot in synchronization with the clock from the only time division multiplexing signal reception device and the time division multiplexing signal reception device to the time division multiplexing signal reception device. In a time division multiplexing signal transmission system comprising a plurality of time division multiplexing signal transmission devices for sending to a serial signal transmission line of
While applying each of the time division multiplexing signal transmission devices according to claim 1 as the time division multiplexing signal transmission device,
4. A time division multiplexed signal transmission system, wherein the time division multiplexed signal receiving apparatus according to claim 3 is applied as the time division multiplexed signal receiving apparatus.

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