JP2006141017A - Synchronizer for transferring data from a first system to a second system - Google Patents

Abstract

An efficient method and means for transmitting data across domain boundaries is provided.
A second system for receiving data based on a third clock (103D) from a first system (102) for transmitting data based on a first clock (103A) and a second clock (103B). Synchronizer (104) for passing data to the system (106) of the first embodiment, comprising a first set (204A-C) of flip-flops that receive data from the first system based on a first clock apparatus. The synchronizer includes a second set (204B, 204D) of flip-flops that receive data from the first system based on a second clock. The synchronizer includes a first multiplexer (206) connected to the outputs of the flip-flops in the first set and the second set. The synchronization device controls the first multiplexer based on the third clock, and outputs data from the selected flip-flop among the flip-flops, thereby generating output data to be supplied to the second system. A control device (212) is included.
[Selection] Figure 2

Description

  Many data communication applications require the transmission of digital data across domain boundaries. A domain boundary is a boundary between two systems operating with different clock signals. Data transmission beyond the boundary is usually performed using a synchronizer.

  Some existing synchronizers are relatively complex devices that perform full handshake operations and are designed to function as a general synchronization means. Implementing such a synchronizer is generally not very efficient (eg in terms of gate count).

  Therefore, in this technical field, in order to transmit data across domain boundaries with minimum error, and between a first system that transmits data with a dual clock and a second system that receives data with a single clock. There is a need for further improvements in systems and technologies for specific applications such as transmitting data.

  According to an embodiment of the present invention, data is received from a first system that transmits data based on a first clock and a second clock to a second system that receives data based on a third clock. A passing synchronizer is obtained. The synchronizer includes a first set of flip-flops that receive data from the first system based on a first clock. The synchronizer includes a second set of flip-flops that receive data from the first system based on a second clock. The synchronizer includes a first multiplexer connected to the outputs of the flip-flops in the first set and the second set. The synchronization device generates output data to be supplied to the second system by controlling the first multiplexer based on the third clock and outputting the data from the selected flip-flop among the flip-flops. Including a control device.

  In the detailed description of the invention, reference is made to the accompanying drawings that illustrate, by way of illustration, specific embodiments for carrying out the invention. Other embodiments may be used and structural or logical changes may be made without departing from the scope of the invention. Accordingly, the detailed description of the invention should not be construed in a limiting sense. The scope of the invention is defined in the claims.

  FIG. 1 is a block diagram showing a communication system 100 according to an embodiment of the present invention. The communication system 100 includes a system A 102, a synchronization device 104, and a system B 106. In the illustrated embodiment, system A 102 functions as a data source, ie, a data transmitter, and system B 106 functions as a receiver, ie, a data sink, that receives data transmitted from system A 102. System A102 is connected to synchronization device 104 via communication links 103A-C. The system A102 outputs two clock signals (clock A and clock B) to the synchronization device 104 via the communication links 103A and 103B. System A outputs a digital data signal (data_in) to synchronization device 104 via communication link 103C. The system B106 outputs a clock signal (clock C) to the synchronization device 104 via the communication link 103D. System B 106 receives a digital data signal (data_out) from synchronizer 104 via communication link 103E.

  In one embodiment, system A102 is located in a first clock domain and system B106 is located in a second clock domain that is different from the first clock domain. In one embodiment, the first clock domain and the second clock domain are coherent (synchronized) clock domains. In the embodiment of FIG. 1, two clocks (clock A and clock B) are arranged in the first clock domain, and one clock (clock C) is arranged in the second clock domain. The method described herein is also applicable when each of the two clock domains has one clock. In one embodiment, the frequency of clock signal A and clock signal B that system A 102 outputs to communication link 103A is the same and the phase is 180 degrees different. The clock signal C output from the system B 106 to the communication link 103D is twice the frequency of the clock signal A and the clock signal B. In one embodiment, clock signal A and clock signal B are each 62.5 MHz clock signals and clock signal C is a 125 MHz clock signal. In this embodiment, the data word is input to the synchronizer 104 at 125 MHz using two different clocks (clock A and clock B), while the data word is input at 125 MHz using one clock (clock C). Input to the system B106. In one embodiment, system B 106 derives clock signal C from clock signal A or clock signal B. FIG. 4 shows an embodiment of clock signal A, clock signal B, and clock signal C. Hereinafter, FIG. 4 will be described.

  In one embodiment, the communication system 100 uses “8B10B” encoding. In 8B10B encoding, each 8-bit word data is associated with a 10-bit code word. In one embodiment, 10-bit codewords are transferred to and from synchronizer 104 according to a clock at a rate of 125 MHz. In other embodiments, other communication protocols and other speeds may be used.

The synchronization device 104 according to an embodiment is a first-in first-out (FIFO) synchronization device that can transfer data between the system A 102 and the system B 106 with high reliability. In one embodiment, synchronizer 104 transmits data words generated from system A 102 at one clock rate to system B 106, which removes those data words at another clock rate. In one embodiment, the synchronizer 104 is configured to operate in applications that meet the following conditions:
(1) Only the phase relationship between the two clock domains is unknown (that is, the clocks are coherent and the magnitude of a certain phase difference is unknown).
(2) Clock jitter is less than one clock cycle.
(3) The flow of data output from the transmitter (that is, the system A 102) cannot be stopped.

  FIG. 2 is a schematic diagram illustrating a synchronization device 104 according to an embodiment of the present invention. Synchronizer 104 includes multiplexers 202A-D (collectively referred to as multiplexer 202), flip-flops 204A-D (collectively referred to as flip-flop 204), multiplexers 206, 208, flip-flop 210, state machine or controller 212, and Flip-flops 214 and 216 are included. In this specification, the flip-flop 204 is sometimes referred to as a register 204. Each multiplexer 202 has two inputs (“0” input, “1” input) and one output. Each flip-flop 204, 210, 216 has one data input (“in”), one data output (“out”), and one clock input (“clk”). The flip-flop 214 has one data input (“in”), two data outputs (“out1”, “out2”), and one clock input (“clk”).

  The “0” inputs of multiplexers 202A and 202B and the “1” inputs of multiplexers 202C and 202D are connected to communication link 103C (data_in). The “1” inputs of multiplexers 202A and 202B are connected to the outputs of flip-flops 204A and 204B, respectively. The “0” inputs of multiplexers 202C and 202D are connected to the outputs of flip-flops 204C and 204D, respectively. The outputs of multiplexers 202A-D are connected to the inputs of flip-flops 204A-D via communication links 203A-D, respectively. The multiplexer 202 receives a control signal or selection signal from the communication link 215A connected to the first output (out1) of the flip-flop 214. When the select signal is low (eg, logic 0), each multiplexer 202 outputs a signal to the “0” input of multiplexer 202. When the select signal is high (eg, logic 1), each multiplexer 202 outputs a signal to the “1” input of multiplexer 202.

  Communication link 103A (clock A) is connected to the clock inputs of flip-flops 204A, 204C. Communication link 103B (clock B) is connected to the clock input of flip-flops 204B, 204D, 214. The outputs of flip-flops 204A-D are connected to “00” input, “01” input, “11” input, and “10” input of multiplexer 206 via communication links 205A-D, respectively. The multiplexer 206 receives a 2-bit selection signal from the state machine 212 via the communication links 211A and 211B. Multiplexer 206 outputs a signal to the “00” input of multiplexer 206 when both bits of the select signal are low (ie, logic 0). When both two bits of the select signal are high (ie, logic 1), multiplexer 206 outputs the signal to the “11” input of multiplexer 206. When the first bit of the selection signal is low and the second bit is high, the multiplexer 206 outputs a signal to the “01” input of the multiplexer 206. When the first bit of the selection signal is high and the second bit is low, the multiplexer 206 outputs a signal to the “10” input of the multiplexer 206.

  The output of multiplexer 206 is connected to the “0” input of multiplexer 208 via communication link 207A. The “1” input of multiplexer 208 is connected to the “/ V /” signal via communication link 207B. This “/ V /” signal is an error code in the 8B10B protocol. The multiplexer 208 receives the selection signal from the state machine 212 via the communication link 211C. When the select signal is low (eg, logic 0), multiplexer 208 outputs a signal to the “0” input of multiplexer 208. When the select signal is high (eg, logic 1), multiplexer 208 outputs a signal to the “1” input of multiplexer 208.

  The output of multiplexer 208 is connected to the data input of flip-flop 210 via communication link 209. Communication link 103D (clock C) is connected to the clock inputs of flip-flops 210 and 216 and is further connected to state machine 212. The flip-flop 210 outputs data (data_out) to the system B 106 (FIG. 1) via the communication link 103E.

  The first output (out1) of flip-flop 214 is connected to the input of flip-flop 216 via communication link 215A. The second output (out2) of the flip-flop 214 is an inverted output and is connected to the input of the flip-flop 214. The flip-flop 214 supplies the synchronization pulse to the flip-flop 216 via the communication link 215A. The output of flip-flop 216 is connected to state machine 212 via communication link 217. The flip-flop 216 supplies the synchronization pulse to the state machine 212 via the communication link 217. When a signal is supplied from the flip-flop 216 to the state machine 212, the state machine 212 transitions between various states. This will be described in detail later with reference to FIG.

  As shown in FIG. 2, flip-flops 204A and 204C are clocked by a clock signal A received via communication link 103A. Therefore, these flip-flops belong to the clock domain of clock A. Flip-flops 204B, 204D, and 214 are clocked by a clock signal B that is received via communication link 103B. Therefore, these flip-flops belong to the clock domain of clock B. The flip-flop 210, state machine 212, and flip-flop 216 are clocked by a clock signal C received via the communication link 103D. Therefore, they belong to the clock domain of clock C. Next, the operation of the synchronization device 104 will be described in detail with reference to FIGS.

  As will be appreciated by those skilled in the art, the logic circuit shown in FIG. 2 is replicated multiple times depending on the number of data bits that the synchronizer 104 processes per clock cycle. For example, in an embodiment where the synchronizer 104 processes 10 bits of data per clock cycle, the multiplexers 202A-D, flip-flops 204A-D, multiplexers 206, 208, and flip-flop 210 are each preferably replicated 10 times. . In one embodiment, when the integer corresponding to the number of data bits that the synchronizer 104 processes per clock cycle is “N”, the synchronizer 104 includes N multiplexers 202A-D (4N total). , N flip-flops 204A to 204D (4N in total), N multiplexers 206, N multiplexers 208, and N flip-flops 210.

  FIG. 3 is a state diagram illustrating various states of the state machine 212 of the synchronizer shown in FIG. 2 according to one embodiment of the invention. As shown in FIG. 3, the state machine 212 has eight states 302-316. A three-bit value is associated with each of the eight states 302-316. For example, the 3-bit value associated with state 302 is “000”. The least significant 2 bits (2 bits at the right end) of each 3-bit state value correspond to a signal that the state machine 212 outputs to the multiplexer 206 via the communication links 211A and 211B. The flip-flop 216 outputs a transition variable (“1” or “0”) that determines the transition between the states 302 to 316 to the communication link 217.

  In one embodiment, state machine 212 begins at state 306, which is a reset / error state. The 3-bit value corresponding to the state 306 is “100”. In state 306, state machine 212 outputs a “1” selection signal to multiplexer 208 via communication link 211C and a “00” selection signal to multiplexer 206 via communication links 211A and 211B. While the signal that flip-flop 216 outputs to communication link 217 is low (ie, logic 0), state machine 212 remains in its state 306. When the signal output by flip-flop 216 to state machine 212 goes high (ie, logic 1), state machine 212 transitions from state 306 to state 310.

  The 3-bit value corresponding to the state 310 is “011”. In state 310, state machine 212 outputs a “0” selection signal to multiplexer 208 via communication link 211C and a “11” selection signal to multiplexer 206 via communication links 211A and 211B. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 is logic 1 in state 310, the state machine 212 transitions from state 310 to state 312. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in state 310 is a logic zero, the state machine 212 transitions from state 310 to state 316.

  The 3-bit value corresponding to the state 312 is “010”. In state 312, state machine 212 outputs a “0” selection signal to multiplexer 208 via communication link 211C and a “10” selection signal to multiplexer 206 via communication links 211A and 211B. If the signal that flip-flop 216 outputs to state machine 212 over communication link 217 in state 312 is a logic 1, state machine 212 transitions from state 312 to state 314. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in state 312 is a logic zero, the state machine 212 transitions from state 312 to state 302.

  The 3-bit value corresponding to the state 314 is “111”. State 314 is an error condition. In state 314, the state machine 212 outputs a “1” selection signal to the multiplexer 208 via the communication link 211C and outputs an “11” selection signal to the multiplexer 206 via the communication links 211A and 211B. State machine 212 remains in state 314 while the signal that flip-flop 216 outputs to state machine 212 over communication link 217 is a logic one. When the signal that flip-flop 216 outputs to state machine 212 over communication link 217 in state 314 changes to logic zero, state machine 212 transitions from state 314 to state 302.

  The 3-bit value corresponding to state 316 is “110”. In state 316, state machine 212 outputs a “0” selection signal to multiplexer 208 via communication link 211C and a “10” selection signal to multiplexer 206 via communication links 211A and 211B. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in the state 316 is logic, the state machine 212 transitions from the state 316 to the state 314. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in state 316 is a logic zero, the state machine 212 transitions from state 316 to state 302.

  The 3-bit value corresponding to the state 302 is “000”. In the state 302, the state machine 212 outputs a “0” selection signal to the multiplexer 208 via the communication link 211C and outputs a “00” selection signal to the multiplexer 206 via the communication links 211A and 211B. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in the state 302 is logic 1, the state machine 212 transitions from the state 302 to the state 308. If the signal output by flip-flop 216 to state machine 212 via communication link 217 in state 302 is a logic zero, state machine 212 transitions from state 302 to state 304.

  The 3-bit value corresponding to the state 304 is “001”. In state 304, state machine 212 outputs a “0” selection signal to multiplexer 208 via communication link 211C and a “01” selection signal to multiplexer 206 via communication links 211A and 211B. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in the state 304 is logic 1, the state machine 212 transitions from the state 304 to the state 310. If the signal output by the flip-flop 216 to the state machine 212 via the communication link 217 in state 304 is a logic zero, the state machine 212 transitions from state 304 to state 306.

  The 3-bit value corresponding to the state 308 is “101”. In state 308, state machine 212 outputs a “0” selection signal to multiplexer 208 via communication link 211C and a “01” selection signal to multiplexer 206 via communication links 211A and 211B. If the signal that flip-flop 216 outputs to state machine 212 over communication link 217 in state 308 is a logic 1, state machine 212 transitions from state 308 to state 310. If the signal that flip-flop 216 outputs to state machine 212 over communication link 217 in state 308 is a logic zero, state machine 212 transitions from state 308 to state 306.

  FIG. 4 is a diagram illustrating the timing of various signals of the synchronizer 104 shown in FIG. 2 according to one embodiment of the present invention. Clock signal A (402) represents the clock signal output by system A (102) (FIG. 1) to synchronizer 104 via communication link 103A. A clock signal B (404) represents a clock signal output from the system A (102) to the synchronization device 104 via the communication link 103B. A Data_in signal 406 represents a data signal output from the system A 102 to the synchronization device 104 via the communication link 103C. In one embodiment, each time the clock signals 402 and 404 transition, a new data word is input to the synchronizer 104 according to the clock via the communication link 103C. In signal 406, the individual data words are identified by numbers 1, 2, 3,. In one embodiment, each data word in signal 406 is a 10-bit value. Synchronization signal 408 represents the synchronization signal output by flip-flop 214 (FIG. 2) to communication link 215A. As shown in FIG. 4, the synchronization signal 408 includes a plurality of pulses, the width of each pulse being equal to the width of one clock cycle of the clock signal 402 or 404, and the interval between pulses being one clock cycle. In one embodiment, the synchronization signal 408 output by the flip-flop 214 is an index value encoded with a Gray code to give an instruction to the state machine 212, and the flip-flop 216 indicates that the unstable signal is a state machine. It has a function of preventing input to 212.

  Signal 410 shows the data word in signal 406 that flip-flop 204A (FIG. 2) outputs to the “00” input of multiplexer 206 via communication link 205A. As shown in FIG. 4, the flip-flop 204A outputs data words corresponding to the numbers 3, 7, and 11 in the signal 406. Signal 412 shows the data word in signal 406 output by flip-flop 204B (FIG. 2) to “01” input of multiplexer 206 via communication link 205B. As shown in FIG. 4, flip-flop 204B outputs data words corresponding to numbers 4, 8, and 12 in signal 406. Signal 414 shows the data word in signal 406 output by flip-flop 204C (FIG. 2) to the “11” input of multiplexer 206 via communication link 205C. As shown in FIG. 4, the flip-flop 204 </ b> C outputs data words corresponding to numbers 1, 5, 9, and 13 in the signal 406. Signal 416 shows the data word in signal 406 output by flip-flop 204D (FIG. 2) to “10” input of multiplexer 206 via communication link 205D. As shown in FIG. 4, flip-flop 204D outputs a data word corresponding to numbers 2, 6, 10, 14 in signal 406.

  After sampling each data word from the data_in signal 406, as shown by signals 410-416 in FIG. 4, the data word is one of the flip-flops 204A-D for the duration of two clock cycles of the clock signal 402 or 404. Are held in one output. Thus, each data word substantially occupies a time frame of two clock cycles. However, since the two clock cycle time frames are divided at the clock boundaries, in one embodiment, the synchronizer 104 is configured to process jitter for up to one entire clock cycle.

  The operation of the synchronizer 104 is not only affected by the clock signal C output by the system B 106 (FIG. 1) to the synchronizer 104 via the communication link 103D, but also between the clock signal C and the clock signals 402, 404. Also affected by relationships. Signals 418A-424A illustrate a first example of the operation of the synchronizer 104. In this example, the clock signal C starts in synchronization with the clock signal 402 and the clock signal 404 and flows to the right and then to the left. Signals 418B-424B illustrate a second example of the operation of the synchronizer 104. In this example, the clock signal C starts later than the clock signal 402 and the clock signal 404, flows to the left, and then flows to the right.

  A clock signal C (418A) indicates a clock signal output from the system B 106 (FIG. 1) to the synchronization device 104 via the communication link 103D. As shown in FIG. 4, the clock signal C (418A) starts in synchronization with the clock signal 402 and the clock signal 404, flows to the right, and then flows to the left. A gray synchronization (Gray_sync) signal 420 </ b> A indicates a synchronization signal output from the flip-flop 216 to the state machine 212 via the communication link 217. As shown in FIG. 4, the synchronization signal 420A includes a plurality of pulses having different widths, and the interval between the pulses also varies. The fluctuation of the pulse width and interval is caused by the drift (fluctuation) of the clock signal C (418A). The state signal 422A indicates the state of the state machine 212 over time. Each state is identified by a 3 bit value corresponding to that state. A Data_out signal 424A indicates a data signal output from the synchronization device 104 to the system B 106 via the communication link 103E. As shown in FIG. 4, the data_out signal 424 A has the same data word as the data_in signal 406. As can be seen by comparing the data_out signal 424A with the signals 410-416, each data word of the data_out signal 424A fits in the time frame for two clock cycles corresponding to that data word indicated in the signals 410-416. ing.

  As indicated by signal 422A, state machine 212 starts at state “100”. State “100” is a reset state and state machine 212 remains in this state for several clock cycles before transitioning to state “011”. In state “100”, state machine 212 causes multiplexer 208 (FIG. 2) to output a value from the “1” input of multiplexer 208. This value is an error code. The multiplexer 208 outputs the error code to the flip-flop 210, and the flip-flop 210 outputs the error code to the communication link 103E when the clock signal C (418A) next transitions from low to high.

  In state “011”, state machine 212 causes multiplexer 208 to output a value from the “0” input of multiplexer 208. The “0” input of multiplexer 208 is connected to the output of multiplexer 206. The least significant 2 bits of the state “011” are “11”. Accordingly, the state machine 212 causes the multiplexer 206 to output a value from the “11” input of the multiplexer 206. The “11” input of the multiplexer 206 is connected to the output of the flip-flop 204C. As indicated by signal 414, the value held at the output of flip-flop 204 </ b> C during state “011” is data word number 1. Therefore, the multiplexer 206 outputs the data word number 1 to the input of the flip-flop 210 via the multiplexer 208. Then, the flip-flop 210 outputs the data word number 1 to the communication link 103E when the clock signal C (418A) next transitions from low to high.

  After the state “011”, the state machine 212 successively transitions to another state (“010”, “000”, “001”,..., “010”) as indicated by a signal 422A. The least significant 2 bits of the 3-bit state value correspond to one of the flip-flops 204A-D. As shown in signal 422A, the least significant 2 bits of these states form a pattern of 11, 10, 00, 01, which is repeated continuously. That is, the state machine 212 causes the multiplexer 206 to select the output from the flip-flop 204C in the state “011”, and then sequentially outputs the output from the flip-flop 204D, the output from the flip-flop 204A, and the output from the flip-flop 204B. Causes the multiplexer 206 to select. The selection then returns to the output from flip-flop 204C and the process is repeated. Each time multiplexer 206 selects one of flip-flops 204A-D, the data word held at the output of the selected flip-flop 204 is output to the input of flip-flop 210 via multiplexers 206 and 208. Is done. The flip-flop 210 outputs the data word to the communication link 103E when the clock signal C (418A) next transitions from low to high.

  Signals 418B-424B illustrate a second example of the operation of the synchronizer 104. A clock signal C (418B) indicates a clock signal that the system B 106 (FIG. 1) outputs to the synchronization device 104 via the communication link 103D. As shown in FIG. 4, the clock signal C (418B) is delayed from the clock signal 402 and the clock signal 404 and flows to the left and then to the right. A Gray_sync (gray synchronization) signal 420B indicates a synchronization signal that the flip-flop 216 outputs to the state machine 212 via the communication link 217. As shown in FIG. 4, the signal 420B includes a plurality of different pulses, and the interval between the pulses also varies. The fluctuation of the pulse width and interval is caused by the drift of the clock signal C (418B). The state signal 422B indicates the state of the state machine 212 over time. Each state is identified by a 3 bit value corresponding to that state. The data_out signal 424B indicates a data signal output from the synchronization device 104 to the system B 106 via the communication link 103E. As shown in FIG. 4, the data_out signal 424 </ b> B has the same data word as the data_in signal 406. However, an error code is inserted between the data word identified by number 6 and the data word identified by number 7. This is due to the drift of the clock signal C (418B). As can be seen by comparing the data_out signal 424B with the signals 410-416, each data word of the data_out signal 424B fits in the time frame for two clock cycles corresponding to that data word indicated in the signals 410-416. ing.

  Regarding the signals 418B to 424B, the state machine 212 selects the output from the flip-flop 204C, the output from the flip-flop 204D, the output from the flip-flop 204A, and the output from the flip-flop 204B to the multiplexer 206 in order in a repeating pattern. Let This method is the same as described above for signals 418A-424A. However, as indicated by signal 422B, while flip-flop 210 is outputting data word number 6 (obtained from flip-flop 204D), state machine 212 is in state "111". This state is an error state. In state “111”, state machine 212 causes multiplexer 208 to output a value at the “1” input of multiplexer 208. This value is an error code. This error code is output from the multiplexer 208 to the flip-flop 210. Then, the flip-flop 210 outputs the error code to the communication link 103E when the clock signal C (418B) next transitions from low to high. As shown in signal 422B, the next state after state “111” is state “000”, which corresponds to flip-flop 204A. That is, after inserting the error code into the data stream, the flip-flop 210 outputs the data word number 7 from the flip-flop 204A to the communication link 103E. Then, the state machine 212 continues to select the flip-flops 204A to 204D based on this repeating pattern.

  According to an embodiment of the present invention, a synchronization device 104 is obtained that is more efficient (eg, in terms of the number of gates) and has a waiting time as short as possible compared to a conventional synchronization device. In one embodiment, the synchronizer 104 can withstand high frequency jitter in the clock for up to one clock period. In one embodiment of the present invention, the synchronization device 104 has an error detection function for ensuring the reliability of data transmitted by the synchronization device. In one embodiment, the synchronizer 104 may detect from a FIFO overflow or underflow condition that may occur when the conditions for the synchronizer 104 to operate correctly (as described above in connection with FIG. 1) are violated. Built-in recovery function. In one embodiment, the synchronizer 104 may be configured for use in Ethernet applications, memory applications, and other applications. The synchronization device 104 according to an embodiment of the present invention has a number of applications in an input / output (I / O) front end. The clock is usually supplied from a data source (source synchronization), and the receiver has a clock derived from the source clock and undergoes an unknown magnitude phase shift. There are various industry standards such as PCIx 2.0 (DDR PCIx), Fiber Channel, and Gigabit Ethernet.

  While the specification describes and describes particular embodiments, those skilled in the art will recognize that various alternative embodiments and / or equivalents may be substituted for the specific embodiments shown and described without departing from the scope of the invention. Embodiments can also be adopted. This application is intended to cover all modifications and variations of the specific embodiments described herein within the scope of the invention. The scope of the invention is defined only by the claims and their equivalents.

It is a block diagram which shows the communication system by one Embodiment of this invention. 1 is a schematic diagram illustrating a synchronization device according to an embodiment of the present invention. FIG. 3 is a state diagram illustrating various states of the state machine of the synchronizer shown in FIG. 2 according to an embodiment of the present invention. FIG. 3 is a timing diagram illustrating various signals of the synchronizer shown in FIG. 2 according to an embodiment of the present invention.

Explanation of symbols

100 Communication system 102, 106 System 103, 207, 211, 215, 217 Communication link 104 Synchronizer 202, 206, 208 Multiplexer 204, 210, 214, 216 Flip flop 212 State machine 402, 404 Clock signal 406 Data_in signal 408 Synchronization signal

Claims (10)

A second system (106) that receives data based on a third clock (103D) from a first system (102) that transmits data based on a first clock (103A) and a second clock (103B). A synchronization device (104) for passing data to
A first set of flip-flops (204A, 204C) for receiving data from the first system based on the first clock;
A second set (204B, 204D) of flip-flops that receive data from the first system based on the second clock;
A first multiplexer (206) connected to the outputs of flip-flops in the first set and the second set;
Output data supplied to the second system by controlling the first multiplexer (206) based on the third clock and outputting data from a selected flip-flop of the flip-flops And a control device (212) for generating (103E). When the integer corresponding to the number of data bits processed by the synchronizer per clock cycle is N,
The first set of flip-flops (204A, 204C) is 2N flip-flops configured to be clocked by the first clock;
The synchronization device according to claim 1, wherein the second set of flip-flops (204B, 204D) is 2N flip-flops configured to be clocked by the second clock.   The synchronizer has a data input for receiving data from the first system, and the synchronizer further includes a first plurality of multiplexers (202A-202D), each of the first plurality of multiplexers. A first input connected to the data input; an output connected to one input of the flip-flop; and a second input connected to an output of one of the flip-flops. The synchronization device according to claim 1.   A first control signal generator (214) for generating a first set of control signals for controlling the first plurality of multiplexers (202A-202D) based on the second clock signal; 4. The synchronizer of claim 3, further comprising a second control signal generator (216) that generates a second set of control signals based on the first set and the third clock signal.   The control device controls the first multiplexer based on the third clock signal and the second set of control signals, and outputs data from a selected flip-flop of the flip-flops. 5. A synchronization device according to claim 4, configured.   The synchronization device of claim 1, wherein the controller is configured to identify whether an error has occurred when passing data from the first system to the second system.   The synchronization device according to claim 6, wherein the control device is configured to insert an error code into data to be passed to the second system when an occurrence of an error is identified.   The synchronization device according to claim 1, wherein the first clock and the second clock operate at a first frequency, and the third clock operates at a frequency twice as high as the first frequency.   9. The phase of the first clock and the second clock is 180 degrees different, and the third clock is derived from at least one of the first clock and the second clock. Synchronization device. Data from the first system (102) that transmits data based on the first clock (103A) and the second clock (103B) to the second system that receives data based on the third clock (103D) A method of passing
Data is input from the first system to the first plurality of flip-flops (204A, 204C) based on the first clock, and from the first system to the second plurality of flip-flops based on the second clock. Putting data into flip-flops (204B, 204D)
Outputting data from a flip-flop in the first plurality of flip-flops and the second plurality of flip-flops to a first multiplexer (206);
Based on the third clock, the first multiplexer is controlled to output data from a selected flip-flop of the flip-flops, thereby generating output data to be supplied to the second system. A method consisting of and steps.

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