JP5690374B2 - Clock synchronizer - Google Patents

Description

  The present invention relates to a clock synchronization apparatus.

  Conventionally, a clock synchronization method for performing time synchronization between devices connected by communication means such as the Internet has been proposed (see, for example, Non-Patent Document 1).

  The clock synchronization method described in Non-Patent Document 1 uses NTP (Network Time Protocol) defined in RFC1305, which is an Internet communication standard, to transmit time information from a master device that is a synchronization subject to a slave device subordinate to the master device. The slave device adds the received time and the time to send the time information to the master device again to the master device, and sends the master device to the time information. The propagation delay time between the devices is calculated based on the described time, and the time synchronization of the slave device is corrected based on the calculated propagation delay time.

  However, the conventional clock synchronization method described in this non-patent document is based on the assumption that the propagation delay time is the same in the forward path in which time information is transmitted from the master apparatus to the slave apparatus and in the reverse path. However, when there is a difference in the propagation delay time between the propagation delay time of the forward path and the backward path due to a collision of time information packets in the forward path and the backward path, the accuracy of time synchronization is reduced or an offset occurs.

  As a means for solving the above problem, a clock synchronization apparatus has been proposed (for example, see Patent Document 1).

  When transmitting time information from a master device to a slave device, the clock synchronizer described in Patent Literature 1 causes dispersion in the transmission timing by giving a delay to the transmission cycle. The time synchronization of the slave device is corrected based on the time information at a timing at which the collision is reduced and the propagation delay time is reduced.

Japanese Patent No. 4542027

Network Time Protocol (Version3) Specification, Implementation and Analysis, David L. Mills, IETF RFC-1305

  However, the conventional clock synchronizer described in Patent Document 1 improves the accuracy of time synchronization, but does not eliminate variations in the propagation delay time. From a microscopic viewpoint, it fluctuates with the clock frequency of the slave device. There is a problem that occurs.

  Therefore, an object of the present invention is to provide a clock synchronization device that improves the accuracy of clock frequency synchronization between devices connected by communication means, compared to the case where this configuration is not used.

  In order to achieve the above object, one aspect of the present invention provides the following clock synchronization apparatus.

[ 1 ] A synchronization packet transmitted from the master device is received at a transmission interval determined based on the clock signal of the clock source, the arrival times of the received plurality of synchronization packets are recorded, and the difference between the recorded arrival times is initialized. Is a first filter with a slow decay slope and a short convergence time, and after the initial stage, it is averaged with a second filter with a steep slope and a long convergence time compared to the first filter, and the difference between the arrival times A synchronous packet receiver that generates a clock signal based on the average of
A clock synchronization apparatus comprising: an output unit that outputs a synchronization clock based on a clock signal generated by the synchronization packet reception unit;

[ 2 ] A synchronization packet transmitter that generates a synchronization packet, determines a transmission interval based on a clock signal, and transmits the synchronization packet to the slave device at the transmission interval;
The synchronization packet is received after the synchronization packet receiving unit generates a clock signal and the synchronization packet received from the master device is not normal or the synchronization packet does not arrive at the transmission interval from the master device. The clock synchronization apparatus according to [ 1 ], further including a control unit that operates the synchronization packet transmission unit based on a clock signal generated by the reception unit.

[ 3 ] A synchronization packet transmitter that generates a synchronization packet, determines a transmission interval based on a clock signal of a clock source, and transmits the synchronization packet to the slave device at the transmission interval;
Before the synchronization packet receiving unit generates a clock signal, if the synchronization packet received from the master device is not normal, or if the synchronization packet does not arrive at the transmission interval from the master device, the synchronization packet The clock synchronization apparatus according to [ 2 ], further including a control unit that stops the operation of the reception unit and operates the synchronization packet transmission unit.

[4] wherein, if it is communicatively connected to a plurality of clock synchronization device, based on the priority defined between the plurality of clock synchronizer, said operating [2] or [ 3 ] The clock synchronizer according to.

According to the invention of claim 1 can be improved as compared with the case without the present arrangement, the synchronization accuracy of the clock frequency in between devices connected by a communication means.

According to the second or third aspect of the invention, when the synchronization packet received from the master device is not normal or when the synchronization packet does not arrive at the transmission interval from the master device, the slave device can operate as the master device. .

According to the fourth aspect of the present invention, the slave device can operate as the master device based on the priority order.

FIG. 1 is a schematic diagram showing an example of a connection configuration of a clock synchronization apparatus according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing an example of the configuration of the clock synchronization apparatus according to the embodiment of the present invention. FIG. 3 is a diagram for explaining the generation operation of the differential data value of the clock synchronization device as the slave device. FIG. 4 is a graph showing an example of the synchronous clock signal output from the clock synchronizer operating as the master device and the synchronous clock signal output from the clock synchronizer operating as the slave device.

[Embodiment]
(Connection configuration of clock synchronizer)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram showing an example of a connection configuration of a clock synchronization apparatus according to an embodiment of the present invention.

The clock synchronizers 1m, 1s ₁ -1s ₇ are respectively connected via the network 3, and the clock synchronizer 1m becomes a synchronization subject (hereinafter referred to as “master device”), and the clock synchronizer 1s ₁ -1s ₇ It is subordinate to the master device (hereinafter referred to as “slave device”).

Clock synchronizer 1m generates a synchronous clock signal S _c based on the clock signal of the clock source 2, and outputs to an external device (not shown). The clock synchronization device 1m uses an internal clock source may generate a synchronizing clock signal S _c based on the clock signal of the internal clock source.

The clock synchronization device 1m generates a synchronization packet, determines a transmission interval using the clock signal of the clock source 2 or the clock signal of the internal clock source, and transmits the synchronization packet to the clock synchronization device 1s at the determined transmission interval. ₁ -1s ₇ periodically. The synchronization packet is generated in the clock synchronization apparatus 1 in a format defined in RFC2030.

The clock synchronizer 1s ₁ -1s ₇ receives the synchronization packet from the clock synchronizer 1m, which is the master device, and records the arrival time. Clock synchronizer 1s ₁ -1s ₇ is averaged over a plurality of the difference of the arrival time of the synchronization packet is calculated and the synchronous clock frequency that follows the synchronous clock signal S _c of the clock synchronization system 1m based on the calculated difference A signal _Sc is generated and output to an external device (not shown).

In addition, when one of the clock synchronization devices 1s _{1 to} 1s ₇ that are slave devices has an abnormality in the clock synchronization device 1m that is a master device, _{one of} them becomes a master device instead. It is assumed that which slave device becomes the master device is determined based on a predetermined priority. The priority is stored as priority information on a memory (not shown).

Synchronizing clock signal S _c is the clock synchronizer 1 m, is output to an external device (not shown) connected to 1s ₁ -1s _7, is utilized by the external device.

(Configuration of clock synchronizer)
FIG. 2 is a schematic diagram showing an example of the configuration of the clock synchronization apparatus according to the embodiment of the present invention. Note that the clock synchronization device 1m, 1s ₁ -1s ₇ have a common configuration, and will be described as a representative of the clock synchronization device 1.

  The clock synchronization device 1 includes a multiplier 10, a packet reception processing unit 11, a synchronous packet control unit 12, and a frequency divider 13.

  The multiplier 10 generates a 20 MHz clock signal from the 10 MHz clock signal input from the external clock source 2.

Packet reception processing unit 11 includes a clock synchronization device 1 receives the synchronization packet P _s from the other clock synchronization device 1 is the master device when the slave device.

The synchronization packet control unit 12 generates and transmits a synchronization packet when it becomes a master device, and generates a synchronization clock signal by receiving a synchronization packet when it becomes a slave device. a master / slave control unit 120 for controlling happens if the slave device, a synchronization packet transmitting part 121 for transmitting a synchronization packet if the master device, the synchronization for receiving the synchronization packet P _s when the slave device It has a packet receiver 122 and a clock selector 123 that selects which synchronization clock signal of the synchronization packet transmitter 121 or the synchronization packet receiver 122 is used.

The frequency divider 13 is for function as an output unit for outputting a synchronizing clock signal S _c, the clock signal of 20MHz from the synchronization packet control unit 12 is input, it generates a synchronous clock signal S _c of 10MHz Output to the outside.

  The synchronization packet transmission unit 121 includes an OCXO (Oven Controlled Xtal Oscillator) 121a, a clock selector unit 121b, a multiplier 121c, a time counter unit 121d, a counter selector unit 121e, and a synchronization packet generation unit 121f.

  The OCXO 121a is a thermostatic crystal oscillator and outputs a 20 MHz clock signal.

  The clock selector 121b selects a clock signal from either the external clock source 2 or the OCXO 121a.

  The multiplier 121c generates a 100 MHz clock signal from the 20 MHz clock signal.

  The time counter unit 121d is a 64-bit value counter, and operates by a 100 MHz clock signal input from the multiplier 121c to count the time.

  The counter selector unit 121e selects which time counter of the time counter unit 121d or the time counter unit 122k described later is to be used.

Synchronization packet generation unit 121f is configured to generate a synchronization packet _{P s,} with reference to the time counter of the time counter section 121d or the time counter section 122k which is selected by the counter selector unit 121e, the transmission interval is 10msec, every 10msec sending synchronization packets P _s to the slave device.

  The sync packet receiving unit 122 includes a sync packet analyzing unit 122a, an arrival time recording unit 122b, a delay adding unit 122c, an arrival time difference calculating unit 122d, a digital filter 1 unit 122e, a digital filter 2 unit 122f, and a PID. (Proportional Integral Derivative) control unit 122g, D / A converter unit 122h, TCXO (Temperature Compensated Crystal Oscillator) 122i, multiplier 122j, and time counter unit 122k.

Synchronization packet analysis unit 122a analyzes the normality of the clock synchronization system 1 operating as a normality and the master device of the synchronization packet P _s of packet reception processing unit 11 has received.

Arrival time recording unit 122b, when the synchronous packet P _s is judged to be normal by the synchronization packet analysis unit 122a, by referring to the time counter unit 122k to record the arrival time of the synchronization packet P _s. Incidentally, the synchronization packet _{P s} would be sent from the slave device for each 10 msec, time of arrival is recorded for approximately every 10 msec.

  The delay adding unit 122c delays the arrival time recorded by the arrival time recording unit 122b by 1 sec.

  The arrival time difference calculation unit 122d compares the current arrival time recorded by the arrival time recording unit 122b with the arrival time delayed by 1 sec by the delay adding unit 122c and generates a difference data value. The generated difference data value is a value obtained by counting 1 sec at 100 MHz.

  The digital filter 1 unit 122e is a filter having a slow attenuation slope and a short convergence time, and averages the difference data values every 100 pieces.

  The digital filter 2 unit 122f is a filter having a steep attenuation slope and a long convergence time, and averages every 100 differential data values.

PID control unit 122g, the approximately 1sec after receiving the first synchronization packet _{P s} on the basis of the output of the digital filter part 122e, about 1sec elapses after receiving the first synchronization packet _{P s} digital filter 2 Based on the output of the unit 122f, the TCXO 122i is controlled via the D / A converter unit 122h so that the difference data becomes 1 sec, that is, 100000000 counts at 100 MHz.

  The D / A converter unit 122h converts the digital signal output from the PID control unit 122g into an analog signal input to the TCXO 122i.

  The TCXO 122i generates a 20 MHz clock signal under the control of the PID control unit 122g.

  The multiplier 122j generates a 100 MHz clock signal from the 20 MHz clock signal output from the TCXO 122i.

  The time counter unit 122k counts the time based on the 100 MHz clock signal.

(Operation)
Hereinafter, the operation of the clock synchronization device 1 will be described with reference to each drawing, divided into (1) operation as a master device, (2) operation as a slave device, and (3) switching operation from the slave device to the master device. To do.

(1) Operation as a Master Device First, the master / slave control unit 120 controls each unit to become a master device, stops the operation of the packet reception processing unit 11 and the synchronous packet reception unit 122, and sets the counter selector unit 121e. The time counter unit 121d is selected for reference, and the clock selector unit 123 is selected to use the clock signal output from the clock selector unit 121b.

  Next, the clock selector 121b selects which clock signal from the external clock source 2 or the OCXO 121a is to be used.

  Next, when the external clock source 2 is used, the multiplier 10 generates a 20 MHz clock signal from the 10 MHz clock signal input from the external clock source 2.

  Further, when the OCXO 121a which is an internal clock source is used, a 20 MHz clock signal output from the OCXO 121a is used.

  Next, the multiplier 121c generates a 100 MHz clock signal from the 20 MHz clock signal.

  Next, the time counter unit 121d operates by a 100 MHz clock signal input from the multiplier 121c and counts the time.

Next, the synchronization packet generating unit 121f is configured to generate a synchronization packet _{P s,} with reference to the time counter of the time counter unit 121d, and transmits synchronization packets _{P s} to the slave device in each 10 msec.

The clock signal of 20MHz outputted from the clock selector 121b is input via the clock selector 123 to the divider 13, the frequency divider 13 is synchronized clock signal _{S c} from a clock signal of 10 MHz 20MHz Generate and output.

(2) Operation as a Slave Device First, the master / slave control unit 120 controls each unit to become a slave device, stops the operation of the multiplier 10 and the synchronization packet transmission unit 121, and sends the clock selector unit 123 from the TCXO 122i. The output clock signal is selected to be used.

  First, the TCXO 122i generates a 20 MHz clock signal.

  Next, the multiplier 122j generates a 100 MHz clock signal from the 20 MHz clock signal output from the TCXO 122i.

The synchronous packet receiving unit 122 receives a synchronization packet P _s from the master device.

Next, the synchronization packet analysis unit 122a analyzes the normality of the clock synchronization system 1 operating as a normality and the master device of the synchronization packet P _s of packet reception processing unit 11 has received.

  FIG. 3 is a diagram for explaining the generation operation of the differential data value of the clock synchronization device as the slave device.

Next, when the synchronization packet analysis unit 122a determines that the synchronization packet P _s is normal, the arrival time recording unit 122b refers to the time counter unit 122k and arrives at the arrival time t ₁ , t of the synchronization packet P _s. Record ₂ , t ₃ ... Since the sync packet _{P s} is sent from the slave device in each 10msec, arrival time recording unit 122b records the arrival time approximately every 10msec.

Next, the delay adding unit 122c delays the arrival time recorded by the arrival time recording unit 122b by 1 sec. The arrival time of 1sec was delayed and _{t 1.}

Arrival time difference computing unit 122d the current arrival time the arrival time recording unit 122b has recorded _{t i} and is compared with the arrival time _{t 1} that is allowed to 1sec delayed by the delay adding section 122c difference data value _t d1 = t _i −t ₁ is generated. Difference data values are sequentially generated as t _d2 , t _d3 , t _d4 .

About 1 sec after receiving the first synchronization packet P _s , the digital filter 1 unit 122e and after about 1 sec from receiving the first synchronization packet P _s , the digital filter 2 unit 122f receives the difference data value. t _d1 , t _d2 , t _d3 , t _d4 ... are averaged every 100 to generate an average difference data value t _dm .

Next, the PID control unit 122g passes through the D / A converter unit _122h based on the difference data t _dm1 output from the digital filter 1 unit 122e or the difference data t _dm2 output from the digital filter 2 unit 122f. The TCXO 122i is controlled so that the difference data t _dm1 or t _dm2 becomes 1 sec, that is, the count number of the time counter becomes 100000000 counts at 100 MHz.

  Next, the D / A converter unit 122h converts the digital signal output from the PID control unit 122g into an analog signal input to the TCXO 122i.

  Next, the TCXO 122i corrects the clock signal generation of 20 MHz under the control of the PID control unit 122g.

Next, the clock signal of 20MHz outputted from TCXO122i is input via the clock selector 123 to the divider 13, the divider 13 generates a synchronous clock signal _{S c} of 10MHz clock signal of 20MHz ,Output.

  FIG. 4 is a graph showing an example of the synchronous clock signal output from the clock synchronizer 1m operating as the master device and the synchronous clock signal output from the clock synchronizer 1s operating as the slave device.

Among synchronizing clock signal _{S c,} synchronous clock synchronized clock signal _{S cm} for outputting the clock synchronization device 1m which operates as a master device, when the frequency 10MHz clogging period 100 nsec, the output of the clock synchronizer 1s which operates as a slave device Similarly, the signal _Scs has a frequency of 10 MHz, that is, a period of 100 nsec, and the clock frequency is synchronized.

  Under the conditions described in the embodiment, the clock frequency can be synchronized with an accuracy of 10 MHz ± 1 ppm.

(3) clock synchronization device synchronizing packet analysis unit 122a of the first operating as a switching operation the slave device from the slave device to the master device, clock synchronization which operates as a master device from the synchronous packet P _s of packet reception processing unit 11 receives and analyzing the health of the device 1, if the predetermined time synchronization packet P _s is not received, the master device is determined not to be normal.

  When the synchronization packet analysis unit 122a determines that the master device is not normal, the master / slave control unit 120 of the clock synchronization device 1 refers to priority information (not shown), and if the own device has the highest priority, the slave device An operation for switching from the device to the master device is executed.

  First, the master / slave control unit 120 controls the packet reception processing unit 11 to stop operating.

  Here, when the synchronization of the clock frequency with the master device before it is determined to be not normal is probable, the master / slave control unit 120 stops the operation of the PID control unit 122g and outputs it to the TCXO 122i. The 20 MHz frequency is output, and the clock selector 123 is caused to continue using the clock signal output from the TCXO 122i.

  Further, the master / slave control unit 120 controls the counter selector unit 121e to select the clock signal output from the time counter unit 122k that operates based on the clock signal output from the TCXO 122i, and synchronizes based on the clock signal. The packet generator 121f is operated.

  On the other hand, when the synchronization of the clock frequency with the master device before being determined to be not normal is not probable, the master / slave control unit 120 is externally connected as described in “(1) Operation as a master device”. Each unit of the clock synchronizer 1 is operated based on the clock signal output from the clock source 2 or the internal OCXO 121a.

(Effect of embodiment)
According to the above-described embodiment, the clock synchronization device 1m generates a synchronization packet, determines the transmission interval using the clock signal of the clock source 2 or the clock signal of the internal clock source, and synchronizes at the determined transmission interval. the packet clock synchronization device _1s 1 -1s ₇ transmits periodically, the clock synchronization device _1s 1 -1s ₇ receives a synchronization packet from the master device clock synchronization device 1 m, recording the arrival time, average calculated for a plurality of the difference of the arrival time of the synchronization packet, for generating the synchronization clock signal S _c based on the calculated difference, the frequency that follows the synchronous clock signal S _c which is the master device clock synchronization device 1m to a clock signal generated in clock synchronization device _1s 1 -1s ₂ is a slave device It is possible.

  In addition, when the synchronization packet received from the master device is not normal or when the synchronization packet does not arrive from the master device at the transmission interval, the slave device operates as the master device based on the priority order. Even in this case, the frequency synchronization of the synchronous clock signal can be maintained.

[Other embodiments]
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

₁ , 1 m, 1 s ₁ −1 s ₇ clock synchronizer 2 clock source 3 network 10 multiplier 11 packet reception processing unit 12 synchronous packet control unit 13 frequency divider 120 master / slave control unit 121 synchronous packet transmission unit 121a OCXO
121b Clock selector unit 121c Multiplier 121d Time counter unit 121e Counter selector unit 121f Synchronization packet generation unit 122 Synchronization packet reception unit 122a Synchronization packet analysis unit 122b Arrival time recording unit 122c Delay addition unit 122d Arrival time difference calculation unit 122e Digital filter 1 unit 122f Digital filter 2 part 122g PID control part 122h D / A converter part 122i TCXO
122j multiplier 122k time counter 123 clock selector _{P s} synchronous packet _{S c, S cm, S cs} synchronous clock signals _t 1 -t _i arrival time _{t d1, t d2} difference data value _{t dm} average difference data value _{t dm1,} t _dm2 difference data

Claims (4)

Receives synchronization packets transmitted from the master device at a transmission interval determined based on the clock signal of the clock source, records the arrival times of the received plurality of synchronization packets, and initially sets the difference between the recorded arrival times as an attenuation gradient Is a first filter with a slow convergence time, and is averaged with a second filter having a steep attenuation slope and a long convergence time compared to the first filter after the initial stage to obtain the average difference of the arrival times. A synchronous packet receiver for generating a clock signal based on the
A clock synchronization apparatus comprising: an output unit that outputs a synchronization clock based on a clock signal generated by the synchronization packet reception unit; A synchronization packet generating unit that generates a synchronization packet, determines a transmission interval based on a clock signal, and transmits the synchronization packet to the slave device at the transmission interval;
The synchronization packet is received after the synchronization packet receiving unit generates a clock signal and the synchronization packet received from the master device is not normal or the synchronization packet does not arrive at the transmission interval from the master device. The clock synchronization apparatus according to claim 1 , further comprising: a control unit that operates the synchronization packet transmission unit based on a clock signal generated by the reception unit. A synchronization packet generating unit that generates a synchronization packet, determines a transmission interval based on a clock signal of a clock source, and transmits the synchronization packet to the slave device at the transmission interval;
Before the synchronization packet receiving unit generates a clock signal, if the synchronization packet received from the master device is not normal, or if the synchronization packet does not arrive at the transmission interval from the master device, the synchronization packet The clock synchronization apparatus according to claim 2 , further comprising a control unit that stops the operation of the reception unit and operates the synchronization packet transmission unit. Wherein, if it is communicatively connected to a plurality of clock synchronizer clock according to claim 2 or 3 based on the priority defined between the plurality of clock synchronizer operates Synchronizer.

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