JP5391964B2 - Clock synchronization method and packet communication system - Google Patents

Description

  According to the present invention, a slave clock signal of at least one slave device among a plurality of communication devices that transmit and receive data packets via a packet network such as an IP (Internet Protocol) is transmitted to one master device of the communication devices. The present invention relates to a clock synchronization method for synchronizing with a master clock signal and a packet communication system for performing packet communication by executing the clock synchronization method.

  There are roughly two types of methods for performing clock synchronization between communication devices. The first method is called an adaptive clock regeneration method. In the reception buffer on the slave device side, for example, the buffer retention amount of, for example, video or audio stream data packets is constantly monitored, and the buffer retention amount is always constant. This is a method of controlling the reproduction clock so that For the concept of such method, see ITU-T Recommendation I.D. For example, Patent Document 1 is referred to as an example. The first method has a problem that the synchronization accuracy is lacking because the synchronization between the both is indirectly achieved from the fluctuation of the buffer retention amount without exchanging the clock information between the master device and the slave device. .

  The second method is a method for realizing clock synchronization between communication devices with high accuracy by transferring a packet in which clock data is embedded (hereinafter referred to as a clock packet) to a packet network in addition to a normal data packet. It is. However, some relay devices such as routers and switches exist on the packet network, and packets other than clock packets are transferred on the packet network. Therefore, the clock packet propagation delay time from the master device to the slave device varies. Such fluctuation is called “IP network fluctuation” in the case of an IP network. When clock synchronization is performed in such a situation with fluctuations, a time lag occurs between the arrival time of a clock packet embedded in a certain clock data and the content of the clock data, and the clock frequency The accuracy, jitter, or wander deteriorates, causing a problem that proper clock synchronization cannot be realized.

  In this regard, in the technique disclosed in Patent Document 2, the time of the clock data in the clock packet is set for each relay device in accordance with the length of the packet queue in the relay device such as a router or a switch that is a factor of such fluctuation. A method has been proposed in which the influence of fluctuation is reduced by sequentially correcting.

Japanese Patent No. 3555883 JP 2005-253033 A

  However, in the technique disclosed in Patent Document 2 described above, two special functions of a function for measuring a queue time and a function for editing and updating clock packet data according to the queue time are provided as a router, a switch, or the like. It is necessary to prepare for the relay device. Since these devices are usually sold in a wide variety in the commercial market, it is virtually impossible to request such special functions widely.

  Therefore, an object of the present invention is to accurately detect the influence of the propagation delay time of the clock packet between the communication devices without requiring a special function from a relay device such as a router or a switch on an intermediate path of the packet network. It is to provide a packet communication method and a communication system for achieving clock synchronization.

A clock synchronization method according to the present invention is a clock for synchronizing a slave clock signal of a slave device among a plurality of communication devices that transmit and receive data packets via a packet network with a master clock signal of a master device of the communication devices. In the synchronization method, in the master device, a clock packet transmission step of transmitting a clock packet in which a count value of the master clock signal at the time of transmission is stored to the slave device at a predetermined frequency; and in the slave device, A delay time data acquisition step of acquiring delay time data representing the propagation delay time by measuring a propagation delay time with the master device for each clock packet; and in the slave device, each of the clock packets The corresponding delay time data is accumulated An average value calculating step for calculating an average value of the accumulated delay time data group; and in the slave device, the count value of the clock packet is corrected based on the average value, and the count value of the slave clock signal is corrected by updating the by count value, said saw including a phase control step of controlling the phase of the slave clock signal, wherein the average value calculating step, the delay time data corresponding to each of said clock packet, previously By comparing with the calculated average value, the data within the deviation based on the predetermined deviation threshold and the data outside the deviation are accumulated separately, and the new average value is calculated only from the accumulated data group within the deviation, If data continues for a predetermined number of times per clock packet, a new average value is calculated from only the accumulated non-deviation data group. To wherein there to be.

A packet communication system according to the present invention includes a plurality of communication devices that transmit and receive data packets via a packet network, wherein a slave device of the communication devices receives its own slave clock signal and a master device of the communication devices. A packet communication system for processing the data packet in synchronization with a master clock signal of the master device, wherein the master device sends a clock packet storing a count value of the master clock signal at the time of transmission to the slave device at a predetermined frequency. A delay time for acquiring delay time data representing the propagation delay time by measuring a propagation delay time with the master device for each clock packet. Data acquisition means and a delay corresponding to each of the clock packets; Average value calculation means for storing time data and calculating an average value of the accumulated delay time data group; and in the slave device, correcting the count value of the clock packet based on the average value, and the slave clock signal delay by updating the count value to the corrected count value, said saw including a phase control means for controlling the phase of the slave clock signal, and said average value calculation means corresponding to each of said clock packet Comparing the time data with the previously calculated average value, it accumulates the data within the deviation and the data outside the deviation based on the predetermined deviation threshold, and calculates a new average value only from the accumulated data group within the deviation On the other hand, if the out-of-deviation data continues for a predetermined number of times or more for each clock packet, a new average is generated only from the accumulated out-of-deviation data group. To wherein there may calculate the value.

  According to the clock synchronization method and the packet communication system of the present invention, since the propagation delay time of the clock packet is measured between the master device and the slave device, a relay device such as a router or a switch having a special function is not required. Further, by measuring the propagation delay time, it is possible to avoid the influence of fluctuations related to clock synchronization as much as possible. The correction of the propagation delay time of the clock data does not use the propagation delay time itself, but uses the average value of the propagation delay time, thereby preventing deterioration of jitter and wander and enabling good clock synchronization.

1 is a block diagram showing a packet communication system that executes a clock synchronization method according to the present invention as an embodiment of the present invention; FIG. It is a block diagram which shows the internal structure of the master apparatus shown by FIG. It is a block diagram which shows the internal structure of the slave apparatus shown by FIG. It is a sequence diagram which shows the operation | movement procedure in which a master apparatus and a slave apparatus calculate delay time data in cooperation. It is a flowchart which shows the operation | movement procedure in which a slave apparatus implement | achieves clock synchronization based on the average value of delay time data.

Embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Example of the present invention>
FIG. 1 shows an embodiment of the present invention and shows a packet communication system for executing a clock synchronization method according to the present invention. The packet communication system includes a master device 20 and a slave device 30. The master device 20 and the slave device 30 are connected to each other via a packet network 10 such as an Internet line. There are usually several relay devices (not shown) such as routers and switches on the route in the packet network 10.

  The master device 20 and the slave device 30 normally transmit / receive data packets to / from each other, and at least the master device 20 transmits a clock packet to the slave device 30 to achieve clock synchronization between the two. In the clock packet, clock data that is a count value obtained by counting the pulses of the clock signal is stored as a payload.

  In the present embodiment, the master device 20 and the slave device 30 are described as being configured in a one-to-one relationship, but the present invention is also in a one-to-N relationship (N is a positive number). Applicable. In addition, an embodiment in which the slave device becomes a new master device and clock synchronization is sequentially performed for other different slave devices in a cascade manner is also within the scope of the present invention.

  FIG. 2 shows an internal configuration of the master device 20 shown in FIG. Here, the master device 20 includes a master clock unit 21, a clock information generation unit 22, a clock packet transmission unit 23, and a clock packet reception unit 24.

  The master clock unit 21 generates a master clock signal that is a reference for clock synchronization, and inputs this to the clock information generation unit 22. The clock information generation unit 22 includes a cyclic counter 22a that counts the pulses of the input master clock signal and holds the count value. Further, the clock information generation unit 22 generates clock data representing the count value of the cyclic counter 22 a and inputs this to the clock packet transmission unit 23.

  The clock packet transmission unit 23 generates a first clock packet and a third clock packet that use the generated clock data as a payload, and transmits the first clock packet and the third clock packet to the slave device 30. The clock packet receiving unit 24 receives the second clock packet transmitted from the slave device 30. The second clock packet functions as a response packet from the slave device 30 for the first clock packet. The third clock packet functions as a response packet from the master device 20 with respect to the second clock packet.

  FIG. 3 shows an internal configuration of the slave device 30 shown in FIG. Here, the slave device 30 includes a clock packet reception unit 31, a clock packet transmission unit 32, a propagation delay time calculation unit 33, a deviation confirmation unit 34, a first delay time accumulation unit 35, a second delay time accumulation unit 36, an average value. A calculation unit 37, a clock information correction unit 38, a clock information update unit 39, a slave clock unit 40, and a PLL unit 41 are provided.

  The clock packet receiver 31 receives the first clock packet and the third clock packet transmitted from the master device 20, and extracts clock data (t1 and t4 described later) and arrival time (t2 described later) from these packets. These are input to the propagation delay time calculator 33. The clock packet transmission unit 32 generates a second clock packet as a response packet to the first clock packet, transmits the second clock packet to the master device 20, and inputs the transmission time (t3 described later) to the propagation delay time calculation unit 33. The content of the clock data of the second clock packet is not particularly required and may be empty.

  The propagation delay time calculation unit 33 calculates delay time data from the input clock data, and inputs this to the deviation confirmation unit 34. The deviation confirmation unit 34 compares the input delay time data with an average value, which will be described later, and if the delay time data is within a deviation (X) that is a predetermined threshold, the delay time data is converted into in-deviation data ( ≦ X) and input to the first delay time accumulating unit 35. If it is out of the deviation, the delay time data is input to the second delay time accumulating section 36 as out-of-deviation data (> X). The value of the deviation (X) can be set from the outside in advance.

  Each of the first delay time accumulating unit 35 and the second delay time accumulating unit 36 accumulates input delay time data as a predetermined number of delay time data groups. The number of delay time data can be preset from the outside. The average value calculating unit 37 calculates an average value from the delay time data group read from the first delay time accumulating unit 35 and inputs this to the clock information correcting unit 38 and the deviation checking unit 34 as new average values. . The clock information correction unit 38 generates corrected clock data from the clock data input from the clock packet reception unit 31 and the average value input from the average value calculation unit 37, and inputs this to the clock information update unit 39. .

  The clock information update unit 39 includes a cyclic counter 39a that counts the pulses of the slave clock signal generated by the slave clock unit 40, and in response to the input of the corrected clock data from the clock information correction unit 38, a cyclic counter is added to the corrected clock data. While updating the count value of 39a, PLL phase data for frequency control is generated based on the corrected count value, and this is input to the PLL unit 41. The PLL unit 41 controls the frequency of the slave clock signal generated by the slave clock unit 40 based on the input PLL phase data.

  FIG. 4 shows an operation procedure in which the master device 20 and the slave device 30 cooperate to calculate delay time data. Here, in order to measure the propagation delay time between the master device 20 and the slave device 30, three types of clock packets (first to third clock packets) according to NTP (Network Time Protocol) are transmitted and received. . These three types of clock packets form one set, and the one set is transmitted and received between the master device 20 and the slave device 30 at an intermittent frequency. The frequency can be set to an arbitrary frequency such as a predetermined period. Preferably, a set identifier indicating that it is included in the same set may be stored in each of the first to third clock packets forming one set. Thereby, even when the frequency is high, it is possible to easily identify clock packets between adjacent sets.

  In this figure, time t1 and time t4 are count values of the cyclic counter 22a (see FIG. 2) in the master device 20, and mean count values at the time of transmission or arrival of the clock packet. Time t2 and time t3 are count values of the cyclic counter 39a (see FIG. 3) in the slave device 30, and mean count values at the time of transmission or arrival of the clock packet.

  First, at time t1, the master device 20 generates a first clock packet including clock data representing the transmission time t1, and transmits the first clock packet to the slave device 30. The slave device 30 receives the first clock packet and holds the transmission time t1 and the arrival time t2 of the first clock packet in the first clock packet. Next, the slave device 30 generates a second clock packet and transmits it to the master device 20. At this time, the slave device 30 holds the transmission time t3 of the second clock packet together with the times t1 and t2.

  On the other hand, the master device 20 receives the second clock packet at the arrival time t4. Next, the master device 20 generates a third clock packet including clock data representing the arrival time t <b> 4 and transmits it to the slave device 30. The slave device 30 receives the third clock packet, and holds the time t4 included therein together with the times t1 to t3 described above. As a result of the above operation, the slave device 30 calculates delay time data representing the propagation delay time by applying the held data of t1, t2, t3, and t4 to the following equation.

Delay time data = ((t4-t1)-(t3-t2)) / 2
As described above, the embodiment of the present invention basically uses NTP (Network Time Protocol) shown in the standard RFC1305 defined by IETF (Internet Engineering Task Force) for measurement of propagation delay time. For the content of RFC1305, refer to, for example, http://www.faqs.org/rfcs/rfc1305.html. The NTP measures the round trip propagation delay time, approximates that each propagation delay time in the downstream direction from the master device to the slave device direction and the upstream direction from the slave device to the master device direction is equal, Obtain the propagation delay time. In this method, if the amount of fluctuation in the upstream direction and the downstream direction are the same as the propagation delay time, there is no difference between the obtained propagation delay time and the actual propagation delay time. However, in reality, if the amount of fluctuation is different between the upstream direction and the downstream direction, it is unlikely that the propagation delay time is completely equal. Also, even if the propagation delay time in the up and down directions is equal to the reality, and the propagation delay time can be measured accurately, it is not possible to simply adopt the obtained propagation delay time when the fluctuation amount of sudden fluctuation occurs. Good clock synchronization cannot be realized. Therefore, in this embodiment, as will be described later, the slave device further accumulates the propagation delay time of the clock packet, takes the average value of the accumulated propagation delay time, and acquires the corrected clock data using the average value.

  FIG. 5 shows an operation procedure in which the slave device 30 realizes clock synchronization based on the average value of the delay time data. Here, the slave device 30 includes the units shown in FIG. 2, that is, the deviation confirmation unit 34, the first delay time accumulation unit 35, the second delay time accumulation unit 36, the average value calculation unit 37, the clock information correction unit 38, The clock information update unit 39, the slave clock unit 40, and the PLL unit 41 are operated to realize clock synchronization.

  First, in the deviation confirmation unit 34, the slave device 30 calculates a difference between the delay time data and the average value calculated so far by the average value calculation unit 37 for each delay time data (step S21). Next, it is determined whether or not the difference is within the deviation X (step S22). If it is within the deviation X, the delay time data is stored in the first delay time accumulating unit 35 as the deviation data (≦ X) (step S23). Next, the process proceeds to step S28.

  On the other hand, if the delay time data does not fall within the deviation X, the deviation confirmation unit 34 stores the delay time data as non-deviation data (> X) in the second delay time accumulation unit 36 (step S24). ). Next, the continuity of out-of-deviation data is determined (step S25). That is, it is determined whether or not each delay time data is continuously deviated by Y (predetermined integer) times or more (step S26). If it has not deviated more than Y consecutive times, the operation procedure is terminated at that time, and the clock correction is stopped until the next clock packet arrives. As a result, the PLL unit 41 maintains a self-running state. On the other hand, if it is out of the continuous Y times or more, all the data in the first delay time storage unit 35 is cleared, and all the data stored in the second delay time storage unit 36 is transferred to the first delay time storage unit 35. Move (step S27). Next, the process proceeds to step 28.

Next, in the slave device 30, in the average value calculation unit 37, when the delay time data is within the deviation X, or when the deviation is not within the deviation X, but is continuously out of deviation Y times or more. Then, the delay time data group is read from the first delay time accumulation unit 35, and a new average value is calculated (step S28). Next, the clock information correction unit 38 corrects the average value as the propagation delay time between the master device and the slave device with respect to the clock data to generate corrected clock data (step S29). Next, the clock information update unit 39 updates the count value of the cyclic counter 39a of the slave clock unit 40 to the count value of the modified clock data (step S30). Next, PLL phase data is generated from the count value of the cyclic counter 39a and is input to the PLL unit 41, thereby controlling the frequency of the slave clock signal generated by the slave clock unit 40 (step S31).
<Operational effect of the present invention>
As described above, in the embodiment according to the present invention, the slave device measures the average value of the propagation delay time, and when the difference between the propagation delay time and the average value of a certain clock packet is large, the clock packet is synchronized with the clock. By not adopting it, it responds to sudden fluctuations in fluctuations and continuous fluctuations in fluctuations. Since a clock packet that is not employed for clock synchronization is generated, the PLL (Phase Locked Loop) of the slave device is in a free-running state until the next clock packet arrives. Accordingly, the master device preferably continuously transmits clock packets periodically so that the PLL self-running period is preferably as short as possible.

  Further, in the embodiment according to the present invention, the slave device uses the double buffer method for accumulating the propagation delay time to avoid a state where clock synchronization is impossible. For example, if the propagation delay time fluctuates significantly, such as when the route on the packet network changes, the delay time data continues to deviate from the deviation, and the average value is permanently new. An event that does not follow this occurs and clock synchronization becomes impossible. Therefore, in this embodiment, two portions for storing the propagation delay time are provided in the slave device as a double buffer method. That is, a first accumulating unit that accumulates data that falls within the deviation and a second accumulating unit that accumulates data that does not fall within the deviation are provided. All entered data is cleared, and data that does not fall within the deviation is newly used for average calculation. As a result, it is possible to quickly follow a large fluctuation in the propagation delay time. With these configurations, the present invention does not require a relay device such as a special router or switch, and can cope with both sudden fluctuations or continuous fluctuations in fluctuations and significant propagation delay time fluctuations due to path changes. It is possible to realize a good clock synchronization that suppresses the deterioration of the wander component as much as possible.

DESCRIPTION OF SYMBOLS 10 Packet network 20 Master apparatus 21 Master clock part 22 Clock information generation part 22a Cyclic counter 23 Clock packet transmission part 24 Clock packet reception part 30 Slave apparatus 31 Clock packet reception part 32 Clock packet transmission part 33 Propagation delay time calculation part 34 Deviation confirmation Unit 35 first delay time accumulating unit 36 second delay time accumulating unit 37 average value calculating unit 38 clock information correcting unit 39 clock information updating unit 39a cyclic counter 40 slave clock unit 41 PLL unit

Claims (3)

A clock synchronization method for synchronizing a slave clock signal of a slave device among a plurality of communication devices that transmit and receive data packets via a packet network with a master clock signal of a master device of the communication devices,
In the master device, a clock packet transmission step of transmitting a clock packet storing the count value of the master clock signal at the time of transmission to the slave device at a predetermined frequency;
In the slave device, a delay time data acquisition step of acquiring delay time data representing the propagation delay time by measuring a propagation delay time with the master device for each clock packet;
In the slave device, an average value calculating step of storing delay time data corresponding to each of the clock packets and calculating an average value of the accumulated delay time data group;
In the slave device, the phase value of the slave clock signal is controlled by correcting the count value of the clock packet based on the average value and updating the count value of the slave clock signal to the corrected count value. and a phase control step, only including,
In the average value calculating step, the delay time data corresponding to each of the clock packets is divided and accumulated into data within deviation and data outside deviation based on a predetermined deviation threshold by comparing with the previously calculated average value. When a new average value is calculated only from the accumulated data group within deviation, while the non-deviation data continues for a predetermined number of times or more for each clock packet, a new average value is calculated only from the accumulated non-deviation data group. A clock synchronization method characterized by calculating a value . The delay time data acquisition step includes:
The clock packet transmitted in the clock packet transmission step is the first clock packet, the count value of the first clock packet is held as time t1, and the count value of the slave clock signal when the first clock packet arrives Holding as time t2,
Transmitting a second clock packet to the master device and holding a count value of the slave clock signal at the time of transmission as a time t3;
The third clock packet storing the count value of the master clock signal when the second clock packet reaches the master device is received from the master device, and the count value of the third clock packet is received at time t4. As a step to hold as
The held times t1, t2, t3 and t4 are
Delay time data = ((t4-t1)-(t3-t2)) / 2
The clock synchronization method according to claim 1, further comprising: calculating the delay time data by applying to an equation consisting of : Including a plurality of communication devices that transmit and receive data packets via a packet network, wherein a slave device of the communication devices synchronizes its slave clock signal with a master clock signal of a master device of the communication devices. A packet communication system for processing the data packet ,
The master device includes a clock packet transmitting means for transmitting a clock packet in which a count value of the master clock signal at the time of transmission is stored to the slave device at a predetermined frequency,
The slave device is
Delay time data acquisition means for acquiring the delay time data representing the propagation delay time by measuring the propagation delay time with the master device for each clock packet;
Average value calculating means for storing delay time data corresponding to each of the clock packets and calculating an average value of the accumulated delay time data group;
In the slave device, the phase value of the slave clock signal is controlled by correcting the count value of the clock packet based on the average value and updating the count value of the slave clock signal to the corrected count value. Phase control means, and
The average value calculating means stores the delay time data corresponding to each of the clock packets by dividing it into data within deviation and data outside deviation based on a predetermined deviation threshold value by comparing with the previously calculated average value. When a new average value is calculated only from the accumulated data group within deviation, while the non-deviation data continues for a predetermined number of times or more for each clock packet, a new average value is calculated only from the accumulated non-deviation data group. A packet communication system characterized by calculating a value .

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