JP5167862B2 - Clock synchronization system, clock synchronization method, program, and recording medium - Google Patents

Description

  The present invention relates to a clock synchronization system, a clock synchronization method, a program, and a recording medium.

  Telecommunications carriers are proceeding with the construction of high-speed data communication networks in order to realize higher value-added services. High-speed data communication networks require large traffic capacity, so low-cost and high-efficiency Internet Protocol (IP) is more suitable than high-cost Time Division Multiple (TDM) .

  However, when shifting the network to the IP system, depending on the application, it is necessary to transmit accurate clock information to a device connected to the packet network. For example, in order to exchange real-time data such as voice and video with high quality between a transmitter and a receiver, it is necessary to reproduce the data at a predetermined timing, and a stable clock is indispensable.

  Also, in a mobile network or the like, an accurate clock is indispensable for realizing handover between cells without delay. Specifically, each base station on a mobile network must be clock synchronized with an accuracy of 50 parts per billion (ppb). If the base station clock drifts beyond this 50 ppb frame, handover between cells may fail, and packets may be dropped or communication quality may be degraded.

  Thus, in order to realize stable service quality, a method capable of transmitting accurate clock information via a packet network is required. A promising technique that can solve this problem is the time stamp method.

The time stamp method can be easily implemented and can achieve excellent clock synchronization accuracy.
FIG. 9 shows a configuration diagram of the time stamp method.
In the time stamp method, the master node transmits a packet with a time stamp to the slave node, and the slave node adjusts its own clock based on the time stamp, thereby achieving clock synchronization.
More specifically, this time stamp is used to generate a control signal of a phase locked loop (PLL). That is, the PLL calculates a difference between its own clock and a newly arrived time stamp, and adjusts its own clock based on the difference, thereby realizing clock synchronization.

  Here, the PLL mainly consists of four functions. That is, a phase comparator, a loop filter, a voltage controlled oscillator (VCO) and a counter. The phase comparator calculates a differential signal between the reception timestamp and the output signal of the VCO. This difference signal is input to the loop filter, and jitter and noise are suppressed. Further, PI (Proportional Integral) control is performed on the difference signal, and a control signal that finally drives to zero is output to the VCO. The VCO outputs a clock having a frequency determined by a control signal from the loop filter. The counter generates a time stamp based on the frequency from the VCO and outputs it to the phase comparator.

Patent Documents 1 to 5 describe techniques related to clock control.
The PLL circuit described in Patent Document 1 is a PLL circuit that generates a system clock using a time stamp transmitted in a data packet, and inputs the data packet and records it at a predetermined position in the packet. The time stamp extracting means for extracting and outputting the generated time stamp, the frequency dividing means for dividing the system clock to the time stamp period and outputting the divided value, the time stamp and the divided value are compared, and the frequency If the phase of the division value is delayed due to the pull-in, an up signal is output, and if the phase of the division value is advanced, a phase comparison means that outputs a down signal, and an up signal and a down signal are input. According to these inputs, the N-bit counter (N is an integer of 2 or more) is counted up and down to output the N-bit count value. Up / down counter means for inputting the count value, and adding the N-bit count value and the output of the N-bit addition means in a cycle equal to or less than 1 / N of the cycle in which the count value is updated, Adding means for outputting the highest-order carry of the addition result, low-pass filter means for inputting the carry, removing the high-frequency component of the carry and outputting the control voltage, and inputting the control voltage, according to the control voltage And a variable frequency oscillating means for outputting a system clock by converting the frequency into a predetermined frequency.

  According to this PLL circuit, the output of the up / down counter is input to the adder, and the carry output pulse of the operation that is fed back is averaged to generate the VCO control voltage. A stable PLL circuit can be realized. It is also easy to increase the apparent number of bits in order to increase accuracy.

  The method described in Patent Document 2 is a time synchronization method for performing time synchronization between a clock master having a first clock and a clock slave having a second clock. B. sending a first message to the clock master, the first message having information representing a first sending time of the first message; Receiving a second message from the clock master, the second message comprising information representing a first receipt time of the first message and a second delivery time of the second message; C. C. obtaining a second receipt time of the second message at the clock slave; Calculating a transmission delay between the clock slave and the clock master from the first and second reception times and the first and second transmission times; Determining whether or not the calculated transmission delay is within an allowable delay window and, if the calculated transmission delay is within the window, updating the accumulation delay with the calculated transmission delay; and It is provided.

  According to this method, the clock slave generates a first timing cell including information on the transmission time, and transmits the first timing cell to the clock master. Upon receiving the first timing cell, the clock master generates a second timing cell and sends it to the clock slave. The second timing cell has a time when the first timing cell is received and a time when the second timing cell is transmitted. When the clock slave receives the second timing cell, the clock slave acquires the reception time, and calculates a transmission delay based on the reception time and the timing information included in the timing cell. At this time, in order to exclude undesirable data from the synchronization processing, the variable window filtering function is used to accurately synchronize the time between components of the wireless communication system.

  The packet transmission control device described in Patent Document 3 controls packet transmission in a device that transmits or relays a packet sequence composed of two or more packets each carrying a part of predetermined data or data obtained by encoding the data. A first means for acquiring the transmission processing time of each packet in the packet sequence; a second means for acquiring an ideal transmission processing time of each packet in the packet sequence; A third means for subtracting the ideal transmission processing time of the one packet from the transmission processing time of the single packet and discarding the single packet without transmitting when the time exceeds a certain time. is there.

  According to this packet transmission control device, by discarding a packet whose transmission processing is delayed over a certain time on the transmission side or the relay point side, the network on the reception side can be considered without considering fluctuations due to transmission processing delay. Control for delay fluctuation absorption can be performed in consideration of only fluctuation due to delay, and as a result, the average delay can be shortened.

  The packet transmission system described in Patent Document 4 is a packet transmission system that performs packet transmission, and measures a packet gap extraction unit that extracts a packet gap from a packet stream in which packet data is multiplexed, and measures the extracted packet gap. Packet transmission device comprising: a packet gap measurement unit that generates gap information that is a value; and a packet data transmission unit with gap information that adds gap information to packet data and generates and transmits packet data with gap information Between the packet data with gap information, which receives the packet data with gap information and separates the gap information and the packet data, and the packet gap adjusted based on the gap adjustment value between the buffered packet data Insert The packet gap insertion unit, the packet buffer that stores the packet data and the packet gap to be inserted, and the buffer usage of the packet buffer are monitored. If the buffer usage exceeds the overflow detection threshold, the packet gap And a packet monitoring device configured to generate a gap adjustment value for increasing the packet gap when the buffer usage is below the underflow detection threshold. is there.

  According to this packet transmission system, the packet transmission device extracts a packet gap from the packet stream, measures the packet gap, generates gap information, generates packet data with gap information, and transmits the packet data. The gap adjustment value to decrease the packet gap when the buffer usage of the packet buffer exceeds the overflow detection threshold, and to increase the packet gap when the buffer usage is lower than the underflow detection threshold And a packet gap with the gap amount adjusted is inserted between the buffered packet data based on the gap adjustment value. As a result, it is possible to suppress the occurrence of overflow and underflow and to reproduce the packet interval on the transmission side with high accuracy on the reception side to perform high-quality packet transmission.

  The clock synchronization method described in Patent Document 5 synchronizes a transmission side clock signal and a reception side clock signal in a packet transmission system that transmits a packet including data to be processed according to a clock signal via a transmission network. A clock synchronization method, wherein a transmission time stamp is added to a transmission packet supplied to a transmission network, wherein the transmission time stamp changes in synchronization with a transmission side clock signal and includes time information indicating a supply timing to the transmission network. An addition step and a reception time stamp addition for adding a reception time stamp that includes time information that changes in synchronization with the reception-side clock signal and indicates the timing of acquisition from the transmission network to a transmission packet that is captured as a reception packet from the transmission network Steps and received packets are arranged in the order of the time of the transmission timestamp. For each of a series of received packets, a received packet included in each of the accumulated periods of a predetermined time length is extracted from the series of received packets, and for each of the series of extracted received packets obtained by extraction, A difference accumulated value calculating step for calculating a difference accumulated value for each extracted received packet by calculating a difference value between a transmission timestamp interval and a reception timestamp interval determined between And a frequency adjusting step for adjusting the frequency of the received clock signal accordingly.

According to this clock synchronization method, there is a synchronization method and circuit between a transmission side clock signal and a reception side clock signal in a packet transmission system for transmitting a packet including data processed according to a clock signal via a transmission network. A transmission time stamp is added to a transmission packet supplied to the transmission network, and a reception time stamp is added to the transmission packet every time the transmission packet is fetched from the transmission network as a reception packet. A transmission time stamp determined by extracting a reception packet included in a predetermined time length from a series of reception packets obtained by arranging reception packets in the order of the time of the transmission time stamp, and with an extracted reception packet before or after that A difference value between the interval and the reception timestamp interval is calculated, and this is accumulated for each extracted reception packet to calculate a difference accumulation value, and the frequency of the reception clock signal is adjusted according to the difference accumulation value. As a result, output jitter on the receiving side can be appropriately suppressed.
JP 2000-244473 A JP 2001-308837 A JP 2006-94130 A JP 2007-258932 A JP 2007-306497 A

Here, the condition that the clock synchronization accuracy is the best is a case where there is only a fixed delay between the master and slave nodes, and the time stamp periodically arrives at the slave node side.
However, such a case cannot be a packet network.

  In packet networks, there are delay variations and jitter is introduced into the arrival time of the time stamp, which makes clock synchronization very difficult. There are mainly two factors that appear as jitter on the slave node side.

  The first factor is the clock drift between the master and slave nodes, but the effect is minor compared to the second factor.

The second factor is the network delay variation described above, which results in very large jitter in the time stamp arrival time. By the way, the cause of the delay variation is due to the fact that the forwarded packet is randomly waited in the switch queue.
A certain amount of jitter can be absorbed by the PLL loop filter. However, if jitter exceeding the allowable value is received, it cannot be absorbed and the synchronization accuracy is deteriorated.

FIG. 10 is a diagram showing the relationship between the recovered clock frequency and time according to the technique related to the present invention. In the figure, the horizontal axis represents time, and the vertical axis represents the recovered clock frequency.
FIG. 10 shows how the clock synchronization accuracy deteriorates when a packet with a jitter larger than the expected value comes in.

Therefore, in order to maintain synchronization accuracy, a packet filter is provided in front of the PLL (see FIG. 11), and a time stamp including jitter exceeding the allowable value (threshold value) is filtered to allow the allowable value (threshold value). It is necessary to add measures such as using only the following time stamps for clock synchronization (see FIG. 12).
FIG. 11 is a block diagram of a clock synchronization system related to the present invention. FIG. 12 is a diagram showing the relationship between the number of packets and jitter in the clock synchronization system shown in FIG. In FIG. 12, the horizontal axis indicates jitter, and the vertical axis indicates the number of packets.

However, if the time stamp of the large jitter packet is filtered, including the techniques described in Patent Documents 1 to 5, the PLL is in an unstable self-running state. When falling into such a free-running state, the clock fluctuates due to temperature drift and aging.
The temperature drift of the PLL is very large even with a temperature compensated crystal oscillator (TCXO) (~ 3000ppb / ° C), so if the time stamp packet is continuously filtered, the effect of this temperature drift There is a risk that will become apparent and cause out-of-synchronization. As a result, for example, when the FFO (Fractional Frequency Offset) value of the slave node is 50 ppb or more, handover between cells cannot be realized without delay in a mobile network or the like.

  As described above, it is very difficult to realize stable clock synchronization by simply filtering a time stamp including jitter larger than the threshold.

  Therefore, the present invention has been made to solve such a problem, the purpose of which is to reduce the influence of delay variation of the network without falling into an unstable self-running state, It is an object to provide a clock synchronization system, a clock synchronization method, a program, and a recording medium that can realize accurate clock synchronization.

  A first system of the present invention is a clock synchronization system that synchronizes a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node. A time stamp packet generating means for generating a stamp packet; and a packet transmission amount control means for controlling the number of time stamp packets to be generated, wherein the slave node is a jitter filter means for filtering a time stamp whose jitter is larger than a threshold value. And a request message generating means for generating a request message for controlling the transmission amount of the time stamp packet of the master node and transmitting the request message to the master node.

  A second system of the present invention is a clock synchronization system that synchronizes a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node. A time stamp packet generating means for generating a stamp packet; and a packet transmission amount control means for controlling the number of time stamp packets to be generated. The slave node is a jitter filter means for filtering a time stamp whose jitter is larger than a threshold value. The acceptance rate monitoring means that monitors the acceptance rate of the jitter filter and, when the acceptance rate is less than the threshold value, generates a request message for increasing the transmission amount of the time stamp packet and notifies the request message generation means to transmit the request message. With It is characterized in.

  A third system of the present invention is a clock synchronization system that synchronizes a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node. A time stamp packet generating means for generating a stamp packet; a packet transmission amount control means for controlling the number of time stamp packets to be generated; and a network monitoring means for monitoring a jitter change of the packet network. Jitter filter means for filtering a time stamp having a value larger than a threshold value is provided.

  A first method of the present invention is a clock synchronization method for generating a time stamp packet by synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node. Control the number of time stamp packets to be generated, filter time stamps whose jitter is greater than a threshold value, generate a request message for controlling the amount of time stamp packets transmitted by the master node, and transmit the request message to the master node. It is characterized by that.

  A second method of the present invention is a clock synchronization method for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node, and generates a time stamp packet Control the number of timestamp packets to be generated, control the amount of packet transmission, filter timestamps with jitter greater than the threshold, monitor the acceptance rate of the jitter filter, and if the acceptance rate is less than the threshold, A request message for increasing the transmission amount is generated and transmitted to the request message generating means.

  A third method of the present invention is a clock synchronization method for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node. And controlling the number of time stamp packets to be generated, monitoring a change in the jitter of the packet network, and filtering time stamps whose jitter is greater than a threshold value.

  A first program of the present invention is a program for causing a computer to execute processing for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node, The master node causes the master node to execute a time stamp packet generation process for generating a time stamp packet and a packet transmission amount control process for controlling the number of time stamp packets to be generated, and the slave node has a jitter greater than a threshold value. A jitter filter process for filtering a time stamp and a request message generation process for generating a request message for controlling a transmission amount of a time stamp packet of the master node and transmitting the request message to the master node are executed. .

  A second program of the present invention is a program for causing a computer to execute processing for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node, The master node causes the master node to execute a time stamp packet generation process for generating a time stamp packet and a packet transmission amount control process for controlling the number of time stamp packets to be generated, and the slave node has a jitter greater than a threshold value. Jitter filter processing that filters time stamps and the acceptance rate of the jitter filter are monitored. If the acceptance rate is less than the threshold value, a request message for increasing the amount of time stamp packets to be transmitted is generated and sent to the request message generation means. I will do it Characterized in that to execute the selection rate monitoring process, to notify.

  A third program of the present invention is a program for causing a computer to execute processing for synchronizing the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node. In the computer, a master node generates a time stamp packet for generating a time stamp packet, a packet transmission amount control process for controlling the number of time stamp packets to be generated, a network monitoring process for monitoring a jitter change in the packet network, And the slave node executes a jitter filter process for filtering a time stamp whose jitter is larger than a threshold value.

  The recording medium of the present invention records any one of the above programs.

  According to the present invention, when the jitter of the packet network becomes large, when the adoption rate of the time stamp in the filter device becomes low, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  One embodiment of a clock synchronization system according to the present invention is a clock synchronization system that synchronizes a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node, The master node includes a time stamp packet generating means for generating a time stamp packet and a packet transmission amount control means for controlling the number of time stamp packets to be generated, and the slave node filters time stamps whose jitter is larger than a threshold value. And a request message generating means for generating a request message for controlling the transmission amount of the time stamp packet of the master node and transmitting the request message to the master node.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the time stamp packet generation means of the master node increases the packet transmission amount by N (N is a natural number) times as requested by the packet transmission amount control means. In this case, the payload size is set to 1 / N.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the time stamp packet generation means of the master node is increased when the packet transmission amount is N times as requested by the packet transmission amount control means. The packet is characterized by not including a payload or including dummy data.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, when the packet transmission amount control means of the master node receives the request message from the slave node, the packet transmission amount is increased N times or 1 / N The time stamp packet generation means is notified as follows.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the jitter filter means of the slave node filters time stamps whose jitter is less than the threshold, and adopts time stamp packets whose jitter is less than the threshold. It is characterized by calculating the rate.

  Another embodiment of the clock synchronization system according to the present invention is a clock synchronization system that synchronizes the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node. The master node includes a time stamp packet generating means for generating a time stamp packet, and a packet transmission amount control means for controlling the number of time stamp packets to be generated, and the slave node has a time stamp whose jitter is larger than a threshold value. Jitter filter means for filtering and the acceptance rate of the jitter filter are monitored, and when the acceptance rate is less than the threshold, a request message for increasing the amount of time stamp packet transmission is generated and transmitted to the request message generation means Acceptance rate to notify Nitaringu means, characterized by comprising a.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the slave node monitors the adoption rate of the jitter filter, and reduces the transmission amount of the time stamp packet when the acceptance rate is higher than the threshold. And an acceptance rate monitoring means for notifying the request message generating means to transmit the request message to the request message generating means.

  Another embodiment of the clock synchronization system according to the present invention is characterized in that, in addition to the above configuration, the slave node determines a threshold value of the time stamp adoption rate from the relationship between the time stamp adoption rate and the clock synchronization accuracy. To do.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above-described configuration, the slave node has clock synchronization monitoring means for monitoring the clock accuracy of the PLL, and the clock synchronization accuracy of the PLL cannot satisfy the required accuracy. It is characterized by comprising acceptance rate monitoring means for notifying the request message generator to issue a request message for increasing the transmission amount of the time stamp packet when detected.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the slave node has clock synchronization monitoring means for monitoring the clock accuracy of the PLL, and the clock synchronization accuracy of the PLL satisfies the required accuracy. , The acceptance rate monitoring means for monitoring the adoption rate of the time stamp packet in the jitter filter means and notifying that a request message for controlling the transmission amount of the time stamp packet is issued if necessary, It is provided with.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above-described configuration, the slave node sets the advance interval of the time stamp generated from the clock f2 of its own node to the time stamp value of the received time stamp packet. PLL counter means for controlling to adjust to the change in the advance interval is provided.

  Another embodiment of the clock synchronization system according to the present invention is a clock synchronization system that synchronizes the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node. The master node includes a time stamp packet generating means for generating a time stamp packet, a packet transmission amount control means for controlling the number of time stamp packets to be generated, and a network monitoring means for monitoring a jitter change of the packet network. The slave node includes a jitter filter means for filtering a time stamp whose jitter is larger than a threshold value.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above-described configuration, the time stamp packet generation unit of the master node has a payload size when the packet transmission amount is N times as requested by the packet transmission amount control unit. Is 1 / N.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the time stamp packet generation unit of the master node increases when the packet transmission amount is N times as requested by the packet transmission amount control unit. The packet to be transmitted does not include a payload or includes dummy data.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, when the packet transmission amount control means of the master node receives notification from the network monitoring means, the packet transmission amount is multiplied by N or 1 / N. The time stamp packet generation means is notified as follows.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the network monitoring means of the master node is based on the RTT (Round-Trip Time) measurement result between the master node and the slave node. The network jitter is calculated, and information indicating whether or not the measurement result exceeds a threshold value is notified to the packet transmission amount control means.

  In another embodiment of the clock synchronization system according to the present invention, in addition to the above configuration, the network monitoring unit of the master node receives information on the occurrence of logical link switching between the master node and the slave node. The information is notified to the packet transmission amount control means.

  One embodiment of a clock synchronization method according to the present invention is a clock synchronization method for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from a master node to a slave node, Generating timestamp packets, controlling the number of timestamp packets to be generated, filtering timestamps with jitter greater than a threshold, generating request messages for controlling the amount of master node timestamp packets transmitted, It transmits to a master node, It is characterized by the above-mentioned.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, when the packet transmission amount is N (N is a natural number) times as requested by the packet transmission amount control means, the payload size is reduced to 1 / N. It is characterized by doing.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, when the packet transmission amount is N times as requested by the packet transmission amount control means, the increased packet does not include a payload or is a dummy It is characterized by including data.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above-described configuration, when a request message from a slave node is received, the time stamp packet generation means is configured to increase the packet transmission amount to N times or 1 / N. It is characterized by notifying.

  Another embodiment of the clock synchronization method according to the present invention is characterized in that, in addition to the above-described configuration, time stamps with jitter greater than a threshold are filtered and the adoption rate of time stamp packets with jitter less than the threshold is calculated. To do.

  Another embodiment of the clock synchronization method according to the present invention is a clock synchronization method for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from the master node to the slave node. , Generate time stamp packets, control packet transmission amount to control the number of time stamp packets to be generated, filter time stamps with jitter greater than threshold, monitor adoption rate of jitter filter, adoption rate is less than threshold In this case, a request message for increasing the transmission amount of the time stamp packet is generated and transmitted to the request message generating means.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, the adoption rate of the jitter filter is monitored, and when the acceptance rate is higher than the threshold, a request message for reducing the transmission amount of the time stamp packet is displayed. It is generated and notified to be transmitted to the request message generating means.

  Another embodiment of the clock synchronization method according to the present invention is characterized in that, in addition to the above-described configuration, the threshold value of the time stamp adoption rate is determined from the relationship between the time stamp acceptance rate and the clock synchronization accuracy.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, a clock synchronization monitoring step for monitoring the clock accuracy of the PLL, and a case where it is detected that the clock synchronization accuracy of the PLL does not satisfy the required accuracy The request message generator is notified to issue a request message for increasing the transmission amount of the time stamp packet.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, the PLL clock accuracy is monitored, and when it is detected that the PLL clock synchronization accuracy satisfies the required accuracy, the jitter filter step The time stamp packet adoption rate is monitored, and a request message for controlling the transmission amount of the time stamp packet is notified as necessary.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, the advance interval of the time stamp generated from the clock f2 of the own node is changed as the advance interval of the time stamp value of the received time stamp packet. It is characterized by controlling to match.

  Another embodiment of the clock synchronization method according to the present invention is a clock synchronization system that synchronizes the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node. Generating a time stamp packet, controlling the number of time stamp packets to be generated, monitoring a jitter change of the packet network, and filtering a time stamp having a jitter larger than a threshold value.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  Another embodiment of the clock synchronization method according to the present invention is characterized in that, in addition to the above configuration, when the packet transmission amount is N times as requested by the packet transmission amount control means, the payload size is set to 1 / N. To do.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above configuration, if the packet transmission amount is N times as requested by the packet transmission amount control means, does the increased packet contain no payload? Alternatively, dummy data is included.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above-described configuration, when a notification is received from the network monitoring unit, the time stamp packet generation unit is configured so that the packet transmission amount is N times or 1 / N. It is characterized by notifying.

  In addition to the above-described configuration, another embodiment of the clock synchronization method according to the present invention calculates network jitter based on the RTT measurement results every time between the master node and the slave node, and the measurement results set the threshold value. It is characterized by notifying the packet transmission amount control means of whether or not it exceeds.

  In another embodiment of the clock synchronization method according to the present invention, in addition to the above-described configuration, when information on logical link switching between the master node and the slave node is received, the information is used for packet transmission amount control. The means is notified.

That is, an embodiment of the first clock synchronization system according to the present invention includes a master node that generates and transmits a time stamp packet based on a base clock, and uses the time stamp packet as a clock for the master node. The slave node includes a slave node that synchronizes, and the master node has a packet transmission amount controller (13 in FIG. 1 described later) that controls the number of time stamp packets to be generated. In order to control the transmission amount, a request message generator (26 in FIG. 1 to be described later) that generates and transmits a request message and an acceptance rate of the received time stamp packet are monitored, and the acceptance rate is below a certain threshold. Request message to increase the amount of time stamp packet transmission When there is an acceptance rate monitoring device (25 in FIG. 1 to be described later) that notifies the request message generator to be transmitted, the jitter of the packet network increases, and the time stamp acceptance rate in the filter device decreases. However, by increasing the number of time stamps adopted within a unit time, the risk of falling into an unstable self-running state for a long time can be eliminated.
Thereby, the object of realizing the accurate clock synchronization of the present invention can be achieved.

In one embodiment of the second clock synchronization system according to the present invention, in addition to the configuration of the first clock synchronization system, the slave node has a clock synchronization monitor (see FIG. 7 described later) for monitoring the clock accuracy of the PLL. 27) and, when it is detected that the clock synchronization accuracy does not satisfy the required accuracy, the adoption rate monitor that notifies the request message generator to issue a request message for increasing the transmission amount of the time stamp packet (a diagram to be described later) 7) and 25), measurement of the clock synchronization monitor is not performed, as in the first clock synchronization system, instead of judging from the theoretical relationship or experience value of the change in the time stamp acceptance rate and the clock synchronization accuracy. By determining whether the clock synchronization accuracy satisfies the required accuracy based on the result, the first Lock increased clock synchronization accuracy reliability slave node compared to synchronization system, it is possible to increase the possibility of eliminating from falling long unstable self state.
Thereby, the object of realizing the accurate clock synchronization of the present invention can be achieved.

In one embodiment of the third clock synchronization system according to the present invention, in addition to the configurations of the first and second clock synchronization systems, the master node is a network monitor (described later) that monitors the jitter change of the packet network 3. 14) in FIG. 8 and the time stamp packet of the master node based on the time stamp adoption rate and the deterioration of the clock synchronization accuracy in the slave node as in the first and second clock synchronization systems. Rather than controlling the amount of transmission, the master node monitors the jitter change of the packet network 3, and when the jitter increases, the master node increases the amount of time stamp packet transmission by itself, and the slave node becomes unstable. Eliminates the risk of long-term self-propelled conditions.
Thereby, the object of realizing the accurate clock synchronization of the present invention can be achieved.

<Program and recording medium>
The clock synchronization system of the present invention described above is realized by a program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this.

  One embodiment of a program according to the present invention is a program for causing a computer to execute processing for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from the master node to the slave node. The master node causes the master node to execute a time stamp packet generation process for generating a time stamp packet and a packet transmission amount control process for controlling the number of time stamp packets to be generated. Jitter filter processing for filtering a time stamp larger than a threshold value, and request message generation processing for generating a request message for controlling the transmission amount of the time stamp packet of the master node and transmitting the request message to the master node. And butterflies.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the time stamp packet generation unit of the master node has a packet transmission amount N (N is a natural number) times as requested by the packet transmission amount control unit. In this case, a process for reducing the payload size to 1 / N is executed.

  In addition to the above-described configuration, another embodiment of the program according to the present invention increases the time stamp packet generation means of the master node when the packet transmission amount is N times as requested by the packet transmission amount control unit. The packet to be processed is characterized in that processing is performed so as not to include a payload or to include dummy data.

  In another embodiment of the program according to the present invention, in addition to the above configuration, when the packet transmission amount control means of the master node receives a request message from the slave node, the packet transmission amount is increased N times or 1 / A process of notifying the time stamp packet generating means to N is executed.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the jitter filter means of the slave node filters a time stamp packet having a jitter less than the threshold while the jitter filter means of the slave node filters the time stamp packet having a jitter less than the threshold. A process for calculating the acceptance rate is executed.

  Another embodiment of the program according to the present invention is a program for causing a computer to execute processing for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from the master node to the slave node. The master node causes the master node to execute a time stamp packet generation process for generating a time stamp packet and a packet transmission amount control process for controlling the number of time stamp packets to be generated. Filter processing that filters time stamps that are greater than the threshold, and monitoring the acceptance rate of the jitter filter. If the acceptance rate is less than the threshold value, a request message is generated to increase the amount of time stamp packets transmitted. Generator Selection rate monitoring process, to notify to send to, characterized in that for the execution.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the slave node monitors the acceptance rate of the jitter filter in the computer, and when the acceptance rate is higher than the threshold, the transmission amount of the time stamp packet is reduced. And a selection rate monitoring process for notifying the request message generating means to transmit the request message to the request message generating means.

  In another embodiment of the program according to the present invention, in addition to the above configuration, the slave node causes the computer to execute a process of determining a threshold value of the time stamp adoption rate from the relationship between the time stamp adoption rate and the clock synchronization accuracy. It is characterized by making it.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the slave node in the computer monitors the clock accuracy of the PLL and the clock synchronization accuracy of the PLL cannot satisfy the required accuracy. When the message is detected, an acceptance rate monitoring process for notifying the request message generator to issue a request message for increasing the transmission amount of the time stamp packet is performed.

  In another embodiment of the program according to the present invention, in addition to the above configuration, the slave node in the computer satisfies the required accuracy with the clock synchronization monitoring process in which the slave node monitors the PLL clock accuracy and the PLL clock synchronization accuracy. An admission rate monitoring process for monitoring the admission rate of the time stamp packet in the jitter filter means and notifying that a request message for controlling the transmission amount of the time stamp packet is issued if necessary. , Is executed.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the slave node indicates the advance interval of the time stamp generated from the clock f2 of the own node to the computer, and the time stamp value of the received time stamp packet. The counter processing of the PLL that is controlled so as to match the change in the advance interval is executed.

  Another embodiment of the program according to the present invention is a program for causing a computer to execute processing for synchronizing a clock of a slave node with a clock of a master node using a time stamp packet transmitted from the master node to the slave node. A network in which a master node in a computer monitors a change in jitter of a packet network, a time stamp packet generation process in which a time stamp packet is generated, a packet transmission amount control process in which the number of time stamp packets to be generated is controlled And a monitoring process, and the slave node executes a jitter filter process for filtering a time stamp whose jitter is larger than a threshold value.

  According to the above configuration, when the jitter of the packet network increases, when the adoption rate of the time stamp in the filter unit decreases, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. In this way, it is possible to eliminate a long time falling into a free-running state, so that it is possible to realize clock synchronization that operates stably even in an actual field.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the time stamp packet generating unit of the master node may have a payload when the packet transmission amount is N times as requested by the packet transmission amount control unit. A process for reducing the size to 1 / N is executed.

  In another embodiment of the program according to the present invention, in addition to the above configuration, when the time stamp packet generation unit of the master node has a packet transmission amount N times as requested by the packet transmission amount control unit, The incremented packet is characterized in that a process of not including a payload or including dummy data is executed.

  In another embodiment of the program according to the present invention, in addition to the above configuration, when the packet transmission amount control unit of the master node receives notification from the network monitoring unit, the packet transmission amount is increased N times or 1 / A process of notifying the time stamp packet generating means to N is executed.

  In another embodiment of the program according to the present invention, in addition to the above-described configuration, the network monitoring unit of the master node causes the computer to perform network jitter based on the RTT measurement result between the master node and the slave node. It is characterized in that a process for calculating and a process for notifying the packet transmission amount control means of information on whether or not the measurement result exceeds a threshold value are executed.

  In another embodiment of the program according to the present invention, in addition to the above configuration, the network monitoring unit of the master node has received information on the occurrence of logical link switching between the master node and the slave node. In this case, a process of notifying the packet transmission amount control means of the information is executed.

  An embodiment of a recording medium according to the present invention is a recording medium on which any one of the above programs is recorded.

Thus, the clock synchronization system of the present invention can be realized anywhere as long as there is a computer environment capable of executing the program.
Such a program may be recorded on a computer-readable recording medium.

  Here, examples of the recording medium include a computer-readable recording medium such as a CD-ROM (Compact Disc Read Only Memory), a flexible disk (FD), a CD-R (CD Recordable), and a DVD (Digital Versatile Disk). Semiconductor memories such as HDD (Hard Disc Drive), flash memory, RAM (Random Access Memory), ROM (Read Only Memory), and FeRAM (ferroelectric memory).

  Network delay variation introduces very large jitter in the time stamp arrival time. A certain amount of jitter can be absorbed by the PLL loop filter. However, if jitter exceeding the allowable value is received, it cannot be absorbed and the synchronization accuracy is deteriorated. To maintain synchronization accuracy, a packet filter is provided in front of the PLL to filter time stamps that include jitter that exceeds the allowable value (threshold value), so that only time stamps below the allowable value (threshold value) are clock-synchronized. It is necessary to add countermeasures such as using them.

  However, if the time stamp of the large jitter packet is filtered, the PLL is in an unstable self-running state during that time. When falling into such a free-running state, the clock fluctuates due to temperature drift and aging. In this patent proposal, when the jitter of the packet network becomes large, when the adoption rate of the time stamp in the filter device becomes low, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. Since the risk of falling into a free-running state for a long time can be eliminated, clock synchronization that operates stably even in an actual field can be realized.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

  Next, an embodiment of a clock synchronization system according to the present invention will be described in detail with reference to the drawings.

<Configuration>
FIG. 1 is a block diagram showing an embodiment of a clock synchronization system according to the present invention.
The clock synchronization system shown in FIG. 1 includes a master node 1, a slave node 2, and a packet network 3.

<Master node>
The master node 1 includes a time stamp packet generator 11, a packet transmitter / receiver 12, and a packet transmission amount controller 13.
The time stamp packet generator 11 generates a time stamp packet based on the clock f1 of the master node. The value of the time stamp is, for example, such that it increases by A for each packet.
The packet transmitter / receiver 12 transmits and receives time stamp packets and control messages, and distributes packets received from the slave node 2.

  The packet transmission amount controller 13 controls the transmission amount of the time stamp packet based on the request message from the slave node 2. For example, when a message requesting to increase the number of time stamp packets is received from the slave node 2, the packet transmission amount controller 13 changes the time stamp packet so as to change the transmission amount of the time stamp packet to N times. Notify the generator 11. Conversely, when a message requesting to reduce the number of time stamp packets is received from the slave node 2, the packet transmission amount controller 13 changes the time stamp so as to change the transmission amount of the time stamp packet to 1 / N. Notify the packet generator 11.

<Slave node>
The slave node includes a packet transmitter / receiver 21, a time stamp extractor 22, a jitter filter 23, a PLL 24, an acceptance rate monitor 25, and a request message transmitter 26.
The packet transmitter / receiver 21 transmits and receives time stamp packets and control messages.
The time stamp extractor 22 extracts time stamp information from the time stamp packet received from the packet transmitter / receiver 21 and passes it to the jitter filter 23.
The jitter filter unit 23 calculates the delay jitter of each received time stamp and checks whether or not the value is within a certain threshold range. If the threshold is exceeded, the corresponding time stamp is discarded.

On the contrary, if it falls within the threshold value, the time stamp is passed to the PLL 24. Further, the adoption rate of the time stamp is periodically calculated and passed to the acceptance rate monitor 25.
The PLL 24 regenerates the clock f2 from the time stamp received from the jitter filter unit 23. As shown in FIG. 2, the PLL 24 includes a phase comparator 241, a loop filter 242, a VCO 243, and a counter 244.

FIG. 2 is an example of a block diagram of the PLL shown in FIG.
The phase comparator 241 receives the time stamp, compares the phase difference with the time stamp received from the counter 242, and outputs a difference signal to the loop filter 242.
The loop filter 242 converts a control signal generated by converting the difference signal input from the phase comparator 241 into a direct current (cutting off a high frequency component) via an LPF (Low-pass filter) and a PI control function. Output to.

The VCO 243 generates the clock f2 by the control signal input from the loop filter 242 and outputs the generated clock signal to the counter 244.
The counter 244 generates time stamp information based on the clock input from the VCO 243 and outputs the information to the phase comparator 241. Further, a function is used in which the advance interval of the time stamp generated based on the clock f2 received from the VCO is matched with the change of the advance interval of the time stamp value received by the phase comparator 241.

The adoption rate monitor 25 monitors the adoption rate of the time stamp in the jitter filter unit 23, and notifies the request message transmitter 26 when the acceptance rate falls below a certain threshold.
The request message transmitter 26 generates a request message for increasing the amount of transmission of the time stamp packet when receiving a notification from the adoption rate monitor 25 that the adoption rate of the time stamp falls below a certain threshold. The data is transmitted to the master node 1 via the transceiver 21.

<Operation>
Next, the operation of the first embodiment for carrying out the present invention will be described in detail.
In order to realize high-accuracy clock synchronization in the slave node, when a time stamp including a large delay jitter that exceeds the threshold value is received, it is necessary to discard the time stamp and suppress deterioration in clock synchronization accuracy. However, when the jitter of the packet network increases, the time stamp adoption rate decreases, but if the time stamp adoption rate is too low, the clock falls into an unstable free-running state for a long time. There is a risk that the synchronization accuracy will deteriorate.

For example, FIG. 3 shows an empirical value of the relationship between the time stamp adoption rate and the FFO in the slave node. If the time stamp adoption rate of the small jitter packet is 30% or less, the FFO value may be 50 ppb or more. There is. When the FFO value of the slave node is 50 ppb or more, for example, handover between cells cannot be realized without delay in a mobile network or the like.
Here, FIG. 3 is a diagram showing a change in clock synchronization accuracy according to a time stamp adoption rate used in the clock synchronization system shown in FIG. In the figure, the horizontal axis indicates the time stamp adoption rate, and the vertical axis indicates FFO.

  In order to solve this problem, in the first embodiment of the present invention, when the adoption rate monitoring function of the time stamp packet is provided to the slave node, if the time stamp adoption rate is too low, the time stamp packet is sent to the master node. The master node can receive the request from the slave node and adjust the transmission amount of the time stamp packet. If the amount of time stamp packet transmission increases, even if the jitter of the packet network increases, the number of small jitter time stamps adopted in the unit time in the slave node increases, so that the clock becomes unstable and free running. Eliminate the risk of falling for a long time.

As shown in FIG. 4, when the adoption rate of the time stamp within a certain time T is lower than a certain threshold value P (for example, 30%), the slave node causes the master node to increase the transmission amount of the time stamp packet. By requesting it, the transmission amount of the time stamp packet of the master node is adjusted.
FIG. 4 is a diagram showing the relationship between the adoption rate of time stamp packets used in the clock synchronization system shown in FIG. 1 and time. In the figure, the horizontal axis represents time, and the vertical axis represents the adoption rate of the type stamp packet.

Hereinafter, the above operation will be described in detail with reference to FIGS.
FIG. 5 is an example of the flow of the clock synchronization method according to the present invention.
First, operations of the master node 1 and the slave node 2 will be described with reference to FIG.

<Master node>
The time stamp packet generator 11 of the master node 1 generates a time stamp packet with a time stamp based on the clock f1 of its own node, and transmits it to the slave node 2 via the packet transmitter / receiver 12.

  The packet transmitter / receiver 12 transmits and receives time stamp packets and control messages. For example, a time stamp packet received from the time stamp packet generator 11 is passed to the slave node 2, and a request message received from the slave node 2 is passed to the packet transmission amount controller 13.

The packet transmission amount controller 13 controls the number of time stamp packets generated by the time stamp generator 11 based on the request message from the slave node 2 received via the packet transmitter / receiver 12. For example, when a request message for increasing the transmission amount of the time stamp packet is received from the slave node 2, the time stamp generator 11 is notified so that the packet transmission amount is increased N times.
On the contrary, when a request message for reducing the transmission amount of the time stamp packet is received, the time stamp generator 11 is notified so that the packet transmission amount becomes 1 / N.

<Slave node>
The slave node 2 receives the time stamp packet transmitted from the master node 1 via the packet transmitter / receiver 21.
The packet transmitter / receiver 21 passes the received time stamp packet to the time stamp extractor 22.
The time stamp extractor 22 extracts time stamp information from the received time stamp packet and passes it to the jitter filter 23.
The jitter filter unit 23 calculates the jitter of each received time stamp and passes the calculation result to the acceptance rate monitoring unit 25. If the calculation result exceeds a certain threshold, the time stamp is discarded, and if within the threshold, the time stamp is passed to the PLL 24.
The PLL 24 regenerates a new clock f2 based on the time stamp information received from the jitter filter unit 23. The counter of the PLL 24 looks at the change in the advance interval of the time stamp value of the received time stamp packet, and determines the advance interval of the time stamp generated based on the clock f2 received from the VCO of the PLL 24. To match. In the PLL 24, the operations of modules other than the counter are the same as those of the technology related to the present invention, and thus detailed description thereof is omitted.

The acceptance rate monitor 25 monitors the adoption rate of the time stamp in the jitter filter 23, and when the acceptance rate falls below a certain threshold, transmits a request message so as to generate a request message for increasing the time stamp packet. The device 26 is notified.
On the contrary, when the adoption rate is high and the clock synchronization accuracy is guaranteed, the request message transmitter 26 may be notified to generate a request message for reducing the time stamp packet.

  Upon receiving the notification from the acceptance rate monitoring device 21, the request message transmitter 26 generates a request message for increasing (or decreasing) the transmission amount of the time stamp packet, and the master node via the packet transmitter / receiver 21. 1 to send.

  Next, the operation of the acceptance rate monitoring unit 25 of the slave node 2 will be described with reference to the flowchart of FIG. Here, only the operation for generating a request message for increasing the time stamp packet will be described.

The adoption rate monitor 25 predicts the threshold P of the time stamp acceptance rate from the relationship between the time stamp acceptance rate of the small jitter packet and the FFO of the slave node (step 25a).
Next, the time stamp acceptance rate Pi is periodically received from the jitter filter unit 23.
Next, the time stamp adoption rate Pi is compared with the threshold value P, and when the Pi value within a certain time T becomes lower than P, the request message generator 26 is notified and a request message is transmitted to the master node. On the contrary, when the Pi value is higher than P, the next cycle is compared.

Subsequently, an operation after transmission / reception of a request message in the entire synchronous system including the master node 1 and the slave node 2 will be described.
The master node 1 that receives the request message increases the number of time stamp packets to be transmitted based on the setting contents. For example, assume that the master node 1 changes the transmission amount of the time stamp packet to twice the previous time each time it receives a request message. In order to change the transmission amount of the time stamp packet to double, the advance interval of the time stamp value generated by the time stamp packet generator 11 of the master node 1 is shortened to ½.

  In the slave node 2, the change in the advance interval of the time stamp value of the received time stamp packet is observed, and the advance interval of the time stamp generated based on the clock f2 of the own node is matched with the advance interval of the received time stamp. For example, when the advance interval of the time stamp value received from the master node 1 is shortened to ½, the counter 244 of the PLL 24 of the slave node 2 shown in FIG. 2 uses the time stamp based on the clock input from the VCO 243. A time stamp is generated by changing the advance interval to ½ and output to the phase comparator 241.

  As described above, in the first embodiment, the delay jitter of the network increases, the time stamp adoption rate in the slave node 2 decreases (time stamp adoption rate is 30%), and the clock synchronization accuracy requirement level of the slave node 2 If there is a risk of not reaching, the slave node 2 transmits a request message for increasing the transmission amount of the time packet to the master node 1, and the master node 1 side increases the transmission amount of the time stamp packet.

By increasing the number of time stamp packets transmitted from the master node 1 and increasing the number of time stamps adopted within the unit time in the slave node 2, for example, as shown in FIG. 6, the FFO value of the slave node 2 is increased. Produces results that meet expectations and eliminates the risk of falling into an unstable self-running state for a long time.
FIG. 6 is a diagram showing a change in clock synchronization accuracy according to a time stamp adoption rate.
In the figure, the horizontal axis indicates the time stamp adoption rate, and the vertical axis indicates FFO.

<Effect>
Next, the effect of Example 1 for implementing this invention is demonstrated.
In the first embodiment, when the delay jitter of the network becomes large, the adoption rate of the time stamp in the slave node is reduced, and there is a possibility that the clock synchronization accuracy required level of the slave node may not be reached, the transmission amount of the time packet in the slave node By sending a request message to the master node and increasing the number of time stamps adopted in the unit time in the slave node, network delay variation can be reduced without falling into an unstable self-running state for a long time. Since the influence can be reduced, the object of the present invention can be achieved.

  Further, in the first embodiment, when the jitter of the packet network is reduced and the adoption rate of the time stamp in the filter unit is increased, the time stamp adopted within the unit time is within the range satisfying the required clock synchronization accuracy. By reducing the number, the transmission efficiency of the packet network can be improved.

  Second Embodiment A clock synchronization system according to a second embodiment of the present invention will be described in detail with reference to the drawings.

<Configuration>
FIG. 7 is a block diagram showing another embodiment of the clock synchronization system according to the present invention.
Referring to FIG. 7, the slave node 2 uses the clock synchronization monitor 27, and the acceptance rate monitor 25 controls the request message transmitter 26 based on the monitoring result of the clock synchronization accuracy of the clock synchronization monitor 27. This is different from the first embodiment.

  The clock synchronization monitor 27 is a clock synchronization monitoring technique described in Japanese Patent Application No. 2007-239415, and uses a function of monitoring the current clock synchronization accuracy from a change in the data accumulation amount of the jitter buffer of the slave node. The clock synchronization monitor 27 further uses a function of notifying the acceptance rate monitor 25 when the clock synchronization accuracy of the slave node 2 is lower than the required accuracy.

  Whether or not the adoption rate monitor 25 of the first embodiment should increase the transmission amount of the time stamp packet based on the theoretical relationship (or experience value) between the time stamp acceptance rate and the clock synchronization accuracy change as shown in FIG. However, the adoption rate monitor 25 according to the second embodiment of the present invention uses the measurement result of the clock synchronization accuracy in the clock synchronization monitor 27 to determine whether or not to increase the transmission amount of the time stamp packet. And the request message transmitter 26 is notified of the result.

  Furthermore, the adoption rate monitor 25 according to the second embodiment of the present invention, when the measurement result of the clock synchronization accuracy of the slave node 2 is high, in order to improve the transmission efficiency of the packet network 3, It is also possible to notify the request message transmitter 26 so as to reduce the transmission amount. In that case, the request message transmitter 26 generates and transmits to the master node 1 a request message addressing information indicating that the amount of transmission of the time stamp packet is reduced. When the packet transmission amount controller 13 of the master node 1 receives the corresponding request message, it controls the time stamp packet generator 11 of the master node 1 so as to reduce the transmission amount of the time stamp packet.

<Operation>
The slave node 2 adjusts the time stamp packet amount based on the clock synchronization monitoring function and the actual evaluation result of the time stamp adoption rate. For example, if the clock synchronization accuracy and the time stamp adoption rate are higher than a certain threshold, the master node 1 is requested to reduce the amount of time stamp packet transmission in order to improve transmission efficiency. Conversely, if the clock synchronization accuracy and the time stamp adoption rate are higher than a certain threshold, the master node 2 is requested to increase the amount of time stamp packet transmission.

  Specifically, the clock synchronization monitor 27 of the slave node 2 monitors the FFO value of the clock f2 generated by the PLL, and passes the result to the acceptance rate monitor 25. The acceptance rate monitoring 25 controls the request message transmitter 26 based on the clock accuracy measurement result received from the clock synchronization monitor 27. For example, when the clock accuracy does not satisfy the required accuracy, a request message for increasing the amount of time stamp packet transmission is transmitted to the master node 1, and conversely, the clock synchronization accuracy satisfies the required accuracy, and the time of the jitter filter 23 If the stamp adoption rate is also high, a request message for reducing the amount of time stamp packet transmission is transmitted to the master node 1 in order to improve the transmission band utilization efficiency.

The master node 1 receives the request message from the slave node 2 and adjusts the transmission amount of the time stamp packet in the time stamp packet generator 11 as requested by the slave node 2.
Specifically, when a request message for increasing the time stamp packet transmission amount is received, the packet transmission amount controller 13 sets the time stamp packet transmission amount N within the unit time in the time stamp packet generator 11 to be large. Conversely, when a request message for reducing the amount of time stamp packet transmission is received, the packet transmission amount controller 13 sets N small.

<Effect>
Next, effects of the second embodiment according to the present invention will be described.
As in the first clock synchronization system, the second embodiment according to the present invention does not obtain the relationship between the time stamp acceptance rate and the change in clock synchronization accuracy based on the theoretical value and the empirical value, but measures the clock synchronization accuracy. By determining whether or not the number of time stamps adopted by the slave node should be increased based on the result, the reliability of the clock synchronization accuracy of the slave node is increased and unstable compared to the first clock synchronization system. Since the possibility of eliminating the danger of falling into a free-running state for a long time is also increased, the object of the present invention can be achieved.

  Also, in the second embodiment according to the present invention, when the packet network jitter is small and the time stamp adoption rate in the filter is high, the measurement result of the clock synchronization accuracy is within a range that satisfies the required clock synchronization accuracy. By reducing the number of time stamps adopted within a unit time, the transmission efficiency of the packet network can be improved.

  A third embodiment of the clock synchronization system according to the present invention will be described in detail with reference to the drawings.

<Configuration>
FIG. 8 is a block diagram showing another embodiment of the clock synchronization system according to the present invention.
In the figure, the master node 1 uses a network monitor 14 having a function of monitoring the jitter change of the packet network 3, and the slave node 2 uses an acceptance rate monitor 25, a request message transmitter 26, a clock synchronization monitor 27, and the like. It differs from Example 1 and Example 2 by the point which does not need to have.

<Operation>
The network monitor 14 monitors a change in the jitter of the packet network 3, and when the jitter becomes large, notifies the packet transmission amount controller 13 to control to increase the time stamp packet transmission amount.
Alternatively, the amount of time stamp packet transmission is adjusted by estimating that the jitter of the packet network 3 is changed. For example, when the link between the master node 1 and the slave node 2 in the packet network 3 is switched and packets are concentrated on the transmission link after the switching, the jitter of the time stamp packet transmitted on the corresponding link may increase. is there. When such link switching or the like is detected from some information, the network monitor 14 notifies the packet transmission amount controller 13 to adjust the time stamp packet transmission amount.

The network monitor 14 is not owned by the master node 1 but may be used by the slave node 2. For example, when the network monitor 14 is used in the slave node 2, it is necessary to use the acceptance rate monitor 25 and the request message transmitter 26 of the slave node 2 as in the first or second embodiment.
The acceptance rate monitor 25 and the request message transmitter 26 generate a request message for controlling the transmission amount of the time stamp packet of the master node 1 based on the prediction result of the jitter change of the packet network 3 in the network monitor 14. To the master node 1.

<Effect>
Next, effects of the third embodiment according to the present invention will be described.
In the third embodiment, the master node does not increase the transmission amount of the time stamp packet to the master node based on the deterioration of the time stamp adoption rate and the clock synchronization accuracy as in the first and second clock synchronization systems. When the jitter change of the packet network 3 is monitored and the jitter becomes large, the risk of the slave node falling into an unstable self-running state for a long time is eliminated by increasing the transmission amount of the time stamp packet. The object of the invention can be achieved.

[Description of effects]
According to the present embodiment, when the jitter of the packet network becomes large, when the adoption rate of the time stamp in the filter device becomes low, the clock of the slave node becomes unstable by increasing the number of time stamp packets transmitted by the master node. Since it is possible to eliminate the risk of falling into a free-running state for a long time, it is possible to realize clock synchronization that operates stably even in an actual field.

  Further, according to the present embodiment, the time stamp adopted within the unit time is provided as long as the jitter of the packet network is reduced, the time stamp adoption rate in the filter device is high, and the required clock synchronization accuracy is satisfied. By reducing the number of packets, the transmission efficiency of the packet network can be improved.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.

Here, among Patent Documents 1 to 5, Patent Documents 3 and 5 close to the present invention are compared with the present invention.
First, the invention described in Patent Document 3 is compared with the present invention.
The invention described in Patent Document 3 is different from the present invention in the problem to be solved. The invention described in Patent Document 3 considers “fluctuation in the transmission processing time of the master side timing packet” as a problem, while the present invention “is the adoption rate of the timing packet on the slave side due to jitter fluctuation in the network”. It is different in that it considers "variation" as a problem. The fluctuation of the packet transmission processing time on the master side is so small as to be negligible as compared with the jitter of the network, and it is understood that the effect of the invention described in Patent Document 3 is practically much smaller than that of the present invention.

  Specifically, the invention described in Patent Document 3 is different from the present invention in the configuration of the packet transmission amount controller on the master side, the jitter filter device on the slave side, the adoption rate monitor, and the request message transmitter. The packet transmission amount controller on the master side adjusts the transmission packet amount based on the adoption rate of the slave node. The feature of the jitter filter on the slave side filters the time stamp whose jitter is larger than the threshold. Not only calculate the acceptance rate of timestamp packets with low jitter: The feature of the acceptance rate monitor is to monitor the acceptance rate of the jitter filter, and if the acceptance rate is below a certain threshold, the timestamp packet Instructing to generate a request message for increasing the transmission amount of the message: The characteristics of the request message transmitter differ by generating a request message and transmitting it to the master side.

The difference between the invention combining the invention described in Patent Document 3 and the invention described in Patent Document 5 and the present invention The invention described in Patent Document 5 is a clock synchronization method for absorbing jitter fluctuations in a network. The function of the jitter filter device is similar to the present invention at first glance. The invention described in Patent Document 5 calculates the jitter difference cumulative value at regular intervals, and does not count packets whose jitter is greater than the threshold. This is a function of a general jitter filter device, and is an implementation method equivalent to the invention taken up as a related technique in the present invention, and corresponds to a related technique of the present invention.

In addition, when the invention described in Patent Document 5 and the invention described in Patent Document 3 are combined, the number of discarded time stamp packets is increased only on the transmission side as in the invention described in Patent Document 3. Therefore, the transmission amount of the timing packet does not increase compared to before discarding.
In other words, even if the invention described in Patent Document 3 and the invention described in Patent Document 5 are combined, if the network jitter increases, the adoption rate of the timing packet on the slave side is likely to be very low. It is understood that it is impossible to cope with a network whose jitter is larger than the threshold value.

  As described above, the inventions described in Patent Documents 3 and 5 are different from the present invention in the purpose, configuration, and operation effect.

1 is a block diagram showing an embodiment of a clock synchronization system according to the present invention. It is an example of a block diagram of the PLL shown in FIG. It is a figure which shows the change of the clock synchronization precision by the time stamp adoption rate used for the clock synchronization system shown in FIG. It is a figure which shows the relationship between the adoption rate of the time stamp packet used for the clock synchronous system shown in FIG. 1, and time. It is an example of the flow of the clock synchronization method which concerns on this invention. It is a figure which shows the change of the clock synchronization precision by the time stamp adoption rate. It is a block diagram which shows the other Example of the clock synchronization system which concerns on this invention. It is a block diagram which shows the other Example of the clock synchronization system which concerns on this invention. It is a block diagram of a time stamp system. It is a figure which shows the relationship between the reproduction clock frequency by the technique relevant to this invention, and time. 1 is a block diagram of a clock synchronization system related to the present invention. FIG. 12 is a diagram illustrating a relationship between the number of packets and jitter in the clock synchronization system illustrated in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Master node 2 Slave node 3 Packet network 11 Time stamp packet generator 12 Packet transmitter / receiver 13 Packet transmission amount controller 21 Packet transmitter / receiver 22 Time stamp extractor 23 Jitter filter 24 PLL
25 Acceptance rate monitor 26 Request message transmitter

Claims (52)

A clock synchronization system that synchronizes the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node,
The master node is
A time stamp packet generating means for generating a time stamp packet;
Packet transmission amount control means for controlling the number of time stamp packets to be generated;
With
The slave node is
Jitter filter means for filtering time stamps with jitter greater than a threshold;
A request message generating means for generating a request message for controlling a transmission amount of a time stamp packet of the master node and transmitting the request message to the master node;
A clock synchronization system comprising: The master node time stamp packet generating means includes:
2. The clock synchronization system according to claim 1, wherein when the packet transmission amount is N (N is a natural number) times as requested by the packet transmission amount control means, the payload size is set to 1 / N. The time stamp packet generating means of the master node is
2. The clock synchronization system according to claim 1, wherein when the packet transmission amount is N times as requested by the packet transmission amount control means, the increased packet does not include a payload or includes dummy data. . The packet transmission amount control means of the master node is
4. The time stamp packet generation unit is notified so as to make the packet transmission amount N times or 1 / N when receiving the request message from the slave node. The clock synchronization system described. The jitter filter means of the slave node is
5. The clock synchronization system according to claim 1, wherein time stamps having a jitter larger than a threshold value are filtered, and an acceptance rate of time stamp packets having a jitter less than the threshold value is calculated. A clock synchronization system that synchronizes the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node,
The master node is
A time stamp packet generating means for generating a time stamp packet;
Packet transmission amount control means for controlling the number of time stamp packets to be generated;
With
The slave node is
Jitter filter means for filtering time stamps with jitter greater than a threshold;
Monitoring the adoption rate of timestamp packets whose jitter in the jitter filter is less than or equal to a threshold , and when the acceptance rate is less than or equal to the threshold, generating a request message for increasing the amount of transmission of the timestamp packet, Adoption rate monitoring means to notify to send,
A clock synchronization system comprising: The slave node is
Monitoring the acceptance rate, and if the acceptance rate is higher than a threshold, the acceptance rate monitoring means for generating a request message for reducing the transmission amount of the time stamp packet and notifying the request message generation means to transmit the request message;
6. The clock synchronization system according to claim 5, further comprising: The slave node is
8. The clock synchronization system according to claim 6, wherein a threshold value of the acceptance rate is determined from a relationship between the acceptance rate and clock synchronization accuracy. The slave node is
Clock synchronization monitoring means for monitoring the clock accuracy of the PLL;
An acceptance rate monitoring means for notifying the request message generator to issue a request message for increasing the transmission amount of the time stamp packet when it is detected that the clock synchronization accuracy of the PLL does not satisfy the required accuracy;
The clock synchronization system according to claim 6 or 7, further comprising: The slave node is
Clock synchronization monitoring means for monitoring the clock accuracy of the PLL;
When it is detected that the clock synchronization accuracy of the PLL satisfies the required accuracy, the acceptance rate is monitored, and a request message for controlling the transmission amount of the time stamp packet is issued if necessary. An acceptance rate monitoring means to
The clock synchronization system according to claim 6 or 7, further comprising: The slave node is
A PLL counter means is provided for controlling the advance interval of the time stamp generated from the clock f2 of its own node to match the change of the advance interval of the time stamp value of the received time stamp packet. 10. The clock synchronization system according to 8 or 9. Using the time stamp packet sent from the master node to the slave node,
A clock synchronization system for synchronizing the clock of the slave node with the clock of the master node,
The master node is
A time stamp packet generating means for generating a time stamp packet;
Packet transmission amount control means for controlling the number of time stamp packets to be generated;
Network monitoring means for monitoring jitter changes in the packet network;
With
The clock synchronization system according to claim 1, wherein the slave node includes jitter filter means for filtering a time stamp having a jitter larger than a threshold value. The time stamp packet generating means of the master node is
13. The clock synchronization system according to claim 12, wherein when the packet transmission amount becomes N times as requested by the packet transmission amount control means, the payload size is set to 1 / N. The time stamp packet generating means of the master node is
13. The clock according to claim 12, wherein when the packet transmission amount is increased N times by a request from the packet transmission amount control means, the increased packet does not include a payload or includes dummy data. Synchronous system. The packet transmission amount control means of the master node is
15. When receiving a notification from the network monitoring unit, the time stamp packet generating unit is notified so as to make the packet transmission amount N times or 1 / N. Clock synchronization system. The network monitoring means of the master node is
The network jitter is calculated based on the RTT (Round-Trip Time) measurement result between each of the master node and the slave node, and information indicating whether or not the measurement result exceeds the threshold is the packet transmission amount. 16. The clock synchronization system according to claim 15, wherein the control means is notified. The network monitoring means of the master node is
16. The clock synchronization system according to claim 15, wherein when information on a logical link switching between the master node and the slave node is received, the information is notified to the packet transmission amount control means. A clock synchronization method for synchronizing a clock of the slave node with a clock of the master node using a time stamp packet transmitted from a master node to a slave node,
The master node is
Generate a time stamp packet,
Control the number of timestamp packets to generate,
The slave node is
Filter timestamps with jitter greater than the threshold,
Said generating a request message for controlling the transmission amount of time stamp packet of the master node, transmits to the master node, the clock synchronization method characterized by. 19. The clock synchronization method according to claim 18 , wherein the master node sets the payload size to 1 / N when the packet transmission amount is N (N is a natural number) times as requested by the packet transmission amount control means. 19. The master node according to claim 18, wherein when the packet transmission amount is N times as requested by the packet transmission amount control means, the increased packet does not include a payload or includes dummy data. Clock synchronization method. 21. The time stamp packet generation means is notified so that the master node receives the request message from the slave node so that the packet transmission amount is N times or 1 / N. The clock synchronization method according to claim 1. The clock synchronization method according to any one of claims 18 to 21, wherein the slave node filters a time stamp whose jitter is larger than a threshold, and calculates an acceptance rate of time stamp packets whose jitter is lower than the threshold. . The slave node monitors the acceptance rate, and when the acceptance rate is less than or equal to a threshold value, generates a request message for increasing the amount of transmission of the time stamp packet and notifies the request message generation unit to transmit the request message. 23. The clock synchronization method according to claim 22, wherein: A clock synchronization method for synchronizing a clock of the slave node with a clock of the master node using a time stamp packet transmitted from a master node to a slave node,
The master node is
Generate a time stamp packet,
Control the number of timestamp packets to generate,
The slave node is
Filter timestamps with jitter greater than the threshold ,
Jitter monitor the selection rate of the following time stamp packet threshold, if the selection rate is less than or equal to the threshold, and generates a request message for increasing the transmission amount of the time stamp packet, and transmits the request message generating unit, it A clock synchronization method characterized by the above. The clock synchronization method according to claim 23 or 24 , wherein the slave node determines a threshold value of the acceptance rate from a relationship between the acceptance rate and clock synchronization accuracy. The slave node is
Monitor the clock accuracy of the PLL,
24. When detecting that the clock synchronization accuracy of the PLL does not satisfy the required accuracy, the request message generator is notified so as to issue a request message for increasing the amount of transmission of the time stamp packet. 24. The clock synchronization method according to 24. The slave node is
Monitor the clock accuracy of the PLL,
When it is detected that the clock synchronization accuracy of the PLL satisfies the required accuracy, the acceptance rate is monitored, and a request message for controlling the transmission amount of the time stamp packet is issued if necessary. 25. The clock synchronization method according to claim 23 or 24, wherein: The slave node controls the advance interval of the time stamp generated from the clock f2 of the own node so as to match the change of the advance interval of the time stamp value of the received time stamp packet. 27. The clock synchronization method according to 26. A clock synchronization method for synchronizing a clock of the slave node with a clock of the master node using a time stamp packet transmitted from a master node to a slave node,
The master node is
Generate a time stamp packet,
Control the number of timestamp packets to generate,
Monitor jitter changes in the packet network,
The slave node is
A clock synchronization method comprising filtering a time stamp having a jitter larger than a threshold value. 30. The clock synchronization method according to claim 29 , wherein the master node sets the payload size to 1 / N when the packet transmission amount is N times as requested by the packet transmission amount control means. 2. The master node according to claim 1, wherein when the packet transmission amount is increased N times by a request from the packet transmission amount control means, the increased packet does not include a payload or includes dummy data. 29. The clock synchronization method according to 29. 32. When receiving the notification from the network monitoring unit , the master node notifies the time stamp packet generation unit so that the packet transmission amount is N times or 1 / N. The clock synchronization method according to item 1. The master node calculates network jitter based on the RTT measurement results between the master node and the slave node each time, and information on whether the measurement results exceed a threshold value is the packet transmission amount control means. 33. The clock synchronization method according to claim 32, further comprising: The master node, when receiving information on occurrence of logical link switching between the master node and the slave node, notifies the packet transmission amount control means of the information. Clock synchronization method. A program for causing a computer to execute a process of synchronizing the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node,
The master node is connected to the computer.
A time stamp packet generating process for generating a time stamp packet;
A packet transmission amount control process for controlling the number of time stamp packets to be generated;
And execute
The slave node is
Jitter filtering that filters timestamps with jitter greater than a threshold;
A request message generation process for generating a request message for controlling a transmission amount of a time stamp packet of the master node and transmitting the request message to the master node;
A program characterized by having executed. Time stamp packet generation means of the master node is connected to the computer.
36. The program according to claim 35, wherein when the packet transmission amount is N (N is a natural number) times as requested by the packet transmission amount control means, processing for reducing the payload size to 1 / N is executed. The time stamp packet generating means of the master node is connected to the computer.
36. When the packet transmission amount becomes N times as requested by the packet transmission amount control means, the increased packet is caused to execute a process of not including a payload or including dummy data. Program. The packet transmission amount control means of the master node is connected to the computer.
38. The process of notifying the time stamp packet generating means so as to make the packet transmission amount N times or 1 / N when receiving the request message from the slave node. The program according to any one of the above. The jitter filter means of the slave node is connected to the computer.
The program according to any one of claims 35 to 38, wherein a time stamp whose jitter is larger than a threshold is filtered, and a process of calculating an acceptance rate of time stamp packets whose jitter is equal to or smaller than the threshold is executed. A program for causing a computer to execute a process of synchronizing the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node,
The master node is connected to the computer.
A time stamp packet generating process for generating a time stamp packet;
A packet transmission amount control process for controlling the number of time stamp packets to be generated;
And execute
The slave node is
Jitter filtering that filters timestamps with jitter greater than a threshold;
In the jitter filter processing, the adoption rate of time stamp packets whose jitter is less than or equal to a threshold value is monitored, and when the acceptance rate is less than or equal to the threshold value, a request message for increasing the transmission amount of the time stamp packet is generated, Acceptance rate monitoring process to notify the means to send,
A program characterized by having executed. The slave node is connected to the computer.
Monitoring the acceptance rate, and if the acceptance rate is higher than a threshold value, an acceptance rate monitoring process for generating a request message for reducing the amount of transmission of a time stamp packet and notifying the request message generating means for transmission,
40. The program according to claim 39, wherein: The slave node is connected to the computer.
42. The program according to claim 40 or 41, wherein a process for determining a threshold of the acceptance rate is executed from a relationship between the acceptance rate and clock synchronization accuracy. The slave node is connected to the computer.
A clock synchronization monitoring process for monitoring the clock accuracy of the PLL;
When it is detected that the clock synchronization accuracy of the PLL does not satisfy the required accuracy, an acceptance rate monitoring process for notifying the request message generator to issue a request message for increasing the transmission amount of the time stamp packet;
42. The program according to claim 40 or 41, wherein: The slave node is connected to the computer.
A clock synchronization monitoring process for monitoring the clock accuracy of the PLL;
When it is detected that the clock synchronization accuracy of the PLL satisfies the required accuracy, the acceptance rate is monitored, and a request message for controlling the transmission amount of the time stamp packet is issued if necessary. The acceptance rate monitoring process to
42. The program according to claim 40 or 41, wherein: The slave node is connected to the computer.
PLL counter processing for controlling the advance interval of the time stamp generated from the clock f2 of the own node to match the change of the advance interval of the time stamp value of the received time stamp packet,
44. The program according to claim 42 or 43, wherein the program is executed. A program for causing a computer to execute a process of synchronizing the clock of the slave node with the clock of the master node using a time stamp packet transmitted from the master node to the slave node,
The master node is connected to the computer.
A time stamp packet generating process for generating a time stamp packet;
A packet transmission amount control process for controlling the number of time stamp packets to be generated;
Network monitoring processing to monitor jitter changes in the packet network;
And execute
The slave node executes a jitter filter process for filtering a time stamp whose jitter is larger than a threshold value. The time stamp packet generating means of the master node is connected to the computer.
47. The program according to claim 46, wherein when the packet transmission amount is N times as requested by the packet transmission amount control means, a process for reducing the payload size to 1 / N is executed. The time stamp packet generating means of the master node is connected to the computer.
2. The process according to claim 1, wherein when the packet transmission amount is increased by N times due to a request from the packet transmission amount control means, a process is performed in which the increased packet does not include a payload or includes dummy data. 46. The program according to 46. The packet transmission amount control means of the master node is connected to the computer.
49. The process of notifying the time stamp packet generating means so as to make the packet transmission amount N times or 1 / N when receiving notification from the network monitoring means. Or 1 program. The network monitoring means of the master node is connected to the computer.
Processing for calculating network jitter based on the RTT measurement results each time between the master node and the slave node, and notifying the packet transmission amount control means of whether or not the measurement results exceed a threshold value The program according to claim 49, wherein the program is executed. The network monitoring means of the master node is connected to the computer.
50. The information processing apparatus according to claim 49, wherein when information on a logical link switching between the master node and the slave node is received, a process for notifying the packet transmission amount control unit of the information is executed. program.   52. A recording medium on which the program according to any one of claims 35 to 51 is recorded.

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