JP2516443B2 - Layer 1 frame protection method - Google Patents

Description

The present invention relates to a method of protecting a layer 1 frame in an S interface subscriber circuit, and a layer 1 frame protection method capable of preventing loss of synchronization with a terminal due to disturbance of a system clock. In order to provide a high-speed clock and a highway from a duplicated clock generator in an S interface subscriber circuit that mutually converts ISDN B1 and B2 channel data between highway data and a layer 1 frame. Using the timing signal synchronized with the data, a low-speed clock is created from the signal obtained by dividing the high-speed clock through a counter through a phase synchronization circuit, and the high-speed clock and the timing signal are used for B1 and B2 channels on the highway. To create a synchronization signal that specifies the data timing of the Layer 1 for extracting the data of the B1 and B2 channels in the highway data using the synchronization control unit and the synchronizing signal and assembling the data of the B1 and B2 channels in the layer 1 frame using the low speed clock. And a control unit.

[Industrial applications]

The present invention relates to a method for protecting a layer 1 frame in an S interface subscriber circuit, and particularly to a layer 1 for preventing loss of synchronization with a terminal when the system clock is disturbed.
The present invention relates to a frame protection method.

The S interface subscriber circuit is provided between the time-division electronic switching system and the ISDN terminal and serves to connect them.

In the S interface subscriber circuit, there is a demand for a layer 1 frame protection method that can protect the layer 1 frame by mitigating the influence of the disturbance of the system clock and prevent the loss of synchronization with the terminal.

[Conventional technology]

FIG. 3 shows an outline of an S interface subscriber circuit, and shows a system including an S interface subscriber circuit 11, a system control unit 12 and an ISDN terminal 13 in a time division electronic switching system. .

In the S interface subscriber circuit 11, I43 in CCITT
0 Communicates with the terminal 13 via the subscriber line using the AMI code defined by the recommendation.

The system control unit 12 generates a system clock composed of a 2 MHz clock (CLK1) and an 8 kHz timing signal (FC) which is synchronized with the 2 MHz clock (CLK1) to generate an S interface subscriber circuit.
It is input to the timing control unit 17 in 11. in this case,
The timing signal (FC) is synchronized with the highway (HW) data. The timing control unit 17 is equipped with a timing circuit so that the SYNC signal and 8 kHz
2MHz clock (CLK2)
It is input to the layer 1 control unit 18 together with 1). In addition, the highway package 19 is B with the highway (HW).
Sends and receives data for channels 1 and 2.

FIG. 4 shows a conventional timing circuit, which includes a SYNC generator 21 and a timing of 8 kHz cycle for extracting highway data from a system clock composed of a 2 MHz clock (CLK1) and a timing signal (FC). Is a signal
A SYNC signal is generated, a counter 22 is provided to count down a 2 MHz clock (CLK1), and an 8 kHz clock (CLK2) is generated in synchronization with a timing signal (FC).

In FIG. 3, the layer 1 control unit 18 uses the signals from the timing control unit 17 to output the B1 and B2 channel data from the highway package 19 and the layer 2 control unit 20.
The data of the D channel created in 1) is assembled into a layer 1 frame and transmitted to the terminal 13 via the subscriber line. In addition, at the time of reception, the data from the terminal 13 is received through the subscriber line, the data is disassembled, and the data of the B1 and B2 channels is transmitted through the highway package 19 to the highway (H
W), and the D channel data is sent to the layer 2 control unit 2
Send to 0.

FIG. 5 shows a layer 1 frame.
It is shown that the B1 channel and the B channel are transmitted twice each for 8 bits in one frame having a repetition period of 250 μs each consisting of bits, and the D channel is transmitted in the meantime. The layer 1 frame is generated in synchronization with a 4 kHz clock obtained by dividing the 8 kHz clock (CLK2) input from the timing control unit 17.

FIG. 6 shows the timing of the highway data. The highway data (downstream highway data DH
W, upstream highway data UHW), repeat cycle 125 μs
It consists of 32 time slot data (0kHz) TS0 to TS31 and is synchronized with the timing signal (FC).

Highway data (DHW, UHW) time slots TS0
~ TS31 is composed of 2-bit 8-bit data B0 to B7. The SYNC signal goes high corresponding to the designated time slot, which causes the layer 1 controller 18 to
Extracts B1 or B2 channel data from the highway (HW) or sends B1 or B2 channel data to the highway (HW).

Since it is necessary to synchronize the layer 1 frame in the layer 1 control unit 18 with the highway (HW) data, the layer 1 control unit 18 performs timing so as to synchronize with the timing signal (FC) from the system control unit 12. The layer 1 frame is created using the 8kHz clock (CLK2) synchronized with the signal (FC).

In the system controller 12, the 0-system clock generator 15
And a dual configuration consisting of the 1-system clock generation unit 16,
Select one of them and select 2MHz clock (CLK1) and 8kHz
The timing signal (FC) of is generated. Then, for example, if any failure occurs in the 0-system clock generation unit 15 while operating in the 0-system, the system control unit 12 detects the failure,
It is possible to switch to the 1-system clock generator 16. The same applies when a failure occurs in the 1-system clock generation unit 15 during operation in the 1-system.

[Problems to be Solved by the Invention]

Conventionally, in the system control unit 12, the clocks generated between the 0-system clock generation unit 15 and the 1-system clock generation unit 16 have not been synchronized.

Therefore, when both clock generators are switched, even if the clocks are switched instantaneously, the 2MHz clock (CL
K) and the timing signal (FC) are disturbed.

On the other hand, since the layer 1 control unit 18 uses the 8 kHz clock (CLK2) synchronized with this timing signal (FC) to assemble the frame, the timing signal (F
The disturbance of C) causes disturbance in the layer 1 frame.
In this state, the terminal 13, which receives this signal, detects the loss of frame synchronization and disconnects the communication.

In this case, it is unavoidable that data will not be guaranteed due to loss of synchronization due to clock switching.
In order to maintain the communication state, it is desirable to maintain the layer 1 frame synchronization with the terminal.

However, conventionally, when switching clocks, layer 1
No measures were taken to maintain frame synchronization.

SUMMARY OF THE INVENTION The present invention is intended to solve such a problem of the prior art, and in the S interface subscriber circuit, it is possible to prevent the loss of synchronization with the terminal due to the disturbance of the system clock, the layer 1 frame. It is intended to provide a protection scheme.

[Means for solving the problem]

The present invention uses a signal from a dual clock generator that generates a high-speed clock (CLK1) and a timing signal (FC) synchronized with highway data as shown in FIG. CLK2) and a timing control unit 17 for generating a synchronization signal (SYNC) synchronized with this timing signal (FC), and data extracted from a highway using this synchronization signal (SYNC) by a low-speed clock (CLK2). In an S interface subscriber circuit having a layer 1 control section 18 for creating a layer 1 frame by frame synchronization, the timing control section 17 has a counter 22 and a phase synchronization circuit 23. is there.

Here, the counter 22 counts down the high speed clock (CLK1), and the phase synchronization circuit 23 synchronizes the output signal of the counter 22 with the low speed clock (CLK2).
Is generated).

[Action]

In the S interface subscriber circuit, the timing control unit 17 uses the high-speed clock (CLK1) from the clock generation unit having a duplicated structure and the timing signal (FC) synchronized with the highway data, and uses the low-speed clock (CL).
K2) and a synchronizing signal (SYNC) synchronized with this timing signal (FC) are produced. Layer 1 control unit 18
Uses this synchronization signal (SYNC) to extract data from the highway and uses the extracted data as a low-speed clock (CLK2).
The function of creating a layer 1 frame by synchronizing frames is performed by.

At this time, in the present invention, the timing control unit 17 is provided with the counter 22 to count down the high speed clock (CLK1), and the phase synchronization circuit 23 synchronizes the low speed clock (CLK1) in phase with the output signal counted down from the counter 22. CLK2) is generated.

Therefore, even if the high-speed clock (CLK1) and the timing signal (FC) are disturbed due to switching of the redundant clock generator, etc., the high-speed clock (CLK1)
Disturbance-Reduced Low-Speed Clock (CLK2)
Therefore, it is possible to prevent the synchronization loss between the layer 1 control unit and the terminal due to the disturbance of the system clock.

Further, in the present invention, when the low-speed clock (CLK2) is created in the counter 22, it is asynchronous with the timing signal (FC), so that the disturbance of the low-speed clock (CLK2) based on the disturbance of the timing signal (FC) is reduced. .

〔Example〕

FIG. 2 shows an embodiment of the present invention, and shows a configuration of a timing circuit for generating a SYNC signal and an 8 kHz clock (CLK2) in the timing control section 17 shown in FIG. . In the figure, the same elements as those in FIG. 4 are indicated by the same numbers, and 23 is a phase synchronization circuit (PL
O).

In FIG. 2, the SYNC creating unit 21 receives a system clock composed of a 2 MHz clock (CLK1) and a timing signal (FC) from a system control unit (not shown), and then SY
Generate NC signal. The SYNC signal has a cycle of 8 kHz and is used to extract a signal of a designated time slot from highway (HW) data.

Further, the counter 22 receives the 2 MHz clock (CLK1), counts it down, and generates an 8 kHz signal.

The phase synchronization circuit 23 receives the 8 kHz signal from the counter 22 and generates an 8 kHz clock (CLK2) that is phase-locked with the signal.

The SYNC signal generated in this way and the 8kHz clock (CL
The K2) and the 2 MHz clock (CLK1) are used by the layer 1 control unit (not shown) to create the layer 1 frame as described above.

Clock disturbance in the system controller occurs in both the 2MHz clock (CLK1) and the timing signal (FC).
2 MHz clock (CLK1) in the conventional timing circuit
Since it was synchronized with the timing signal (FC) when the 8 kHz clock (CLK2) was created by counting down from, the disturbance in the timing signal (FC) causes the 8 kHz clock (CLK2) to be disturbed. As a result, the layer 1 frame created by the layer 1 control unit is disturbed, so that the terminal detects out of synchronization.

On the other hand, in the present invention, the phase synchronization circuit 23 is provided after the counter 22 in the timing circuit, and the
Since the Hz clock (CLK2) is taken out, 2M
Disturbance mitigated 8k based on Hz clock (CLK1) disturbance
It is possible to generate the Hz clock (CLK2), and thus prevent the synchronization loss between the layer 1 control unit and the terminal due to the disturbance of the system clock.

Furthermore, in the present invention, when the 8 kHz clock (CLK2) is created in the counter 22, it is asynchronous with the timing signal (FC), so the disturbance of the 8 kHz clock (CLK2) based on the disturbance of the timing signal (FC) is reduced. .

〔The invention's effect〕

As described above, according to the present invention, in the S interface subscriber circuit, it is possible to prevent the synchronization with the terminal due to the disturbance of the system clock, so that the communication state (frame synchronization) in such a case can be prevented.
Can be protected.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an outline of an S interface subscriber circuit, and FIG. 4 is a conventional timing. FIG. 5 is a diagram showing a circuit, FIG. 5 is a diagram showing a layer 1 frame, and FIG. 6 is a diagram showing timing of highway data. Reference numeral 17 is a timing control unit, 18 is a layer 1 control unit, 22 is a counter, and 23 is a phase synchronization circuit.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hiroyuki Ujiie 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kiyoji Miyoshi 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

(57) [Claims] 1. In an S interface subscriber circuit for converting data of ISDN B1 and B2 channels between highway data and a layer 1 frame, a high-speed clock (CLK
1) and a timing signal (F
C) and the high-speed clock (CLK1) using a counter (2
2) The low-speed clock (CLK2) is created from the signal divided by the phase-locking circuit (23), and the high-speed clock (CLK1) and the timing signal (FC) are used for the data of B1 and B2 channels in the highway. And a timing control unit (17) for generating a synchronization signal (SYNC) for designating the timing of, and extracting the data of the B1 and B2 channels in the highway data by using the synchronization signal (SYNC). A layer 1 frame protection system comprising: a layer 1 controller (18) for assembling B1 and B2 channel data in a layer 1 frame using a clock (CLK2).