CN100393014C - Apparatus and method for implementing optical monitoring channel of dense wavelength division multiplex system - Google Patents
Apparatus and method for implementing optical monitoring channel of dense wavelength division multiplex system Download PDFInfo
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- CN100393014C CN100393014C CNB021120919A CN02112091A CN100393014C CN 100393014 C CN100393014 C CN 100393014C CN B021120919 A CNB021120919 A CN B021120919A CN 02112091 A CN02112091 A CN 02112091A CN 100393014 C CN100393014 C CN 100393014C
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Abstract
The present invention discloses a realization device for a light monitoring channel of a dense wave division multiplex system, which relates to a technique for realizing light monitoring channel data high efficiency transmission under the condition of a complicated group network. The realization device comprise an HDLC interface circuit, a TSA circuit, a framing circuit, a clock extraction circuit and a control unit, wherein the HDLC interface circuit is used for finishing data interfaces of a network element control plate and a spending plate; the TSA circuit is used for finishing multiplex processing to output data received by the HDLC interface circuit and demultiplex processing to output data received by the clock extraction circuit; the framing circuit is used for finishing the data framing processing of the output data of a time slot multiplex/demultiplex circuit; the clock extraction circuit is used for finishing the extraction of 8K frame synchronous pulses and the extraction of clock signals when data on a light path is received; the control unit provides 2MHz required clocks for the HDLC interface circuit, the TSA circuit and the framing circuit when the data is sent. When the data is received, the phase position adjustment of the 2MHz required clocks and 8K frame synchronous pulses outputted by the clock extraction circuit is carried out. The problems of the 2MHz required clocks in the complicated group network are solved. The present invention also contains the realization method for a light monitoring channel of a dense wave division multiplex system.
Description
Technical field
The present invention relates to the realization of optical monitoring channel of dense wavelength division multiplex system in the optical transmission field, particularly a kind of implement device and method that under complicated networking situation, realizes the transmission of Optical Supervisory Channel data efficient.
Background technology
Optical Supervisory Channel is the carrier of monitor message and service message and other various expenses in the dense wavelength division multiplexing system, the data format of Optical Supervisory Channel be speed be E1 signal (referring to post and telecommunications technical stipulation YDN 120-1999, " requirement of light wavelength-multiplexing systems general technical ") each node in network of 2Mbit/S all need to data carry out light/electric conversion, data demultiplexing, exchanges data, data are compound and electric/light conversion.The mode that generally adopts is to utilize circuit switching at each node data to be handled at present, use for reference the clock processing mode of SDH system, the used clock of deal with data adopts the synchronous mode of the whole network, be a host node to be arranged in the network as system's master clock, adopt the local oscillator clock on this plate, all the other respectively extract the clock information of upstream node as this nodal clock from node from light path.When the upstream node of optical fiber generation fracture or certain node breaks down, the clock information of downstream node will be lost, must take certain measure to guarantee that all nodes of downstream still can operate as normal like this, the measure of taking at present is then to change the downstream nodal clock into the local oscillator clock when finding upstream clock information dropout, guarantee that all nodes of downstream still can operate as normal, as shown in Figure 1: node 1 is a host node, other node is master clock with a to taking out clock, when 3,4 fractures of node, 4 Dot Clocks are cut to master clock.This mode is very suitable for the networking of strand type.
Along with the complexity of optical-fiber network networking improves day by day, looped network, ring+link network, the two tangent nets of ring and more complicated mesh will occur in succession, then can not satisfy the existence requirement of network like this for above-mentioned clock the whole network method of synchronization of taking.When occurring the situation of many places fibercuts in the network, the situation that then may in network, exist a plurality of local oscillator clocks to work simultaneously according to above-mentioned processing method, like this because the factors such as shake of frequency difference between the clock and circuit make each node that sliding frame and loss of data phenomenon can take place when deal with data, to cause the collapse of network Optical Supervisory Channel when serious, as shown in Figure 2: node 5 is a host node, and other is master clock with a to taking out clock from node.When 1,2 of nodes and 5,6 fractures of node, 3 local oscillator master clocks can appear, and be respectively node 2,5 and 6.In the monitor channel data, most of expense, require than higher as the error rate to data such as ECC data, transparent subscriber channel data, and a plurality of master clocks appear during when fibercuts in taking the synchronous system of the whole network, the data error performance of system is with variation, and the transfer of data that causes the error rate is had relatively high expectations can not satisfy system requirements.
For the SDH network, because SDH itself has the mechanism that a cover clock is handled, the hand of a clock adjustment can be satisfied the synchronous requirement of the whole network of SDH network during employing.But for Optical Supervisory Channel 2Mbit/S data, can not adopt a large amount of expenses to be used for clock and handle, complexity improves simultaneously.Therefore in order to satisfy the requirement of complicated networking, must solve the clock problem of Optical Supervisory Channel to Optical Supervisory Channel.
Summary of the invention
Technical problem to be solved by this invention is the existing data synchronization problems of Optical Supervisory Channel in complicated networking, improves the existence robustness of Optical Supervisory Channel in complicated networking.
Optical Supervisory Channel implement device of the present invention comprises:
High-Level Data Link Control (HDLC) interface circuit is used to finish the data-interface with network element control plate and overhead board, and receives and send data according to the HDLC data frame format;
Timeslot multiplex/demultiplexing circuit (TSA), be used to finish to receiving the demultiplexing processing that HDLC circuit dateout is carried out multiplexing process and receive clock extracted the circuit dateout, data are required to be filled in each time slot according to time slot, realize the timeslot multiplex/demultiplexing of data;
Framer circuit is used to finish the data framing processing of timeslot multiplex/demultiplexing circuit dateout;
Clock extracting circuit, the extraction of 8K frame-synchronizing impulse and the extraction of clock signal when being used to finish data on the receiving light path;
Control unit provides the 2MHz clock that needs for HDLC control interface circuit and TSA circuit and framer circuit when data send; 2MHz clock and 8K frame-synchronizing impulse to clock extracting circuit output when receiving carry out the phase place adjustment, and the 2MHz clock and the 8K frame-synchronizing impulse of needs when satisfying HDLC control interface circuit and the reception of TSA circuit is provided.
Optical monitoring channel of dense wavelength division multiplex system implementation method of the present invention comprises the transmission of carrying out synchronously and receives two processes, wherein:
Process of transmitting:
1) when light path on the expense sends,, puts into the zone buffer memory that the memory block is distributed by the overhead data of HDLC control interface circuit reception from network element control plate and overhead board;
2) timeslot multiplex/demultiplexing circuit (TSA) is mapped to the data time slot corresponding relation according to the rules that the memory block receives in the 2Mb/s signal, realizes timeslot multiplex;
3) handle the 2Mb/s signal data of exporting the back by timeslot multiplex/demultiplexing circuit (TSA) and be sent to framer circuit, the framing that the clock that framer circuit provides by control unit carries out standard E1 signal to data is handled, add frame synchronizing signal, be output as the E1 signal of standard; Then through exporting after encoding process, the electricity/light conversion.
Receiving course:
At first pass through light/electric conversion when 1) receiving, then by clock extracting circuit from receiving from 8K frame synchronizing signal and the clock signal of extracting E1 the overhead data on the light path, restore data signal simultaneously; Export data recovered to timeslot multiplex/demultiplexing circuit (TSA), simultaneously the 8K frame synchronizing signal extracted and clock signal are delivered to control unit and carry out Phase Processing;
2) by control unit clock extracting circuit is extracted 8K frame-synchronizing impulse signal and the clock signal obtain and carry out Phase Processing, meet clock and the frame synchronizing signal that phase place requires for HDLC control interface circuit and timeslot multiplex/demultiplexing circuit (TSA) provide;
3) timeslot multiplex/demultiplexing circuit (TSA) is sent to the HDLC control interface circuit according to the time slot corresponding relation after with the various overhead data demultiplexings in the E1 signal;
4) by the HDLC control interface circuit with the data that receive again according to being sent to network element control plate and overhead board after the packing of HDLC frame structure.
The present invention is applicable to various networking modes by having solved the clock problem of optical monitoring channel of dense wavelength division multiplex system in complicated networking at the multiple mechanism of taking the packet storage to transmit on the Optical Supervisory Channel plate.
Description of drawings
Fig. 1 is that chain networking switches schematic diagram at the clock that fracture takes place circuit optical fiber.
Fig. 2 is the schematic diagram that many places fiber segment fracture appears in two ring phase cut type networks.
Fig. 3 is the implement device block diagram of Optical Supervisory Channel of the present invention.
Fig. 4 is HDLC control interface circuit and the main outer signal schematic diagram of timeslot multiplex/demultiplexing circuits needed among Fig. 3.
Fig. 5 is the one-tenth Frame processing of process of transmitting and the Clock Extraction schematic diagram of receiving course.
Embodiment
The present invention will be further described below in conjunction with drawings and Examples.
Fig. 1, Fig. 2 have done explanation in the background technology part.
Fig. 3 is the implement device block diagram of Optical Supervisory Channel of the present invention:
High-Level Data Link Control interface circuit 301 is used to finish the data-interface with network element control plate and overhead board, and receives and send data according to the HDLC data frame format;
Timeslot multiplex/demultiplexing circuit 302, be used to finish to receiving the demultiplexing processing that HDLC interface circuit 301 dateouts are carried out multiplexing process and receive clock 304 extracted the circuit dateout, data are required to be filled in each time slot according to time slot, realize the timeslot multiplex/demultiplexing of data;
Below in conjunction with Fig. 4, Fig. 5 method of the present invention is described further:
The various expenses of handling on the Optical Supervisory Channel link to each other with network element control plate, overhead board by the HDLC control interface circuit in the device of the present invention.The needed clock of network element control plate and overhead board is provided by device of the present invention.When light path on the expense sent, device of the present invention received overhead data from network element control plate and overhead board by the HDLC control interface circuit, the memory block that the deposit data that receives is being distributed;
The data that timeslot multiplex/demultiplexing circuit (TSA) receives the HDLC control interface circuit by data/address bus are read from the memory block and the mapping of time slot corresponding relation is according to the rules carried out multiplexing process with overhead data, output 2Mb/s signal;
Be sent to the transmission framer circuit by the 2Mb/s signal data after the TSA multiplexing process, the framing that the clock that framer circuit provides by control unit carries out standard E1 signal to data is handled, and adds the Frame synchronizing signal, is output as the E1 signal of standard; Then through exporting after encoding process, the electricity/light conversion;
At first pass through light/electric conversion during reception, then by clock extracting circuit from receiving from extracting E1 frame synchronizing signal and clock signal the overhead data on the light path, by the extraction algorithm extraction 8K frame-synchronizing impulse signal of special chip, simultaneously data are recovered according to frame synchronizing signal.Export data recovered to timeslot multiplex/demultiplexing circuit (TSA), simultaneously the 8K frame synchronizing signal extracted and clock signal are delivered to control unit and carry out Phase Processing;
Extract the 8K frame-synchronizing impulse signal and the clock signal that obtain by clock extracting circuit and be sent to control unit, do to offer HDLC control interface circuit and timeslot multiplex/demultiplexing circuit after delay or straight-through the processing;
Be sent to HDLC control interface circuit according to the time slot corresponding relation after with the various overhead data demultiplexings in the E1 signal by timeslot multiplex/demultiplexing circuit;
By the HDLC control interface circuit data that receive are sent to network element control plate and overhead board after according to the packing of HDLC Frame structure to finish transfer of data.
Can be after software be finished HDLC control interface circuit and framing special chip initial work during specific implementation, handle tranmitting data register by control unit and provide node master clock for network element control plate and overhead board.HDLC control interface circuit in apparatus of the present invention receives and comes from monitor message data and the transparent subscriber channel data that network element control plate and overhead board are sent here, and overhead data is put into separately data storage buffer according to monitor message data and transparent subscriber channel data.Wherein T-CLOCK and R-CLOCK are provided by control unit, and T-DATA represents to be sent to the data wire of network element control plate or overhead board, and R-DATA represents the data wire from network element control plate or overhead board;
According to route data according to the rules timeslot multiplex after are sent to framer circuit to TSA with data to TSA or B by A.Wherein T-CLOCK and T-SYNC and R-CLOCK and R-SYNC are provided by control unit, and the data wire of Frame circuit was sent in TSA output when T-DATA represented to send, and had the data wire of Frame circuit when R-DATA represents to receive of one's own;
Utilize the framing treatment circuit with data according to E1 signal framing, export after adding frame synchronizing signal, as shown in Figure 5.Needed clock is provided through control section by local clock.Be output as the E1 signal of standard, then through exporting after encoding process, the electricity/light conversion;
During reception with the data that receive on the light path at first through exporting clock extracting circuit to after light/electric conversion, the decoding.Clock extracting circuit extracts frame-synchronizing impulse, is used for the time slot location, extracts output signal clock and data recovered simultaneously, and clock, frame-synchronizing impulse signal and the dateout of handling back output through clock extracting circuit are synchronous.Data recovered directly is sent to the TSA circuit, and clock and Frame synchronizing signal are sent to control unit and handle;
Control unit to the clock of Clock Extraction module output and frame synchronizing signal according to TSA when the demultiplexing and the data clock phase place of HDLC control interface circuit when receiving require clock and Frame synchronizing signal are handled, the phase relation of adjusting to data clock meets the requirements;
TSA carries out demultiplexing with the data that the receive multiplexing corresponding relation of time slot when sending, and various different expenses are sent to different HDLC control interface circuit.The demultiplexing of this moment is to receive processing according to the clock and the frame-synchronizing impulse data signal that receive, and data and clock itself are synchronous, do not need extra Synchronous Processing;
The HDLC control interface circuit receives after the data of sending here behind the TSA demultiplexing different overhead datas are repacked and is sent to corresponding net element control board and overhead board separately.This processing procedure has been passed through the process that data are repacked, and does not therefore need Synchronous Processing, and the data that send to network element control plate and overhead board through HDLC are synchronous with the node master clock that is sent to network element control plate and overhead board.Avoided the synchronous requirement of the whole network that in circuit switching, exists, but each node utilizes this nodal clock to send, utilize and extract clock and receive data, transmit deal with data, solve the clock synchronization issue under the complicated networking situation by storage.
Claims (2)
1. optical monitoring channel of dense wavelength division multiplex system implement device comprises:
High-Level Data Link Control interface circuit HDLC (301) is used to finish the data-interface with network element control plate and overhead board, and receives and send data according to the HDLC data frame format;
Timeslot multiplex/demultiplexing circuit (302), be used to finish to receiving the demultiplexing processing that High-Level Data Link Control interface circuit (301) dateout is carried out multiplexing process and receive clock extracted circuit (304) dateout, data are required to be filled in each time slot according to time slot, realize the timeslot multiplex/demultiplexing of data;
Framer circuit (303) is used to finish the data framing processing of timeslot multiplex/demultiplexing circuit dateout;
Clock extracting circuit (304), the extraction of 8K frame-synchronizing impulse and the extraction of clock signal when being used to finish data on the receiving light path;
Control unit (305) is the 2MHz clock that High-Level Data Link Control interface circuit (301) and timeslot multiplex/demultiplexing circuit (302) and framer circuit (303) provide to be needed when data send; 2MHz clock and 8K frame-synchronizing impulse to clock extracting circuit (304) output when receiving carry out the phase place adjustment, and the 2MHz clock and the 8K frame-synchronizing impulse of needs when satisfying High-Level Data Link Control interface circuit (301) and timeslot multiplex/demultiplexing circuit (302) reception is provided.
2. the optical monitoring channel of dense wavelength division multiplex system implementation method comprises the transmission of carrying out synchronously and receives two processes, and wherein process of transmitting comprises:
1) when light path on the expense sends,, puts into the zone buffer memory that the memory block is distributed by the overhead data of High-Level Data Link Control interface circuit HDLC reception from network element control plate and overhead board;
2) timeslot multiplex/demultiplexing circuit is mapped to the data time slot corresponding relation according to the rules that the memory block receives in the 2Mb/s signal, realizes timeslot multiplex;
3) be sent to framer circuit by the 2Mb/s signal data of exporting after timeslot multiplex/demultiplexing processing of circuit, the framing that the clock that framer circuit provides by control unit carries out standard E1 signal to data is handled, and adds frame synchronizing signal, is output as the E1 signal of standard; Then through exporting after encoding process, the electricity/light conversion;
Receiving course comprises:
At first pass through light/electric conversion when 1) receiving, then by clock extracting circuit from receiving from 8K frame synchronizing signal and the clock signal of extracting E1 the overhead data on the light path, restore data signal simultaneously; Export data recovered to timeslot multiplex/demultiplexing circuit, simultaneously the 8K frame synchronizing signal extracted and clock signal are delivered to control unit and carry out Phase Processing;
2) by control unit clock extracting circuit is extracted 8K frame-synchronizing impulse signal and the clock signal obtain and carry out Phase Processing, meet clock and the frame synchronizing signal that phase place requires for HDLC control interface circuit and timeslot multiplex/demultiplexing circuit provide;
3) timeslot multiplex/demultiplexing circuit is sent to the HDLC control interface circuit according to the time slot corresponding relation after with the various overhead data demultiplexings in the E1 signal;
4) by the HDLC control interface circuit with the data that receive again according to being sent to network element control plate and overhead board after the packing of HDLC frame structure.
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2006012771A1 (en) * | 2004-08-02 | 2006-02-09 | Zte Corporation | A multi-channel hdlc controller |
| CN101127577B (en) * | 2006-08-14 | 2012-05-23 | 中兴通讯股份有限公司 | A device and method for using transmission monitoring information of dense wave division multiplexing device |
| US7769256B2 (en) | 2007-04-13 | 2010-08-03 | Futurewei Technologies, Inc. | Method and system for performance monitor for digital optical DWDM networks |
| CN101150376B (en) * | 2007-10-25 | 2012-05-23 | 中兴通讯股份有限公司 | Signal speed adjustment device |
| CN102820964B (en) * | 2012-07-12 | 2015-03-18 | 武汉滨湖电子有限责任公司 | Method for aligning multichannel data based on system synchronizing and reference channel |
| CN104243127B (en) * | 2013-11-20 | 2017-09-05 | 邦彦技术股份有限公司 | Synchronous signal transmission method and system based on PTN |
| CN104301039A (en) * | 2014-09-11 | 2015-01-21 | 广西师范大学 | Local side light transmitting and receiving device based on light code division multiple access |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1298238A (en) * | 1999-12-02 | 2001-06-06 | 深圳市中兴通讯股份有限公司 | Light monitoring channel equipment, system and implementation for wavelength division multiplexing light transmission system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1298238A (en) * | 1999-12-02 | 2001-06-06 | 深圳市中兴通讯股份有限公司 | Light monitoring channel equipment, system and implementation for wavelength division multiplexing light transmission system |
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Assignee: Beijing Zhongxing Net Technology Co., Ltd. Assignor: ZTE Corporation Contract record no.: 2012990000392 Denomination of invention: Apparatus and method for implementing optical monitoring channel of dense wavelength division multiplex system Granted publication date: 20080604 License type: Exclusive License Open date: 20031231 Record date: 20120606 Assignee: Beijing Zhongxing Net Technology Co., Ltd. Assignor: ZTE Corporation Contract record no.: 2012990000392 Denomination of invention: Apparatus and method for implementing optical monitoring channel of dense wavelength division multiplex system Granted publication date: 20080604 License type: Exclusive License Open date: 20031231 Record date: 20120606 |
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