JP6434269B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6434269B2
JP6434269B2 JP2014202018A JP2014202018A JP6434269B2 JP 6434269 B2 JP6434269 B2 JP 6434269B2 JP 2014202018 A JP2014202018 A JP 2014202018A JP 2014202018 A JP2014202018 A JP 2014202018A JP 6434269 B2 JP6434269 B2 JP 6434269B2
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die pad
semiconductor chip
semiconductor device
curved
resin
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JP2016072503A (en
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真 竹沢
真 竹沢
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Ablic Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、半導体装置とその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof.

近年における電子デバイスは、電力消費の削減や環境負荷低減の為の低消費電流動作が要求されている。さらに、車載に代表される高温環境下での安定した高信頼動作が要求されている。電子デバイスの主たる構成を担う半導体デバイスも一種の抵抗と見なすことができ、電流が流れると、オン抵抗（電気を流したときの内部抵抗）に応じた熱を発生することになる。発生した熱は、半導体デバイスそのものに対してはもちろん、それを組み込んだ電子機器にもさまざまな悪影響を及ぼすことから、こうした熱による悪影響を回避するために、半導体パッケージの熱対策が不可欠となっている。半導体デバイスにおける熱は熱源となる半導体チップから最終的な熱の放出先となる空気へ放熱されるが、放熱される熱の大半は外部端子からプリント基板に熱伝導し、空気へと伝達する経路である。従って、半導体デバイスからプリント基板への放熱を促す構造が重要である。放熱性の高い半導体装置として、ダイパッドの裏面を封止樹脂から露出したものが提案されている。（例えば、特許文献１参照）。   In recent years, electronic devices are required to operate with low current consumption for reducing power consumption and environmental load. Furthermore, stable and reliable operation in a high temperature environment typified by in-vehicle is required. A semiconductor device responsible for the main configuration of an electronic device can also be regarded as a kind of resistance. When a current flows, heat corresponding to on-resistance (internal resistance when electricity is passed) is generated. The generated heat has various adverse effects not only on the semiconductor device itself but also on the electronic equipment in which it is incorporated. Therefore, in order to avoid the adverse effects of such heat, it is essential to take measures against heat from the semiconductor package. Yes. The heat in a semiconductor device is radiated from the semiconductor chip that is the heat source to the air that is the final heat release destination, but most of the radiated heat is transferred from the external terminals to the printed circuit board and transferred to the air. It is. Therefore, a structure that promotes heat dissipation from the semiconductor device to the printed circuit board is important. As a semiconductor device having high heat dissipation, a semiconductor device in which the back surface of a die pad is exposed from a sealing resin has been proposed. (For example, refer to Patent Document 1).

特開平９−１９９６３９号公報JP-A-9-199639

しかしながら、特許文献１に示したダイパッドの裏面を露出した半導体装置では、樹脂封止する際にダイパッドと金型との間に樹脂が流れ込みフラッシュバリとも呼ばれる薄バリが形成されることになる。   However, in the semiconductor device in which the back surface of the die pad shown in Patent Document 1 is exposed, when the resin is sealed, the resin flows between the die pad and the mold to form a thin burr called a flash burr.

図８は、従来構造の半導体装置の樹脂封止工程を図示している。図８（ａ）は樹脂封止前の図である。平面のダイパッド３に載置された半導体チップ２はボンディングワイヤ７を介してリード６と電気的に接続された状態で上下の金型１３，１４に収納される。その後、上下金型１３、１４で形成されるキャビティに樹脂が充填され、樹脂封止される。このとき、ダイパッド３の下面と下金型１４の上面との隙間に封止樹脂が入り込むことになる。図８（ｂ）は樹脂封止後の図であるが、平面のダイパッドの裏面にはフラッシュバリ１５が付着形成されている。このフラッシュバリが放熱性を低下させることになるが、これを除去するためには電解バリ浮かしやアルカリ無電解浸漬など技術的に高度な工程を付加する必要がある。
本発明は、上記課題に鑑み成されたもので、放熱性の高い半導体装置を得ることを目的とするものである。 FIG. 8 illustrates a resin sealing process of a semiconductor device having a conventional structure. FIG. 8A is a view before resin sealing. The semiconductor chip 2 placed on the planar die pad 3 is accommodated in the upper and lower molds 13 and 14 while being electrically connected to the lead 6 via the bonding wire 7. Thereafter, the cavities formed by the upper and lower molds 13 and 14 are filled with resin and sealed with resin. At this time, the sealing resin enters the gap between the lower surface of the die pad 3 and the upper surface of the lower mold 14. FIG. 8B is a view after resin sealing, and a flash burr 15 is formed on the back surface of a flat die pad. Although this flash burr reduces heat dissipation, it is necessary to add technically advanced processes such as electrolytic burr floating and alkali electroless dipping in order to remove this flash burr.
The present invention has been made in view of the above problems, and an object of the present invention is to obtain a semiconductor device with high heat dissipation.

上述の課題を解決するための手段は以下の通りである。
まず、半導体チップと、接着剤を介して前記半導体チップを固定するダイパッドと、前記ダイパッドの辺に向かって延在する複数のリードと、前記半導体チップと前記リードとを接続するボンディングワイヤと、前記半導体チップを封止する樹脂とを備えた半導体装置において、前記半導体チップを搭載するダイパッドが前記半導体チップに対し凹状に湾曲したダイパッドであって、前記湾曲したダイパッドの一部が前記封止樹脂から露出していることを特徴とする半導体装置とした。 Means for solving the above-described problems are as follows.
First, a semiconductor chip, a die pad for fixing the semiconductor chip via an adhesive, a plurality of leads extending toward the side of the die pad, a bonding wire for connecting the semiconductor chip and the lead, In a semiconductor device including a resin for sealing a semiconductor chip, a die pad on which the semiconductor chip is mounted is a die pad curved in a concave shape with respect to the semiconductor chip, and a part of the curved die pad is formed from the sealing resin. The semiconductor device is characterized by being exposed.

そして、リードフレームを成形する工程と、半導体チップをダイパッドに固定するダイボンド工程と、前記半導体チップと前記リードとをワイヤを介して接続するワイヤボンド工程と、前記半導体チップを樹脂封止する工程と、を備える半導体装置の製造方法において、前記リードフレームを成形する工程は平板の金属板から湾曲したダイパッドを成形する工程であることを特徴とする半導体装置の製造方法を用いた。   A step of forming a lead frame; a die bonding step of fixing a semiconductor chip to a die pad; a wire bonding step of connecting the semiconductor chip and the lead via a wire; and a step of resin-sealing the semiconductor chip. In the method of manufacturing a semiconductor device, the method of forming a lead frame is a step of forming a curved die pad from a flat metal plate.

上記手段を用いることで、半導体装置のダイパッド裏面にはフラッシュバリが付着せず、良好な放熱性を有する半導体装置とすることができる。   By using the above means, a flash burr does not adhere to the back surface of the die pad of the semiconductor device, and a semiconductor device having good heat dissipation can be obtained.

本発明の半導体装置の平面図である。It is a top view of the semiconductor device of the present invention. 本発明の半導体装置の断面図である。It is sectional drawing of the semiconductor device of this invention. 本発明の半導体装置の要部拡大断面図である。It is a principal part expanded sectional view of the semiconductor device of this invention. 本発明の半導体装置を基板実装させた状態を示す断面図である。It is sectional drawing which shows the state in which the semiconductor device of this invention was mounted on the board | substrate. 本発明の半導体装置の変形例の断面図である。It is sectional drawing of the modification of the semiconductor device of this invention. 本発明の半導体装置の工程途中における断面図である。It is sectional drawing in the middle of the process of the semiconductor device of this invention. 本発明の半導体装置の製造フローである。4 is a manufacturing flow of the semiconductor device of the present invention. 従来構造の半導体装置の工程途中における断面図である。It is sectional drawing in the middle of the process of the semiconductor device of a conventional structure.

本発明の実施形態を、図を用いて説明する。
図１に示すように、樹脂封止型の半導体装置１は、半導体チップ２と、半導体チップ２を固定するダイパッド３と、ダイパッド３の両側に延びるリード４とを備えている。半導体チップ２は、例えば、半導体基板と、半導体基板上に設けられた配線層などから構成されるものであり、ダイパッド３に接着固定されている。ダイパッド３及びリード部４は、導電性を有するものであり、例えば、Ｆｅ−Ｎｉ合金やＣｕ合金等の金属で形成されている。 Embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the resin-encapsulated semiconductor device 1 includes a semiconductor chip 2, a die pad 3 that fixes the semiconductor chip 2, and leads 4 that extend on both sides of the die pad 3. The semiconductor chip 2 is composed of, for example, a semiconductor substrate and a wiring layer provided on the semiconductor substrate, and is bonded and fixed to the die pad 3. The die pad 3 and the lead part 4 have conductivity, and are formed of a metal such as an Fe—Ni alloy or a Cu alloy, for example.

ダイパッドの周囲には複数のリード４があり、本実施形態においては、ダイパッド３の一辺側に２本、対向する他辺側に２本、計４本配置されている。そして、これらのリード４の内の１本であるリードは、吊りリード５であり、吊りリード５の基部５ａがダイパッド３に固定されている。他の３本はダイパッド３から離間したリード６であり、そのインナー部６ａが導電性を有するボンディングワイヤ７を介して半導体チップ２上のパッドと電気的に接続されている。なお、ボンディングワイヤ７には、金線や銅線が用いられる。   There are a plurality of leads 4 around the die pad. In this embodiment, two leads 4 are arranged on one side of the die pad 3 and two on the opposite side. One of the leads 4 is a suspension lead 5, and a base portion 5 a of the suspension lead 5 is fixed to the die pad 3. The other three are leads 6 separated from the die pad 3, and an inner portion 6 a thereof is electrically connected to a pad on the semiconductor chip 2 via a conductive bonding wire 7. The bonding wire 7 is a gold wire or a copper wire.

図２は、図１のＡ−Ａ‘における断面構造を示している。半導体チップ２は、ボンディングワイヤ７を介してリード６のリードインナー部６ａと電気的に接続され、リードインナー部６ａから延伸されたリードアウター部６ｂは封止樹脂８の底面および側面に露出している。   FIG. 2 shows a cross-sectional structure taken along line A-A ′ of FIG. The semiconductor chip 2 is electrically connected to the lead inner portion 6 a of the lead 6 through the bonding wire 7, and the lead outer portion 6 b extending from the lead inner portion 6 a is exposed on the bottom and side surfaces of the sealing resin 8. Yes.

ダイパッド３は、円弧状に湾曲し、半導体チップ対し凹形状を有している。ダイパッド３の上にはダイボンディングペースト１１（接着剤）を介して半導体チップ２が接着固定されている。そして、ダイボンディングペースト１１は半導体チップ２の底面だけではなく、側面にも這い上がってフィレット２２を形成する構造となっている。ダイパッド３もリード６同様、裏面の一部が封止樹脂８から部分的に露出する構造となっており、裏面からの放熱機能を有している。なお、本実施例においては、ダイパッドは紙面の左右方向に湾曲した形状としており、紙面の奥行き方向には湾曲してなく、円柱の一部を切り出したような形状としている。   The die pad 3 is curved in an arc shape and has a concave shape with respect to the semiconductor chip. On the die pad 3, the semiconductor chip 2 is bonded and fixed via a die bonding paste 11 (adhesive). The die bonding paste 11 has a structure in which the fillet 22 is formed not only on the bottom surface of the semiconductor chip 2 but also on the side surface. Like the lead 6, the die pad 3 has a structure in which a part of the back surface is partially exposed from the sealing resin 8 and has a heat radiation function from the back surface. In this embodiment, the die pad has a shape that is curved in the left-right direction on the paper surface, and is not curved in the depth direction on the paper surface, but is a shape obtained by cutting out a part of a cylinder.

図３は、本発明の半導体装置の要部拡大断面図であり、湾曲したダイパッド３および半導体チップ２を示している。半導体チップ２の底面２ａは平面であるのに対し、ダイパッド３の上面３ａは曲面である。したがって、両者の距離は一定ではなく、半導体チップ２の中央で半導体チップの底面２ａとダイパッド３の上面３ａが最も離れ、底面端部の四隅においてダイパッド３と最も近い位置になる。最も離れた箇所の隙間２３が半導体チップの総厚２ｂの１／５以下であれば、ダイボンディングペースト１１が半導体チップ２の側面にフィレット２２を形成しやすく、半導体チップが確実に固定されることになる。   FIG. 3 is an enlarged cross-sectional view of the main part of the semiconductor device of the present invention, showing a curved die pad 3 and semiconductor chip 2. The bottom surface 2a of the semiconductor chip 2 is a flat surface, whereas the upper surface 3a of the die pad 3 is a curved surface. Therefore, the distance between them is not constant, and the bottom surface 2a of the semiconductor chip and the top surface 3a of the die pad 3 are farthest at the center of the semiconductor chip 2, and are closest to the die pad 3 at the four corners of the bottom surface. If the gap 23 at the most distant place is 1/5 or less of the total thickness 2b of the semiconductor chip, the die bonding paste 11 can easily form the fillet 22 on the side surface of the semiconductor chip 2, and the semiconductor chip is securely fixed. become.

図４には、本発明の半導体装置をプリント基板に実装した際の断面図を示す。
半導体装置１の封止樹脂から露出したダイパッドやリードは、プリント基板１９上の接続端子２０と半田ペースト２１により実装接続される。この際にダイパッド３には半田ペースト２１が湾曲形状に沿う様に濡れ拡がり、フィレット２２を形成して、より確実にプリント基板に実装される。また、ダイパッド３が湾曲しているために半田ペースト２１が他の領域に無駄に拡がらないという特徴も有する。 FIG. 4 shows a cross-sectional view when the semiconductor device of the present invention is mounted on a printed circuit board.
The die pads and leads exposed from the sealing resin of the semiconductor device 1 are mounted and connected by connection terminals 20 on the printed circuit board 19 and solder paste 21. At this time, the solder paste 21 wets and spreads along the curved shape on the die pad 3 to form a fillet 22 and is more reliably mounted on the printed circuit board. In addition, since the die pad 3 is curved, the solder paste 21 does not spread unnecessarily to other areas.

図５には、本発明の半導体装置におけるダイパッドの湾曲形状を変更した際の断面図を示す。湾曲形状の度合いを変更することによって、半導体チップ底面とダイパッド底面の隙間とダイパッドの封止樹脂８の底面から露出する面積が変化するが、これらは半導体装置に求められる各種特性に応じて対応すれば良い。図５（ａ）は湾曲が小さく、曲率半径が大きい場合である。図５（ｂ）は湾曲が大きく、曲率半径が小さい場合である。   FIG. 5 shows a cross-sectional view when the curved shape of the die pad in the semiconductor device of the present invention is changed. By changing the degree of the curved shape, the gap exposed between the bottom surface of the semiconductor chip and the bottom surface of the die pad and the area exposed from the bottom surface of the sealing resin 8 of the die pad change, but these correspond to various characteristics required for the semiconductor device. It ’s fine. FIG. 5A shows a case where the curvature is small and the curvature radius is large. FIG. 5B shows a case where the curvature is large and the radius of curvature is small.

なお、これまで図示されたダイパッドは紙面の左右方向に湾曲した状態を示しているが、紙面の奥行き方向に湾曲した構造でも構わない。また、全方向に湾曲した球面形状のダイパッドとしても良い。   The die pad shown so far shows a curved state in the left-right direction of the paper surface, but a structure curved in the depth direction of the paper surface may also be used. Alternatively, a spherical die pad curved in all directions may be used.

また、図示していないが、半導体チップの底面端部の４隅を支えるように、４隅と対応するダイパッド上面に部分的に水平台を設けることで、ダイパッド上の半導体チップの固定をより確実なものとしても良い。   In addition, although not shown, by providing a horizontal base partially on the upper surface of the die pad corresponding to the four corners so as to support the four corners of the bottom end portion of the semiconductor chip, the semiconductor chip on the die pad is more securely fixed. It is good as well.

図６は、本発明の半導体装置の樹脂封止工程を図示している。図６（ａ）は樹脂封止前の図である。リードフレームを成形する工程において、平板の金属板から湾曲して成形されたダイパッド３に載置された半導体チップ２はボンディングワイヤ７を介してリード６と電気的に接続された状態で上下の金型１３，１４に収納される。上金型１３が下降して下金型１４と接触すると、ダイパッド３は下金型１４に強く押さえ付けられ、ダイパッド３の底面の一部は下金型１４の上面に沿った平面となる。上下の矢印はダイパッドにかかる力の向きを表したものである。その後、上下金型１３、１４で形成されるキャビティに樹脂が充填され、樹脂封止される。このとき、ダイパッド３の下面は下金型１４の上面を樹脂充填圧よりも強く押すため、ダイパッド３と下金型１４との間に樹脂が入り込むことはない。   FIG. 6 illustrates a resin sealing process of the semiconductor device of the present invention. FIG. 6A is a view before resin sealing. In the process of forming the lead frame, the semiconductor chip 2 placed on the die pad 3 formed by bending from a flat metal plate is electrically connected to the lead 6 via the bonding wire 7 and is used for upper and lower gold. Housed in molds 13 and 14. When the upper mold 13 is lowered and contacts the lower mold 14, the die pad 3 is strongly pressed against the lower mold 14, and a part of the bottom surface of the die pad 3 becomes a plane along the upper surface of the lower mold 14. The up and down arrows represent the direction of the force applied to the die pad. Thereafter, the cavities formed by the upper and lower molds 13 and 14 are filled with resin and sealed with resin. At this time, since the lower surface of the die pad 3 presses the upper surface of the lower mold 14 stronger than the resin filling pressure, the resin does not enter between the die pad 3 and the lower mold 14.

図６（ｂ）は樹脂封止後の図であるが、上下金型が離れると、歪んでいたダイパッドの湾曲は復帰し、元に戻ることになる。このようにして完成した半導体装置の湾曲したダイパッドの裏面にはフラッシュバリは確認できない。このように、湾曲したダイパッドを有する本発明の半導体装置ではフラッシュバリの付着もなく、放熱性の良好な半導体装置とすることが可能となる。   FIG. 6B is a view after resin sealing. When the upper and lower molds are separated from each other, the distorted curvature of the die pad is restored and returned to the original state. A flash burr cannot be confirmed on the back surface of the curved die pad of the semiconductor device thus completed. Thus, in the semiconductor device of the present invention having a curved die pad, it is possible to obtain a semiconductor device with good heat dissipation without the adhesion of flash burrs.

図７には、本発明の半導体装置の製造フローを示した。まず、Ｆｅ−Ｎｉ合金やＣｕ合金からなる平板の金属板を準備し、これを打ち抜き及びプレス加工を施して湾曲したダイパッドとアップセットされたリードを有するリードフレームを成形する。なお、湾曲したダイパッドは湾曲した台の上でリードフレームをプレス加工することによって成形できる（Ｓ１）。次いで、ダイパッド上にダイボンディングペーストを介して半導体チップを載置する（Ｓ２）。   FIG. 7 shows a manufacturing flow of the semiconductor device of the present invention. First, a flat metal plate made of Fe—Ni alloy or Cu alloy is prepared, and this is punched and pressed to form a lead frame having a curved die pad and upset leads. The curved die pad can be formed by pressing the lead frame on a curved base (S1). Next, a semiconductor chip is placed on the die pad via a die bonding paste (S2).

続くワイヤボンド工程Ｓ３は半導体チップ上の電極とリードフレームのリードとをワイヤで接続する工程である。組立検査工程Ｓ４にて外観検査をした後、ダイパッド上の半導体チップを樹脂で被覆（Ｓ５）し、その後、余分な樹脂バリ取りを行う（Ｓ６）。従来の半導体装置であれば、この後にフラッシュバリを除去する工程になるが、本発明の半導体装置の製造工程においてはその工程は不要であり、リードメッキ工程Ｓ７とリード切断工程Ｓ８を経て本発明の半導体装置が完成する。   The subsequent wire bonding step S3 is a step of connecting the electrodes on the semiconductor chip and the leads of the lead frame with wires. After the appearance inspection in the assembly inspection step S4, the semiconductor chip on the die pad is coated with a resin (S5), and then an extra resin deburring is performed (S6). In the case of a conventional semiconductor device, the flash burrs are removed thereafter. However, this step is not necessary in the manufacturing process of the semiconductor device of the present invention, and the present invention passes through a lead plating step S7 and a lead cutting step S8. This completes the semiconductor device.

なお、本発明の実施形態について図面を参照して詳述したが、具体的な構成はこの実施形態に限られるものではなく、本発明の要旨を逸脱しない範囲の設計変更等も含まれる。   Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes design changes and the like within a scope not departing from the gist of the present invention.

１ 半導体装置
２ 半導体チップ
２a 半導体チップ底面
２b 半導体チップ総厚
３ ダイパッド
３a ダイパッド底面
４ リード
５ 吊りリード
５ａ 吊りリード基部
５ｂ 吊りリードアウター部
６ リード
６ａ リードインナー部
６ｂ リードアウター部
７ ボンディングワイヤ
８ 封止樹脂
１１ ダイボンディングペースト
１３ 上金型
１４ 下金型
１５ フラッシュバリ
１９ プリント基板
２０ 接続端子
２１ 半田ペースト
２３ 隙間
Ｓ１ リードフレーム成形工程
Ｓ２ ダイボンド工程
Ｓ３ ワイヤボンド工程
Ｓ４ 組立検査工程
Ｓ５ 樹脂封止工程
Ｓ６ 樹脂バリ取り工程
Ｓ７ リードメッキ工程
Ｓ８ リード切断工程 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 2a Semiconductor chip bottom face 2b Total thickness of semiconductor chip 3 Die pad 3a Die pad bottom face 4 Lead 5 Hanging lead 5a Hanging lead base part 5b Hanging lead outer part 6 Lead 6a Lead inner part 6b Lead outer part 7 Bonding wire 8 Sealing Resin 11 Die bonding paste 13 Upper mold 14 Lower mold 15 Flash burr 19 Printed circuit board 20 Connection terminal 21 Solder paste 23 Gap S1 Lead frame forming process S2 Die bonding process S3 Wire bonding process S4 Assembly inspection process S5 Resin sealing process S6 Resin Deburring process S7 Lead plating process S8 Lead cutting process

Claims (3)

半導体チップと、
前記半導体チップを接着剤を介して固定するダイパッドと、
前記ダイパッドの辺に向かって延在する複数のリードと、
前記半導体チップと前記リードとを接続するボンディングワイヤと、
前記半導体チップを封止する樹脂とを備えた半導体装置において、
前記半導体チップを搭載するダイパッドは前記半導体チップに対し凹状に湾曲したダイパッドであって、前記半導体チップの中央は前記ダイパッドから離間しており、前記湾曲したダイパッドの裏面の一部が前記封止樹脂から露出し、前記湾曲したダイパッドの上面には、前記半導体チップの底面の４隅と対応する水平台が設けられていることを特徴とする半導体装置。 A semiconductor chip;
A die pad for fixing the semiconductor chip via an adhesive;
A plurality of leads extending toward the sides of the die pad;
A bonding wire connecting the semiconductor chip and the lead;
In a semiconductor device comprising a resin for sealing the semiconductor chip,
The die pad for mounting the semiconductor chip is a concave die pad with respect to the semiconductor chip, the center of the semiconductor chip is separated from the die pad, and a part of the back surface of the curved die pad is the sealing resin. The semiconductor device is characterized in that a horizontal base corresponding to the four corners of the bottom surface of the semiconductor chip is provided on the upper surface of the curved die pad exposed from the substrate . 前記湾曲したダイパッドが球面の一部を成していることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the curved die pad forms a part of a spherical surface. 前記湾曲したダイパッドの底面と前記半導体チップの最大離間距離が前記半導体チップの厚さの１／５以下であることを特徴とする請求項１または請求項２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a maximum separation distance between the bottom surface of the curved die pad and the semiconductor chip is 1/5 or less of a thickness of the semiconductor chip.
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