JP2003086752A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2003086752A JP2003086752A JP2001275933A JP2001275933A JP2003086752A JP 2003086752 A JP2003086752 A JP 2003086752A JP 2001275933 A JP2001275933 A JP 2001275933A JP 2001275933 A JP2001275933 A JP 2001275933A JP 2003086752 A JP2003086752 A JP 2003086752A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lead frame
- semiconductor device
- semiconductor chip
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造技術に関し、特に高放熱面実装パッケージの半
導体装置に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor device having a high heat radiation surface mounting package.
【０００２】[0002]
【従来の技術】本発明者が検討したところによれば、高
放熱面実装パッケージとしては、タブを露出させたＨＴ
ＱＦＰ（Ｈｅａｔｓｉｎｋ Ｔｈｉｎ Ｑｕａｄ Ｆｌ
ａｔＰａｃｋａｇｅ）、ＨＴＳＯＰ（Ｈｅａｔｓｉｎｋ
Ｔｈｉｎ Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａ
ｇｅ）などがある。これらのパッケージは、リードフレ
ームのタブ上に半導体チップを搭載し、このタブの裏面
を露出するように半導体チップおよびワイヤの接続部分
を封止する構造となっている。このようなパッケージ
は、実装基板に実装する際に、タブを実装基板にはんだ
付けすることで放熱性の向上を図っている。2. Description of the Related Art According to a study made by the present inventor, an HT having a tab exposed as a high heat radiation surface mount package.
QFP (Heatsink Thin Quad Fl)
atPackage), HTSOP (Heatsink)
Thin Small Outline Packa
ge) etc. These packages have a structure in which a semiconductor chip is mounted on a tab of a lead frame and a connecting portion of the semiconductor chip and a wire is sealed so that the back surface of the tab is exposed. In such a package, when mounted on a mounting board, tabs are soldered to the mounting board to improve heat dissipation.
【０００３】なお、このようなＱＦＰなどの面実装パッ
ケージに関する技術としては、たとえば２０００年７月
２８日、株式会社工業調査会発行、社団法人エレクトロ
ニクス実装学会編の「エレクトロニクス実装大事典」Ｐ
５２９〜Ｐ６４４に記載される技術などが挙げられる。As a technique relating to such a surface mounting package such as QFP, for example, "Electronics Packaging Encyclopedia" P, published by Industrial Research Institute, Inc., on July 28, 2000, edited by Japan Institute of Electronics Packaging
529 to P644, and the like.
【０００４】[0004]
【発明が解決しようとする課題】ところで、前記のよう
な高放熱面実装パッケージの技術について、本発明者が
検討した結果、以下のようなことが明らかとなった。た
とえば、前記のようなＨＴＱＦＰ、ＨＴＳＯＰにおいて
は、吸湿させて赤外線リフローなどにより実装基板に実
装する方法が用いられるが、この際に、半導体チップと
タブとの接着層が吸湿して水蒸気爆発が発生することが
ある。この場合には、たとえば図１１に示すように、接
着層１１が破壊されて空気層が形成され、この結果、垂
直応力によりタブ２１が膨れる現象が発生する。By the way, as a result of a study by the present inventor on the technique of the high heat dissipation surface mounting package as described above, the following facts have become clear. For example, in the above HTQFP and HTSOP, a method of absorbing moisture and mounting it on a mounting substrate by infrared reflow or the like is used. At this time, the adhesive layer between the semiconductor chip and the tab absorbs moisture and a steam explosion occurs. I have something to do. In this case, for example, as shown in FIG. 11, the adhesive layer 11 is destroyed to form an air layer, and as a result, the tab 21 swells due to vertical stress.
【０００５】すなわち、前記のようなＨＴＱＦＰ、ＨＴ
ＳＯＰでは、吸湿後のリフロー実装によるチップ周辺部
の樹脂剥離や、温度サイクルによる樹脂剥離により、半
導体チップとタブとの接着層に応力がかかり、タブ膨
れ、接着層破壊を生じ、放熱特性が著しく劣化すること
が考えられる。That is, the above-mentioned HTQFP, HT
In SOP, due to resin peeling around the chip due to reflow mounting after moisture absorption and resin peeling due to temperature cycle, stress is applied to the adhesive layer between the semiconductor chip and the tab, causing swelling of the tab and destruction of the adhesive layer, resulting in remarkable heat dissipation characteristics. It may deteriorate.
【０００６】そこで、本発明者は、チップを搭載するリ
ードフレームのタブに着目し、このタブの形状を工夫す
ることで、形状効果によりタブの膨れ変形を防止するこ
とが可能であることを考え付いた。Therefore, the present inventor has considered that it is possible to prevent the swollen deformation of the tab due to the shape effect by paying attention to the tab of the lead frame on which the chip is mounted and devising the shape of this tab. It was
【０００７】そこで、本発明の目的は、形状効果により
タブの膨れ変形を防止することができ、この結果、放熱
特性、信頼性の向上が可能となる半導体装置およびその
製造方法を提供するものである。Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can prevent the swelling and deformation of the tab due to the shape effect, and as a result, can improve the heat dissipation characteristics and reliability. is there.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１０】すなわち、本発明による半導体装置は、表
面に凸部、裏面に凹部がそれぞれ形成されたタブと、複
数のインナーリードと、各インナーリードにつながる複
数のアウターリードとからなるリードフレームと、この
リードフレームのタブの表面上に搭載される半導体チッ
プと、この半導体チップの電極とリードフレームのイン
ナーリードとを接続するワイヤと、リードフレームのア
ウターリードとタブの裏面とを露出するように、半導体
チップおよびワイヤの接続部分を封止する封止材とを有
するものである。That is, the semiconductor device according to the present invention includes a tab having a convex portion on the front surface and a concave portion on the back surface, a plurality of inner leads, and a lead frame including a plurality of outer leads connected to the inner leads. To expose the semiconductor chip mounted on the surface of the tab of the lead frame, the wire connecting the electrode of the semiconductor chip and the inner lead of the lead frame, the outer lead of the lead frame and the back surface of the tab, And a sealing material that seals the connection portion of the semiconductor chip and the wire.
【００１１】さらに、前記半導体装置において、凸部お
よび凹部は、タブの中心から放射状に線状凸形状および
線状凹形状に形成されていたり、タブの中心から放射状
に線状凸形状および線状凹形状に形成されている線状部
と、タブの中心に点状凸形状および点状凹形状に形成さ
れている点状部との組み合わせからなり、あるいはタブ
の中心を頂点とする球形状に形成されているものであ
る。Further, in the above semiconductor device, the convex portions and the concave portions are formed in a linear convex shape and a linear concave shape radially from the center of the tab, or a linear convex shape and a linear shape radially from the center of the tab. Consists of a linear part formed in a concave shape and a dot-shaped part formed in a point-shaped convex shape and a point-shaped concave shape in the center of the tab, or in a spherical shape with the center of the tab as the apex. It has been formed.
【００１２】また、本発明による半導体装置の製造方法
は、表面に凸部、裏面に凹部がそれぞれ形成されたタブ
と、複数のインナーリードと、各インナーリードにつな
がる複数のアウターリードとからなるリードフレーム
と、半導体チップとを用意し、リードフレームのタブの
表面上に半導体チップを搭載し、半導体チップの電極と
リードフレームのインナーリードとをワイヤにより接続
し、リードフレームのアウターリードとタブの裏面とを
露出するように、半導体チップおよびワイヤの接続部分
を封止材により封止する、各工程を有するものである。Further, in the method of manufacturing a semiconductor device according to the present invention, a lead including a tab having a convex portion on the front surface and a concave portion on the rear surface, a plurality of inner leads, and a plurality of outer leads connected to each inner lead. A frame and a semiconductor chip are prepared, the semiconductor chip is mounted on the surface of the tab of the lead frame, the electrodes of the semiconductor chip and the inner leads of the lead frame are connected by wires, and the outer leads of the lead frame and the back surface of the tab are connected. Each step of sealing the connecting portion of the semiconductor chip and the wire with a sealing material so as to expose and.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において、同一部材には同一の符号を付
し、その繰り返しの説明は省略する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, the same members are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１４】まず、図１〜図３により、本発明の一実施
の形態の半導体装置の構成の一例を説明する。図１〜図
３は本実施の形態の半導体装置を示し、図１は平面図、
図２は裏面図、図３は断面図（図２のＡ−Ａ’切断線に
よる拡大断面図）である。First, an example of the configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3 show a semiconductor device of the present embodiment, FIG. 1 is a plan view,
2 is a rear view and FIG. 3 is a sectional view (enlarged sectional view taken along the line AA ′ in FIG. 2).
【００１５】本実施の形態の半導体装置は、たとえばＨ
ＴＱＦＰとされ、タブ、インナーリードおよびアウター
リードからなるリードフレーム１と、このリードフレー
ム１のタブ上に搭載される半導体チップ２と、この半導
体チップ２とリードフレーム１のインナーリードとを接
続するワイヤ３と、半導体チップ２およびワイヤ３の接
続部分を封止する封止材４などから構成され、特にリー
ドフレーム１のタブを露出させたヒートシンク構造とな
っている。The semiconductor device of the present embodiment is, for example, H
A lead frame 1 which is a TQFP and includes a tab, an inner lead and an outer lead, a semiconductor chip 2 mounted on the tab of the lead frame 1, and a wire connecting the semiconductor chip 2 and the inner lead of the lead frame 1. 3 and a sealing material 4 for sealing the connecting portion of the semiconductor chip 2 and the wire 3 and the like, and has a heat sink structure in which the tab of the lead frame 1 is exposed.
【００１６】リードフレーム１は、たとえば銅合金など
のフレームからなり、表面に凸部５、裏面に凹部６がそ
れぞれ形成されたタブ７と、複数のインナーリード８
と、各インナーリード８につながる複数のアウターリー
ド９とを有し、各インナーリード８は半導体チップ２の
各電極とワイヤ３により電気的に接続され、また各アウ
ターリード９は封止材４から突出して成形されて外部端
子となる。The lead frame 1 is made of, for example, a frame of copper alloy or the like, a tab 7 having a convex portion 5 on the front surface and a concave portion 6 on the rear surface, and a plurality of inner leads 8.
And a plurality of outer leads 9 connected to each inner lead 8, each inner lead 8 is electrically connected to each electrode of the semiconductor chip 2 by a wire 3, and each outer lead 9 is connected to the sealing material 4 An external terminal is formed by protruding.
【００１７】半導体チップ２は、たとえばシリコン基板
上に形成されたロジックやメモリなどからなり、この表
面上に複数の電極１０が設けられ、内部に形成されたロ
ジックやメモリなどの所定の回路の各端子から表面上の
電極１０まで電気的に接続されている。この半導体チッ
プ２は、リードフレーム１のタブ７の表面上に、たとえ
ば銀粉末含有エポキシ樹脂などの接着剤による接着層１
１を介して搭載される。The semiconductor chip 2 is composed of, for example, logic and memory formed on a silicon substrate, a plurality of electrodes 10 are provided on the surface thereof, and each of predetermined circuits such as logic and memory formed inside is provided. It is electrically connected from the terminal to the electrode 10 on the surface. This semiconductor chip 2 has an adhesive layer 1 made of an adhesive such as an epoxy resin containing silver powder on the surface of the tab 7 of the lead frame 1.
It is mounted via 1.
【００１８】ワイヤ３は、たとえば金などの金属線から
なり、このワイヤ３により半導体チップ２の表面上の電
極１０とリードフレーム１のインナーリード８とが電気
的に接続される。The wire 3 is made of a metal wire such as gold, and the wire 3 electrically connects the electrode 10 on the surface of the semiconductor chip 2 and the inner lead 8 of the lead frame 1.
【００１９】封止材４は、たとえばエポキシ系などの絶
縁性樹脂材料からなり、この封止材４によりリードフレ
ーム１のアウターリード９とタブ７の裏面とを露出する
ように、半導体チップ２およびワイヤ３の接続部分が封
止される。The sealing material 4 is made of, for example, an insulating resin material such as epoxy, and the semiconductor chip 2 and the semiconductor chip 2 are formed so that the outer leads 9 of the lead frame 1 and the back surface of the tab 7 are exposed by the sealing material 4. The connection part of the wire 3 is sealed.
【００２０】以上のように構成されたＨＴＱＦＰは、半
導体チップ２の回路の各端子から、この半導体チップ２
の表面上の電極１０、ワイヤ３、リードフレーム１のイ
ンナーリード８を通じて、このインナーリード８につな
がるアウターリード９まで電気的に接続された構造とな
る。The HTQFP configured as described above is arranged so that each terminal of the circuit of the semiconductor chip 2 is connected to the semiconductor chip 2 through the terminals.
Through the electrode 10, the wire 3, and the inner lead 8 of the lead frame 1, the outer lead 9 connected to the inner lead 8 is electrically connected.
【００２１】次に、図４および図５により、本実施の形
態の半導体装置において、リードフレームの構成の一例
を説明する。図４はリードフレームを示す平面図、図５
はタブを詳細に示す平面図（ａ）および断面図（ｂ：
（ａ）のＢ−Ｂ’切断線による拡大断面図）である。Next, an example of the structure of the lead frame in the semiconductor device of the present embodiment will be described with reference to FIGS. 4 and 5. 4 is a plan view showing the lead frame, and FIG.
Is a plan view (a) and a sectional view (b:
It is an expanded sectional view by the BB 'cutting line of (a).
【００２２】リードフレーム１は、たとえば短冊状のプ
レス加工フレームからなり、複数個のパッケージが取得
可能な構成になっている。その１個の半導体チップ２に
対応する各部分の中央部に４本のタブ吊りリード１２に
より支持されたタブ７が設けられ、このタブ７の周縁近
傍にタブ７を囲むように複数のインナーリード８が設け
られ、さらにその延長線上にダムバー１３を介して、各
インナーリード８につながる複数のアウターリード９が
設けられている。The lead frame 1 is composed of, for example, a strip-shaped press working frame, and has a structure capable of obtaining a plurality of packages. A tab 7 supported by four tab suspension leads 12 is provided at the center of each part corresponding to the one semiconductor chip 2, and a plurality of inner leads are provided near the periphery of the tab 7 so as to surround the tab 7. 8 are provided, and further, a plurality of outer leads 9 connected to each inner lead 8 via the dam bar 13 are provided on the extension line thereof.
【００２３】特に、リードフレーム１のタブ７には、図
５に示すように、タブ７の中心から放射状に線状凸形状
に凸部５が表面に形成され、この表面の凸部５と同じ位
置にタブ７の中心から放射状に線状凹形状に凹部６が裏
面に形成されている。このタブ７の凸部５および凹部６
は、たとえばスタンピングなどのプレス加工により成形
される。たとえば、タブ７の厚さＴが１５０μｍ程度の
場合に、凸部５、凹部６の寸法ｔは１０μｍ程度であ
る。また、このタブ７の部分は、パッケージ裏面に露出
させるために、たとえば前記図３に示すように、インナ
ーリード８の位置よりも低い位置になるように加工成形
されている。In particular, on the tab 7 of the lead frame 1, as shown in FIG. 5, a convex portion 5 is formed on the surface in a linear convex shape radially from the center of the tab 7 and is the same as the convex portion 5 on this surface. At the position, a concave portion 6 is formed on the back surface in a linear concave shape radially from the center of the tab 7. The convex portion 5 and the concave portion 6 of the tab 7
Is formed by pressing such as stamping. For example, when the thickness T of the tab 7 is about 150 μm, the dimension t of the convex portion 5 and the concave portion 6 is about 10 μm. Further, the tab 7 portion is processed and formed so as to be located at a position lower than the position of the inner lead 8 so as to be exposed on the back surface of the package, for example, as shown in FIG.
【００２４】次に、図６および図７により、本実施の形
態の半導体装置の製造方法の一例の手順を説明する。図
６および図７は本実施の形態の半導体装置の製造方法を
示すフロー図であり、右側の図は左側の各フローに対応
する半導体装置の断面図をそれぞれ示す。Next, the procedure of an example of the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 6 and 7 are flowcharts showing the method for manufacturing the semiconductor device of the present embodiment, and the drawings on the right side are cross-sectional views of the semiconductor device corresponding to the respective flows on the left side.
【００２５】（１）用意工程（ステップＳ１）
ＨＴＱＦＰの組み立てに必要な、リードフレーム１、半
導体チップ２、ワイヤ３、封止材４などを用意する。リ
ードフレーム１は、プレス加工により複数個取りの短冊
状に成形する際に、タブ７にもスタンピングにより凸部
５および凹部６が形成されたものである。半導体チップ
２は、ウェハの前工程において、酸化・拡散・不純物導
入、配線パターン形成、絶縁層形成、配線層形成などの
ウエハ処理工程を繰り返して所望の回路が形成され、こ
のウェハを切断してチップ毎に個別に切り離されたもの
である。(1) Preparation Step (Step S1) The lead frame 1, the semiconductor chip 2, the wires 3, the encapsulating material 4, etc. necessary for assembling the HTQFP are prepared. When the lead frame 1 is formed by pressing into a plurality of strips, the tabs 7 are also formed with the protrusions 5 and the recesses 6 by stamping. In the semiconductor chip 2, a desired circuit is formed by repeating wafer processing steps such as oxidation / diffusion / impurity introduction, wiring pattern formation, insulation layer formation, and wiring layer formation in the pre-process of the wafer. The chips are individually separated.
【００２６】（２）チップ搭載工程（ステップＳ２）
リードフレーム１のタブ７の表面上に、銀粉末含有エポ
キシ樹脂などの接着剤による接着層１１により半導体チ
ップ２を固着して搭載する。(2) Chip Mounting Step (Step S2) The semiconductor chip 2 is fixedly mounted on the surface of the tab 7 of the lead frame 1 by the adhesive layer 11 made of an adhesive such as epoxy resin containing silver powder.
【００２７】（３）ワイヤボンディング工程（ステップ
Ｓ３）
半導体チップ２の電極１０とリードフレーム１のインナ
ーリード８とをワイヤ３により接続する。(3) Wire Bonding Step (Step S3) The wire 10 connects the electrode 10 of the semiconductor chip 2 and the inner lead 8 of the lead frame 1.
【００２８】（４）封止工程（ステップＳ４）
リードフレーム１のアウターリード９とタブ７の裏面と
を露出するように、半導体チップ２およびワイヤ３の接
続部分を封止材４により封止する。(4) Sealing Step (Step S4) The connecting portion of the semiconductor chip 2 and the wire 3 is sealed with the sealing material 4 so that the outer lead 9 of the lead frame 1 and the back surface of the tab 7 are exposed. .
【００２９】（５）切断・成形工程（ステップＳ５）
リードフレーム１のアウターリード９を、所定の長さを
残して切断し、このアウターリード９をガルウイング状
に成形する。これにより、ＨＴＱＦＰ構造の半導体装置
が完成する。(5) Cutting and Forming Step (Step S5) The outer lead 9 of the lead frame 1 is cut while leaving a predetermined length, and the outer lead 9 is formed into a gull wing shape. As a result, the semiconductor device having the HTQFP structure is completed.
【００３０】以上の工程を経て完成された半導体装置
は、実装基板への実装後の耐湿性が問題となるが、本実
施の形態のように、タブ７の表面に凸部５を形成し、裏
面にも表面の凸部５と同じ位置に凹部６を形成すること
により、パッケージ裏面側へのタブ７の変形を防止し、
吸湿後のリフロー実装や、その後の温度サイクルなどに
よる封止材４の剥離、タブ７の膨れを防止することがで
きる。In the semiconductor device completed through the above steps, the moisture resistance after mounting on the mounting substrate becomes a problem, but as in this embodiment, the convex portion 5 is formed on the surface of the tab 7, By forming the concave portion 6 on the back surface at the same position as the convex portion 5 on the front surface, deformation of the tab 7 to the back surface side of the package is prevented,
It is possible to prevent reflow mounting after absorbing moisture, peeling of the sealing material 4 and swelling of the tab 7 due to a subsequent temperature cycle or the like.
【００３１】従って、本実施の形態においては、タブ７
に凸部５および凹部６を設けることで、この凸部５およ
び凹部６による形状効果によりタブ７の膨れ変形を防止
することができるので、ＨＴＱＦＰの放熱特性、信頼性
を向上させることができる。Therefore, in the present embodiment, the tab 7
By providing the convex portion 5 and the concave portion 6 on the ridge, the bulging deformation of the tab 7 can be prevented by the shape effect of the convex portion 5 and the concave portion 6, so that the heat dissipation characteristics and reliability of the HTQFP can be improved.
【００３２】また、本実施の形態のように、タブ７に形
状効果を持たせる場合の例としては、たとえば図８〜図
１０のような形状なども考えられる。Further, as an example of giving the tab 7 a shape effect as in the present embodiment, shapes such as those shown in FIGS. 8 to 10 can be considered.
【００３３】図８（（ａ）は平面図、（ｂ）は（ａ）の
Ｃ−Ｃ’切断線による拡大断面図）は、タブ７ａが円形
の場合で、図５と同様にタブ７ａの中心から放射状に線
状凸形状および線状凹形状が形成されており、さらにタ
ブ７ａの中心が点状凸形状および点状凹形状に形成され
ている。この例は、タブ７ａの凸部５ａおよび凹部６ａ
を、線状部と点状部との組み合わせから形成する例であ
る。8 (a) is a plan view and FIG. 8 (b) is an enlarged sectional view taken along the line CC 'of FIG. 8 (a), where the tab 7a is circular, and as in FIG. A linear convex shape and a linear concave shape are radially formed from the center, and the center of the tab 7a is formed in a point convex shape and a point concave shape. In this example, the convex portion 5a and the concave portion 6a of the tab 7a are
Is an example of forming from a combination of linear portions and dot portions.
【００３４】図９（（ａ）は平面図、（ｂ）は（ａ）の
Ｄ−Ｄ’切断線による断面図）は、図５と同様にタブ７
ｂが矩形の場合で、表面が凸形状に形成され、裏面が凹
形状に形成されている。この例は、タブ７ｂの凸部５ｂ
および凹部６ｂを、タブ７ｂの中心を頂点とする球形状
に形成する例である。FIG. 9 ((a) is a plan view, (b) is a sectional view taken along the line D-D 'of (a)).
When b is rectangular, the front surface is formed in a convex shape and the back surface is formed in a concave shape. In this example, the convex portion 5b of the tab 7b is
And the concave portion 6b is formed in a spherical shape having the center of the tab 7b as an apex.
【００３５】図１０（（ａ）は平面図、（ｂ）は（ａ）
のＥ−Ｅ’切断線による断面図）は、図５と同様にタブ
７ｃが矩形の場合で、表面および裏面に凸形状と凹形状
が交互に形成されている。この例は、タブ７ｃの凸部５
ｃおよび凹部６ｃを、タブ７ｃの中心から径の異なる複
数の円形状に形成する例である。FIG. 10 (a) is a plan view, and FIG. 10 (b) is (a).
5 is a sectional view taken along the line EE ′ of FIG. 5), where the tab 7c has a rectangular shape as in FIG. 5, and convex and concave shapes are alternately formed on the front surface and the back surface. In this example, the convex portion 5 of the tab 7c is
This is an example in which the c and the recess 6c are formed in a plurality of circular shapes having different diameters from the center of the tab 7c.
【００３６】以上の図８〜図１０のような形状において
も、前記と同様に、凸部５ａ，５ｂ，５ｃおよび凹部６
ａ，６ｂ，６ｃの形状効果によりタブ７ａ，７ｂ，７ｃ
の膨れ変形を防止することができる。Also in the above-described shapes as shown in FIGS. 8 to 10, similarly to the above, the convex portions 5a, 5b, 5c and the concave portion 6 are formed.
The tabs 7a, 7b, 7c due to the shape effect of a, 6b, 6c
It is possible to prevent the bulging deformation of the.
【００３７】以上、本発明者によってなされた発明をそ
の実施の形態に基づき具体的に説明したが、本発明は前
記実施の形態に限定されるものではなく、その要旨を逸
脱しない範囲で種々変更可能であることはいうまでもな
い。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.
【００３８】たとえば、前記実施の形態においては、Ｈ
ＴＱＦＰを例に説明したが、ＨＴＳＯＰなどのプラスチ
ックモールドパッケージなどにも適用可能であり、特に
高放熱面実装パッケージに効果的であり、さらに半導体
装置全般に適用することができる。For example, in the above embodiment, H
Although TQFP has been described as an example, it can be applied to a plastic mold package such as HTSOP, is particularly effective for a high heat dissipation surface mount package, and can be applied to all semiconductor devices.
【００３９】また、タブの形状については、前記のよう
な例に限定されるものではなく、変形し難い形状であれ
ばよい。Further, the shape of the tab is not limited to the above-mentioned example, and may be any shape that is difficult to deform.
【００４０】[0040]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.
【００４１】（１）表面に凸部、裏面に凹部がそれぞれ
形成されたタブを有するリードフレームを用いること
で、凸部および凹部の形状効果によりタブの変形を防止
することができるので、吸湿後のリフロー実装や温度サ
イクルなどによる樹脂剥離、タブ膨れを防止することが
可能となる。(1) By using a lead frame having tabs each having a convex portion on the front surface and a concave portion on the back surface, deformation of the tabs can be prevented by the shape effect of the convex portions and the concave portions. It is possible to prevent resin peeling and tab swelling due to reflow mounting or temperature cycle.
【００４２】（２）前記（１）により、タブの膨れ変形
を防止することができるので、放熱特性、信頼性の向上
が可能な半導体装置を提供することが可能となる。(2) According to the above (1), it is possible to prevent the tab from being swollen and deformed, so that it is possible to provide a semiconductor device capable of improving heat dissipation characteristics and reliability.
【図１】本発明の一実施の形態の半導体装置を示す平面
図である。FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施の形態の半導体装置を示す裏面
図である。FIG. 2 is a back view showing a semiconductor device according to an embodiment of the present invention.
【図３】本発明の一実施の形態の半導体装置を示す断面
図である。FIG. 3 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図４】本発明の一実施の形態の半導体装置において、
リードフレームを示す平面図である。FIG. 4 shows a semiconductor device according to an embodiment of the present invention,
It is a top view which shows a lead frame.
【図５】（ａ），（ｂ）は本発明の一実施の形態の半導
体装置において、リードフレームのタブを詳細に示す平
面図および断面図である。5A and 5B are a plan view and a cross-sectional view showing in detail a tab of a lead frame in a semiconductor device according to an embodiment of the present invention.
【図６】本発明の一実施の形態の半導体装置の製造方法
を示すフロー図である。FIG. 6 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図７】本発明の一実施の形態の半導体装置の製造方法
（図６に続く）を示すフロー図である。FIG. 7 is a flowchart showing a method for manufacturing a semiconductor device (continued from FIG. 6) according to the embodiment of the present invention.
【図８】（ａ），（ｂ）は本発明の一実施の形態の半導
体装置において、リードフレームの他のタブを詳細に示
す平面図および断面図である。8A and 8B are a plan view and a cross-sectional view showing in detail another tab of the lead frame in the semiconductor device according to the embodiment of the present invention.
【図９】（ａ），（ｂ）は本発明の一実施の形態の半導
体装置において、リードフレームの他のタブを詳細に示
す平面図および断面図である。9A and 9B are a plan view and a cross-sectional view showing in detail another tab of the lead frame in the semiconductor device according to the embodiment of the present invention.
【図１０】（ａ），（ｂ）は本発明の一実施の形態の半
導体装置において、リードフレームの他のタブを詳細に
示す平面図および断面図である。10A and 10B are a plan view and a cross-sectional view showing in detail another tab of the lead frame in the semiconductor device according to the embodiment of the present invention.
【図１１】本発明の前提となる半導体装置において、リ
ードフレームのタブの膨れ変形を説明するための断面図
である。FIG. 11 is a cross-sectional view for explaining the bulging deformation of the tab of the lead frame in the semiconductor device which is the premise of the present invention.
１ リードフレーム ２ 半導体チップ ３ ワイヤ ４ 封止材 ５，５ａ，５ｂ，５ｃ 凸部 ６，６ａ，６ｂ，６ｃ 凹部 ７，７ａ，７ｂ，７ｃ タブ ８ インナーリード ９ アウターリード １０ 電極 １１ 接着層 １２ タブ吊りリード １３ ダムバー 1 lead frame 2 semiconductor chips 3 wires 4 Sealant 5,5a, 5b, 5c convex part 6,6a, 6b, 6c Recess 7,7a, 7b, 7c tab 8 inner lead 9 Outer leads 10 electrodes 11 Adhesive layer 12 tab suspension lead 13 Dam Bar
───────────────────────────────────────────────────── フロントページの続き (72)発明者 清水 一男 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 Ｆターム(参考） 5F067 AA04 AB03 BE02 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Kazuo Shimizu 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony Company within Hitachi Semiconductor Group F-term (reference) 5F067 AA04 AB03 BE02
Claims (5)
されたタブと、複数のインナーリードと、各インナーリ
ードにつながる複数のアウターリードとからなるリード
フレームと、 前記リードフレームの前記タブの表面上に搭載される半
導体チップと、 前記半導体チップの電極と前記リードフレームの前記イ
ンナーリードとを接続するワイヤと、 前記リードフレームの前記アウターリードと前記タブの
裏面とを露出するように、前記半導体チップおよび前記
ワイヤの接続部分を封止する封止材とを有することを特
徴とする半導体装置。1. A lead frame comprising a tab having a convex portion on the front surface and a concave portion on the back surface, a plurality of inner leads, and a lead frame having a plurality of outer leads connected to the inner leads, and a tab of the lead frame. A semiconductor chip mounted on the front surface, a wire connecting the electrode of the semiconductor chip and the inner lead of the lead frame, the outer lead of the lead frame and the back surface of the tab are exposed, A semiconductor device comprising: a semiconductor chip; and a sealing material that seals a connecting portion of the wire.
に線状凸形状および線状凹形状に形成されていることを
特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the convex portion and the concave portion are formed in a linear convex shape and a linear concave shape radially from the center of the tab. .
に線状凸形状および線状凹形状に形成されている線状部
と、前記タブの中心に点状凸形状および点状凹形状に形
成されている点状部との組み合わせからなることを特徴
とする半導体装置。3. The semiconductor device according to claim 1, wherein the convex portion and the concave portion are linear portions which are radially formed from a center of the tab into linear convex shapes and linear concave shapes, and the tab. A semiconductor device comprising a combination of a dot-shaped convex shape and a dot-shaped portion formed in a dot-shaped concave shape at the center of the semiconductor device.
る球形状に形成されていることを特徴とする半導体装
置。4. The semiconductor device according to claim 1, wherein the convex portion and the concave portion are formed in a spherical shape having the center of the tab as an apex.
されたタブと、複数のインナーリードと、各インナーリ
ードにつながる複数のアウターリードとからなるリード
フレームと、半導体チップとを用意する工程と、 前記リードフレームの前記タブの表面上に前記半導体チ
ップを搭載する工程と、 前記半導体チップの電極と前記リードフレームの前記イ
ンナーリードとをワイヤにより接続する工程と、 前記リードフレームの前記アウターリードと前記タブの
裏面とを露出するように、前記半導体チップおよび前記
ワイヤの接続部分を封止材により封止する工程とを有す
ることを特徴とする半導体装置の製造方法。5. A step of preparing a semiconductor chip and a tab having tabs each having a convex portion on a front surface and a concave portion on a rear surface, a plurality of inner leads, a lead frame including a plurality of outer leads connected to the inner leads, and a semiconductor chip. A step of mounting the semiconductor chip on the surface of the tab of the lead frame; a step of connecting an electrode of the semiconductor chip and the inner lead of the lead frame by a wire; and an outer lead of the lead frame. And a step of sealing the connection portion of the semiconductor chip and the wire with a sealing material so as to expose the back surface of the tab, and a method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001275933A JP2003086752A (en) | 2001-09-12 | 2001-09-12 | Semiconductor device and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001275933A JP2003086752A (en) | 2001-09-12 | 2001-09-12 | Semiconductor device and manufacturing method therefor |
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| Publication Number | Publication Date |
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ID=19100713
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007194379A (en) * | 2006-01-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | Lead frame, semiconductor device, and method of manufacturing same |
| JP2016072503A (en) * | 2014-09-30 | 2016-05-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method of the same |
-
2001
- 2001-09-12 JP JP2001275933A patent/JP2003086752A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007194379A (en) * | 2006-01-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | Lead frame, semiconductor device, and method of manufacturing same |
| JP2016072503A (en) * | 2014-09-30 | 2016-05-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method of the same |
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