JP6397307B2 - 凹部を充填する方法 - Google Patents
凹部を充填する方法 Download PDFInfo
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- JP6397307B2 JP6397307B2 JP2014220542A JP2014220542A JP6397307B2 JP 6397307 B2 JP6397307 B2 JP 6397307B2 JP 2014220542 A JP2014220542 A JP 2014220542A JP 2014220542 A JP2014220542 A JP 2014220542A JP 6397307 B2 JP6397307 B2 JP 6397307B2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Description
Claims (6)
- 被処理体の凹部を充填する方法であって、該被処理体は、半導体基板及び該半導体基板上に設けられた絶縁膜を有し、前記凹部は、前記絶縁膜を貫通して前記半導体基板の内部まで延在しており、該方法は、
前記凹部を画成する壁面に沿って半導体材料の第1の薄膜を形成する工程と、
前記第1の薄膜の半導体材料から、前記凹部を画成する前記半導体基板の面に沿って該半導体基板の結晶に応じたエピタキシャル領域を形成する工程であり、前記第1の薄膜を移動させずに該エピタキシャル領域を形成するように前記被処理体が第1の圧力に設定された容器内においてアニールされる、該工程と、
前記凹部を画成する壁面に沿って半導体材料の第2の薄膜を形成する工程と、
前記第2の薄膜の半導体材料から、エピタキシャル領域を更に形成する工程であり、前記凹部の底に向けて移動させた前記第2の薄膜の前記半導体材料から該エピタキシャル領域を更に形成するように前記被処理体が前記第1の圧力よりも低い第2の圧力に設定された容器内においてアニールされる、該工程と、
を含む、方法。 - 前記第1の圧力は133.3Paより高い圧力であり、前記第2の圧力は133.3Pa以下の圧力である、請求項1に記載の方法。
- 前記第1の薄膜を形成する前記工程の前及び/又は前記第2の薄膜を形成する前記工程の前に、アモルファス半導体層であるライナー層を形成する工程を更に含む、請求項1又は2に記載の方法。
- 前記ライナー層を形成する前記工程の前に、アミノシラン系ガス又は高次シランガスからシード層を形成する工程を更に含む、請求項3に記載の方法。
- 前記エピタキシャル領域を形成する前記工程と前記第2の薄膜を形成する前記工程との間に、前記第1の薄膜をエッチングする工程を更に含む、請求項1〜4の何れか一項に記載の方法。
- 前記エピタキシャル領域を更に形成する前記工程の後に、前記第2の薄膜をエッチングする工程を更に含む、請求項1〜5の何れか一項に記載の方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014220542A JP6397307B2 (ja) | 2014-10-29 | 2014-10-29 | 凹部を充填する方法 |
US14/919,381 US9865467B2 (en) | 2014-10-29 | 2015-10-21 | Recess filling method and processing apparatus |
TW104135018A TWI622125B (zh) | 2014-10-29 | 2015-10-26 | 凹部之充填方法 |
KR1020150149333A KR101877102B1 (ko) | 2014-10-29 | 2015-10-27 | 오목부를 충전하는 방법 및 처리 장치 |
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JP2014220542A JP6397307B2 (ja) | 2014-10-29 | 2014-10-29 | 凹部を充填する方法 |
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JP2016092029A JP2016092029A (ja) | 2016-05-23 |
JP6397307B2 true JP6397307B2 (ja) | 2018-09-26 |
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US (1) | US9865467B2 (ja) |
JP (1) | JP6397307B2 (ja) |
KR (1) | KR101877102B1 (ja) |
TW (1) | TWI622125B (ja) |
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JP6719416B2 (ja) * | 2017-03-30 | 2020-07-08 | 東京エレクトロン株式会社 | 凹部の埋め込み方法および処理装置 |
KR102540252B1 (ko) * | 2018-07-10 | 2023-06-07 | 주식회사 원익아이피에스 | 반도체 소자의 제조 방법 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS58116722A (ja) * | 1981-12-29 | 1983-07-12 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS6477924A (en) * | 1987-09-18 | 1989-03-23 | Fujitsu Ltd | Manufacture of semiconductor device |
US5888876A (en) * | 1996-04-09 | 1999-03-30 | Kabushiki Kaisha Toshiba | Deep trench filling method using silicon film deposition and silicon migration |
JPH1131659A (ja) * | 1997-07-10 | 1999-02-02 | Toshiba Corp | 半導体装置の製造方法 |
JP2000269462A (ja) * | 1999-03-19 | 2000-09-29 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3485081B2 (ja) * | 1999-10-28 | 2004-01-13 | 株式会社デンソー | 半導体基板の製造方法 |
US6410455B1 (en) * | 1999-11-30 | 2002-06-25 | Wafermasters, Inc. | Wafer processing system |
GB0101528D0 (en) * | 2001-01-20 | 2001-03-07 | Trikon Holdings Ltd | A method of filling trenches |
US7344979B2 (en) * | 2005-02-11 | 2008-03-18 | Wafermasters, Inc. | High pressure treatment for improved grain growth and void reduction |
JP6059085B2 (ja) * | 2013-05-27 | 2017-01-11 | 東京エレクトロン株式会社 | トレンチを充填する方法及び処理装置 |
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- 2014-10-29 JP JP2014220542A patent/JP6397307B2/ja active Active
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- 2015-10-21 US US14/919,381 patent/US9865467B2/en active Active
- 2015-10-26 TW TW104135018A patent/TWI622125B/zh active
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KR101877102B1 (ko) | 2018-07-10 |
US9865467B2 (en) | 2018-01-09 |
TWI622125B (zh) | 2018-04-21 |
TW201628126A (zh) | 2016-08-01 |
KR20160052345A (ko) | 2016-05-12 |
US20160126103A1 (en) | 2016-05-05 |
JP2016092029A (ja) | 2016-05-23 |
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