JP6392171B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6392171B2
JP6392171B2 JP2015108811A JP2015108811A JP6392171B2 JP 6392171 B2 JP6392171 B2 JP 6392171B2 JP 2015108811 A JP2015108811 A JP 2015108811A JP 2015108811 A JP2015108811 A JP 2015108811A JP 6392171 B2 JP6392171 B2 JP 6392171B2
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substrate
pad
connecting member
semiconductor chip
semiconductor device
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Japanese (ja)
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JP2016225414A5 (enExample
JP2016225414A (ja
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洋弘 町田
洋弘 町田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2015108811A priority Critical patent/JP6392171B2/ja
Priority to US15/155,175 priority patent/US9564421B2/en
Publication of JP2016225414A publication Critical patent/JP2016225414A/ja
Publication of JP2016225414A5 publication Critical patent/JP2016225414A5/ja
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
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WO2018230534A1 (ja) * 2017-06-16 2018-12-20 株式会社村田製作所 回路基板および回路モジュール、ならびに回路基板の製造方法および回路モジュールの製造方法
JP7015721B2 (ja) * 2018-04-05 2022-02-03 新光電気工業株式会社 配線基板、電子装置
US11569159B2 (en) * 2019-08-30 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of chip package with through vias
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US11094668B2 (en) * 2019-12-12 2021-08-17 Micron Technology, Inc. Solderless interconnect for semiconductor device assembly

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US8404520B1 (en) * 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
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