JP6298312B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a manufacturing method of a multilayer wiring having Al alloy wiring of a semiconductor device, a method of filling a connection hole by blanket tungsten CVD or high temperature sputtering is a known technique as a method of filling a connection hole having a high aspect ratio.

JP-A-8-255833 JP-A-5-267471

The following three points can be cited as problems caused by filling the connection hole with tungsten.
(1) Since connection resistance becomes high resistance, it is disadvantageous in terms of high-speed operation or current consumption. (2) Since there are many manufacturing steps, manufacturing TAT is long and cost is high. (3) Structurally weak to electromigration. Supplementing (3), when Al alloys are connected to each other, Al atoms are supplied from the Al alloy wiring on the cathode side to the Al alloy wiring on the anode side by electromigration. This is because diffusion is blocked by tungsten embedded in the connection hole.

  In order to solve the problems (1) to (3), it is effective to embed Al by high-temperature sputtering, but it is difficult to embed in a connection hole having a high aspect ratio as compared to tungsten, and the aspect ratio is 6 or more. In this case, it is highly possible that Al cannot be completely filled and voids are generated in the connection holes, and there are problems in connection resistance and long-term reliability.

  A method other than high temperature sputtering corresponding to a high aspect ratio is disclosed in Patent Document 1, but it is difficult to obtain sufficient coverage for a connection hole having a high aspect ratio as shown in FIG. Voids may occur in the holes. Further, Patent Document 2 discloses a method of introducing and embedding Al alloy in the connection hole by surface tension by applying heat treatment after depositing Al alloy 13 of the upper layer and surface diffusion of Al. As described above, the Al alloy of the lower layer wiring is sucked up by the upper layer wiring due to aggregation, and there is a concern that the embedding property may be impaired.

  Therefore, the gist of the present invention relates to a method for embedding Al in a connection hole having a high aspect ratio, and to provide a manufacturing method that is excellent in filling of the connection hole, has low resistance, is strong in electromigration resistance, and is low in cost. is there.

  In order to solve the above problems, in the present invention, a step of depositing a plasma nitride film on a first wiring having a laminated structure of a barrier metal, an Al alloy, and an antireflection film on an insulating film including a semiconductor substrate; A step of depositing an oxide film on the nitride film and then flattening; a step of opening a connection hole on the interlayer insulating film made of the plasma nitride film and the oxide film to expose the Al alloy surface of the first wiring; Removing the alumina layer on the surface of the Al alloy at the bottom of the connection hole in a vacuum; and at least a temperature higher than the film formation temperature of the plasma nitride film and the interlayer insulating film in the vacuum after the alumina layer is removed. The first heat treatment is performed so that the Al alloy in the portion where the connection hole is opened is raised in a convex shape within the range from the bottom of the connection hole to the top surface of the connection hole, and at least the first heat treatment is performed in a high-pressure argon gas atmosphere. There is provided a method of manufacturing a semiconductor device comprising the step of forming the upper wiring after flattened by flowing the Al alloy is raised to the convex performing a second heat treatment at a high temperature. Further, when the diameter of the connection hole at the bottom of the connection hole is A and the Al alloy film thickness of the first wiring is B, the relation of B ≧ A is established. Further, the first heat treatment temperature is in the range of 400 ° C. to 470 ° C., the second heat treatment temperature is in the range of 450 ° C. to 550 ° C., and the upper wiring is high in the upper layer of the Al alloy and the Al alloy. It has a structure made of a melting point metal, and the thickness of the refractory metal is in the range of 50 nm to 200 nm.

  It is possible to form a metal connection that is excellent in filling into the connection hole, low resistance, and strong in electromigration resistance.

(A)-(d) is sectional drawing of the manufacturing flow of this invention which concerns on embodiment. (A)-(d) is sectional drawing of the manufacturing flow of this invention which concerns on embodiment following FIG. It is the schematic diagram which showed the relationship between Al film thickness and the diameter of a connection hole which concern on embodiment. It is a typical figure of the Example by a prior art. It is a typical figure of the Example by a related art similarly.

The form for implementing this invention is demonstrated based on process sectional drawing.
First, as shown in FIG. 1A for explaining the embodiment, a barrier metal 3, an Al wiring 4 and an antireflection film 5 are deposited on a semiconductor substrate 1 on which an insulating film 2 is formed, and then photolithography is performed. A first wiring is formed by a dry etching technique.

Next, a plasma nitride film 6 is formed as shown in FIG. The film forming temperature is a general temperature range of about 350 ° C. to 400 ° C. if the film forming apparatus is a single wafer type apparatus and the holding time until the film formation starts from a bare state is several seconds to several tens of seconds. Good. However, when a holding time of 30 minutes to 1 hour is required as in a batch type device, if hillocks appear in the wiring due to stress relaxation due to thermal stress, the Al of the connection hole portion originally intended to be obtained in a later process Since it is difficult to obtain a raised shape, it is desirable that the temperature is as low as possible.
Further, an oxide film is formed by CVD, and after performing a planarization process using an SOG etchback or a chemical mechanical polishing method, the oxide film is formed again to obtain the oxide film 7.

  Subsequently, as shown in FIG. 1C, a connection hole 8 is opened in the interlayer insulating film composed of the plasma nitride film 6 and the oxide film 7 by photolithography and drying techniques. The size of the connection hole is preferably designed so that A ≦ B when the diameter of the connection hole is A and the film thickness of the first Al alloy wiring is B as shown in FIG. This is because it is desired to obtain a sufficient height in the Al raised portion of the connection hole to be obtained later. During etching, the antireflection film made of a refractory metal film is removed by overetching to expose the Al surface. Thereafter, the resist is immersed in an ashing treatment and an organic stripping solution to completely remove the resist and etching by-products. An alumina 9 layer is formed on the Al surface at the bottom of the connection hole.

  Then, using an Al sputtering apparatus having RF etching, a heating mechanism in vacuum, and a high-pressure heating mechanism, the Al surface is first etched by RF etching with Ar plasma at room temperature to remove the alumina layer 9, and FIG. As shown in d), a clean Al surface 10 is obtained.

  Subsequently, the semiconductor substrate is annealed in a temperature range of 400 ° C. to 470 ° C. for about 60 seconds to 300 seconds as a first heat treatment in a vacuum chamber having a mechanism capable of heating the semiconductor substrate by irradiation with a resistance lamp or halogen lamp. Thus, the Al raised portion 11 shown in FIG. The heating time is appropriately adjusted between the resistance heating and the halogen lamp because the heating rate of the semiconductor substrate is different. However, the heating time needs to be adjusted so that the height of the apex of the raised portion of the Al is not more than the upper surface of the connection hole. This indicates the possibility that the connection hole portion may become convex even after the raised Al becomes higher than the upper surface of the connection hole, and when the wiring is provided in the upper layer, the interlayer insulating film is flattened. This is because the interlayer film of the convex portion of the connection hole portion is locally thinned. This is to avoid the problem that the convex portion is exposed after the worst flattening process and causes a short circuit between the lower layer wiring and the upper layer wiring.

  Then, the first heat treatment is performed as a second heat treatment in a chamber having a mechanism capable of heating the semiconductor substrate by irradiation with a resistance heater or halogen lamp without being exposed to the atmosphere and capable of pressurizing from 2 atm to 5 atm in an Ar high pressure gas atmosphere. An Al buried portion shown in FIG. 2 (b) is obtained by annealing the semiconductor substrate in a temperature range of 420 ° C. to 550 ° C. for about 60 seconds to 300 seconds at a temperature higher than that of the heat treatment in FIG. Get 12.

Subsequently, as shown in FIG. 2C, the Al alloy layer 13 is obtained by sputtering to have a desired film thickness by upper Al sputtering, and a high melting point metal is sputtered in the range of 20 nm to 200 nm. A metal layer 14 is obtained. This refractory metal layer plays a role of performing not only an antireflection film but also a bypass effect for increasing the stress migration resistance of the Al alloy.
Finally, a wiring pattern is formed using photolithography and etching techniques to obtain a connection portion as shown in FIG.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Barrier metal 4 1st wiring Al alloy 5 Antireflection film 6 Plasma nitride film 7 Oxide film 8 Connection hole 9 Alumina layer 10 Al clean surface 11 Al protuberance 12 Al buried part 13 Upper layer Al alloy wiring 14 Refractory metal layer A Via hole bottom diameter B Al film thickness of first wiring

Claims (5)

Depositing a plasma nitride film on the first wiring having a laminated structure of a barrier metal, an Al alloy, and an antireflection film;
Depositing and flattening an oxide film;
A step of exposing a surface of the Al alloy constituting the first wiring by opening a connection hole on the interlayer insulating film made of the plasma nitride film and the oxide film using a resist pattern;
Removing the resist pattern and etching by-products completely, and forming an alumina layer on the surface of the Al alloy;
Removing the alumina layer at room temperature in vacuum;
After the alumina layer is removed, a first heat treatment is performed in vacuum at a temperature higher than the deposition temperature of at least the plasma nitride film and the interlayer insulating film, and the Al alloy in the portion where the connection hole is formed is connected to the bottom of the connection hole A step of projecting in the range of the upper surface of the connection hole from,
A step of at least the first performing a second heat treatment at a temperature higher than the heat treatment, to flatten by the flow of the Al alloy is raised to the convex with high pressure argon gas cut囲中,
A step of forming an upper layer wiring after the Al alloy raised in a convex manner is flowed and flattened;
Only including,
The step of flowing and flattening the Al alloy is performed in the same apparatus as the step of raising the protrusion, and is processed without exposure to the atmosphere following the step of raising the protrusion . Production method.   In the step of exposing the surface of the Al alloy, B ≧ A when the hole diameter at the bottom of the connection hole is A and the film thickness of the Al alloy of the first wiring is B. The method of manufacturing a semiconductor device according to claim 1.   In the step of forming an alumina layer on the surface of the Al alloy, the resist pattern and etching by-products are completely removed by immersing in an ashing process and an organic stripping solution, and alumina is formed on the surface of the Al alloy. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a layer is formed.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first heat treatment temperature is in a range of 400 ° C. to 470 ° C., and the second heat treatment temperature is in a range of 420 ° C. to 550 ° C. 3.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the upper wiring has a laminated structure made of an Al alloy and a refractory metal.

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