JPH08316307A - Method for forming multilayer wiring - Google Patents

Abstract

PURPOSE: To make via contact resistance lower by forming a resist pattern after forming a lower layer metal wiring and then selectively removing a reflection preventing film of a via contact part with the resist pattern as a mask, so that remarkable increase in via contact resistance is suppressed. CONSTITUTION: After an insulation film 2 is formed on an Si substrate 1, a lower layer Al wiring 3 having a reflection preventing film 4 is formed. Then a resist pattern 9 is formed, and then only the reflection preventing film 4 in a via contact part 7' is removed with the resist pattern 9 as a mask. Then, the resist pattern 9 is removed, and further, an interlayer insulation film 5 is accumulated. Then a resist pattern 6 is formed, and then a via hole 7 is opened on the interlayer insulation film 5 with the resist pattern 6 as a mask. After the resist pattern 6 is removed, an upper Al wiring 8 is farmed. Therefore, while EM resistance is improved and such effect as prevention of hillock is provided, low via contact resistance can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer wiring, and more particularly to a method for forming a multi-layer wiring having an antireflection film in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, as miniaturization of circuit patterns and multi-layering of wiring have progressed in semiconductor devices, the level difference of the underlying substrate has become large, and halation in the photolithography process for forming wiring has become a serious problem. . This halation is a deterioration phenomenon caused by both the step of the underlying substrate and the reflected light reflected by the step,
This is a phenomenon in which the exposure light is reflected to the side of the resist pattern adjacent to the step portion, and even the portion that should originally be left as the resist pattern adjacent to the step portion is exposed and the resist pattern collapses. The resist pattern destroyed by such halation is transferred to the Al (aluminum) alloy film in the subsequent etching step,
This causes disconnection of the Al alloy wiring.

In order to prevent the resist pattern from collapsing due to the halation, it is necessary to reduce the step of the underlying substrate or suppress the influence of the reflected light at the step. Generally, as a method of suppressing the influence of the reflected light, a method of forming a metal thin film having a low reflectance as an antireflection film on the Al alloy film is used. As the method, there is used a method of forming the low reflectance metal thin film on the Al alloy film by a sputtering method or a CVD method continuously with the formation of the Al alloy film in vacuum. The materials used as the antireflection film are currently Ti, T
There are iN, TiW, TiON, W, WSi ₂ , Si and the like.

The formation of the antireflection film not only suppresses halation but also causes electromigration (E
M) It has been reported that many additional effects such as improved resistance and hillock prevention can be obtained. For example, in order to improve the EM resistance, the structure of the antireflection film is set to a TiN / Ti / Al structure in which TiN is formed on the Al alloy film via Ti so that Ti and A
It has been reported that l reacts to form a low-resistance Al ₃ Ti layer and acts as a good current bypass, or that the Al ₃ Ti / Al interface acts to suppress migration of Al atoms (IEICE). Research Report, P67-
74, (1994), Semicon Kansai / Kyoto 93, Technical Seminar Lecture Proceedings, P11-16, (1993), JP-A-6-120218). In order to obtain these accompanying effects, a wiring structure in which the antireflection film, which is originally intended to prevent halation, is not removed after the photolithography step of wiring formation but is left as it is is generally adopted.

FIG. 3 is a schematic sectional view showing a step of forming a multi-layer wiring in the above-mentioned conventional semiconductor device.

First, the insulating film 2 is formed on the Si substrate 1, and the lower Al wiring 3 having the antireflection film 4 is formed by using the sputtering method, the photolithography and the dry etching technique (FIG. 3A). Subsequently, the interlayer insulating film 5 is formed by the CVD method, and then the resist pattern 6 is formed (FIG. 3B). Next, using the resist pattern 6 as a mask, a via hole 7 is opened in the interlayer insulating film 5 by reactive ion etching, and then the resist pattern 6 is removed (FIG. 3C). Next, the upper Al wiring 8 is formed by the same method as the lower Al wiring 3 (FIG. 3D). In this way, the upper Al wiring 8 and the lower A through the via hole 7
l wiring 3 is connected.

[0007]

According to the above-described conventional method of forming a multilayer wiring, the antireflection film 4 remains between the upper Al wiring 8 and the lower Al wiring 3. If the antireflection film 4 is left as it is after the wiring is formed, the above-mentioned effects of improving the EM resistance and preventing hillocks can be obtained.
On the other hand, the following two problems occur in via contact.

The first problem is that, for example, when TiN is used as the antireflection film 4 of the lower Al wiring 3, if TiN is exposed by overetching during via hole etching (FIG. 3C), polymer (reaction product) ) Is generated, and the polymer intervenes between the upper and lower Al wirings in the via contact portion, the via contact resistance remarkably increases, and in an extreme case, a conduction failure such as disconnection occurs. .

The polymer is similar to a so-called aluminum crown in which a deposit (AlF ₃ or the like) is formed in a crown shape on the side wall of the via hole 7 of the lower Al wiring 3 on which the antireflection film 4 is not formed. It is foreign.
The polymer is an etching gas such as CF ₄ , CHF ₃
Etc. are generated by polymerizing hydrocarbon-based gas or carbon as a resist component in high-energy plasma. When TiN is exposed by overetching, Ti decomposed from TiN catalyzes the polymerization reaction. It is believed to occur in order to The polymer is similarly produced if the antireflection film 4 is a Ti-based material such as Ti, TiW, or TiON.

The aluminum crown can be removed in a subsequent resist stripping step using a general amine-based organic stripping solution, and the resist stripping step is disclosed in JP-A-6-37188. It can be more effectively removed by processing the immediately preceding ashing with half ashing. On the other hand, the polymer resulting from the TiN antireflection film 4 cannot be removed by a general amine-based organic stripping solution, and the removal effect is not recognized even if the half ashing process is performed.

The second problem is that even if the antireflection film 4 of the lower Al wiring 3 is made of W, WSi ₂ , Si or the like which does not produce a polymer, instead of a Ti-based material,
If these layers are present in the via contact portion, there is a problem that an increase in the via contact resistance cannot be avoided due to the influence of the resistance component and the contact resistance between different metals. Especially in recent years, in order to prevent deterioration of reliability due to reduction of hole diameter,
A W plug technique for burying W in the via hole 7 is often adopted. In this case, the structure in the via contact portion is such that the antireflection film 4, the adhesion film, the adhesion film,
Since the W plug, the upper layer Al wiring 8 and a multi-layered dissimilar metal are laminated, the influence of the contact resistance between the dissimilar metals becomes more apparent.

In Japanese Patent Laid-Open No. 6-53324, as a method for suppressing the formation of the polymer in the first problem, hydrogen atoms or a gas containing a hydrogen compound is used to bond H atoms to Ti ⁺ during via hole etching. A method for suppressing the polymerization reaction has been proposed, but since the etching has strong sputterability, there is a possibility that the H atom once bonded to Ti ⁺ may be redeposited, and stable polymerization reaction may not be suppressed. Further, these added gases may affect the etching rate and etching shape.

Further, in this method, since the antireflection film is left as it is, the via contact resistance increases due to the influence of the resistance amount and the contact resistance between different kinds of metals, and the above-mentioned second problem cannot be solved.

The present invention has been made in view of the above problems, and provides a method of forming a multi-layer wiring having a low resistance via contact resistance while having the effects of improving EM resistance and preventing hillocks. It is intended to be provided.

[0015]

In order to achieve the above object, a method of forming a multilayer wiring according to the present invention is a via hole in which a lower metal wiring having an antireflection film and an upper metal wiring are provided in an interlayer insulating film. A method of forming a multi-layer wiring connected via a method, comprising the steps of forming a resist pattern after forming the lower metal wiring, and selectively removing the antireflection film of the via contact portion using the resist pattern as a mask. I am trying.

[0016]

According to the method of forming a multilayer wiring according to the present invention, since only the antireflection film of the via contact portion is selectively removed after the formation of the lower layer metal wiring having the antireflection film, the via contact portion is formed. The antireflection film remains formed on the other wiring portions. Therefore, the effect of improving the EM resistance and preventing hillocks provided by the antireflection film can be obtained in substantially the same manner as in the case of the wiring structure in which the antireflection film is not removed.

The material for forming the antireflection film is TiN.
Even if it is a Ti-based material, since the antireflection film formed on the via contact portion on the lower metal wiring has already been removed in the via-hole etching step after forming the interlayer insulating film, the Ti-based material is used. The polymerization reaction using the antireflection film as a catalyst does not occur, and the production of the polymer in the first problem is suppressed. Therefore, no increase in via contact resistance or conduction failure such as disconnection due to the polymer does not occur.

Furthermore, since the antireflection film in the via contact portion is removed, the upper metal wiring and the lower metal wiring are connected to each other by the same kind of metal, and the resistance of the antireflection film in the second problem and There is no increase in via contact resistance due to contact resistance between dissimilar metals. Even when a W plug is used for the via hole, the resistance of the antireflection film and the contact resistance between different kinds of metals as described above are alleviated, so that the via contact resistance can be similarly reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for forming a multilayer wiring according to the present invention will be described below with reference to the drawings. Components having the same functions as those of the conventional example are designated by the same reference numerals.

FIGS. 1A to 1E are sectional views schematically showing each step for explaining the method of forming a multilayer wiring according to the embodiment.

Si having a transistor (not shown) and the like
After forming the insulating film 2 on the substrate 1 by the CVD method, DC
60 AlSiCu using magnetron sputtering equipment
0 nm, Ti 10 nm, and TiN 25 nm are successively formed in this order in a vacuum. After that, the lower layer Al wiring 3 having the antireflection film 4 (TiN / Ti in this case) is formed by performing a normal photolithography and etching process (FIG. 1A).

Next, the resist pattern 9 is exposed by using a mask for forming a via hole and developed to form a resist pattern 9, and only the antireflection film 4 of the via contact portion 7'is removed by plasma etching using the resist pattern 9 as a mask. (Fig. 1 (b)). The etching conditions for the plasma etching are as follows: Si substrate 1 temperature: 180 ° C., gas pressure:
600 mTorr, CF ₄ : 650 sccm, O ₂ : 1
50 sccm, RF power: 500 W (13.56 MH
z), etching time: 15 seconds, and a downflow type etcher was used. According to the above conditions, the antireflection film 4 on the via contact portion 7'is completely etched off,
Moreover, since the above conditions have sufficient selectivity for the lower layer Al wiring 3, the lower layer Al wiring 3 is hardly etched. Therefore, the aspect ratio (hole depth / hole diameter) of the via contact portion 7'does not become extremely large. Since the above conditions are isotropic etching, the finished hole size is slightly larger than the mask size, but the etching conversion time is not a problem because the etching time is short. Rather, it acts in the direction of increasing the margin for mask alignment during the photolithography process of etching in the subsequent formation of the via hole 7.

After that, the resist pattern 9 is removed by performing ashing and resist stripping, and further plasma CV is performed.
SiO ₂ is 800 nm as the interlayer insulating film 5 by the D method,
It is deposited (FIG. 1 (c)).

Next, photolithography and etching steps are performed to form a resist pattern 6, and a via hole 7 is opened in the interlayer insulating film 5 by using the resist pattern 6 as a mask (FIG. 1D). The etching process is performed by RIE (Reactive Ion Etching), and the process conditions are: Si substrate 1 temperature: -30 ° C., gas pressure: 500 mTorr.
r, CF ₄ : 20 sccm, CHF ₃ : 20 sccm,
Ar: 300 sccm, RF power: 850 W (13.
56 MHz) and etching amount: Just + 80% (overetching amount 80%). At this time, TiN / T which is the antireflection film 4 in the via hole portion of the lower Al wiring 3 has already been formed.
Since i has been removed, no polymer is produced, but since the lower layer Al wiring 3 is exposed, an aluminum crown is produced. However, since the aluminum crown is completely removed by the subsequent ashing and the resist stripping with the amine-based organic stripping solution, there is no problem.

After the resist pattern 6 is removed by performing an ashing and resist stripping process, AlS is formed by a DC magnetron sputtering apparatus as in the case of forming the lower layer Al wiring 3.
A film of iCu 800 nm is formed, and a photolithography and etching process is performed to form an upper Al wiring 8 (FIG. 1E).

FIG. 2 shows a two-layer Al formed by the above embodiment.
6 is a graph showing a measurement result of a wiring via contact resistance. Hole diameter 0.60 to 2.00 as measurement pattern
Forming a via chain with 1000 steps of μm, 5 at both ends
The resistance value is shown when V is applied.

Further, as Comparative Example 1, the via contact resistance of the two-layer Al wiring is shown, even though the antireflection film 4 is not formed on the lower Al wiring 3, and as Comparative Example 2, TiN / Ti is shown.
2 layer Al, although the antireflection film 4 is formed and the antireflection film 4 of the via contact portion 7'is not removed.
Wiring via contact resistance is shown.

As shown in FIG. 2, in Comparative Example 2, the polymer generated during the via hole etching was a factor, and the via contact resistance value was higher than that of Comparative Example 1 by two digits or more. On the other hand, the via contact portion 7 '
In the present example in which only the antireflection film 4 of No. 1 was removed, the via contact resistance value was almost the same level as in Comparative Example 1 regardless of the via hole diameter.

Table 1 below shows Al in the examples.
The results of testing the wiring for EM resistance are shown in Comparative Examples 1 and 2.
It is shown together with the one.

The resistance test was conducted with a line width of 1.0 μm and a line length of 3000.
Current density of 3 × at a temperature of 200 ° C for μm wiring
Applying a current stress of 10 ⁶ (A / cm ² ),
MTF (mean time to failure)
Was evaluated.

[0031]

[Table 1]

As is apparent from Table 1, in the case of Comparative Example 1, the MTF was 740 hours, whereas in the case of the Al wiring according to the Example, no breakage occurred even after 2000 hours,
It had the same EM resistance as that of Comparative Example 2.

As a result of observation with an optical microscope, hillocks were not observed in the case of the two-layer Al wiring according to the example.

As described above, according to the method for forming a multi-layer wiring according to the embodiment, a multi-layer wiring having a low resistance via contact resistance while having the effects of improving EM resistance and preventing hillocks is formed. be able to.

In this embodiment, T is used as the antireflection film 4.
Although iN / Ti is used, the present invention is not limited to this, and other Ti-based materials such as TiW and TiON may be used in another embodiment, and W, WSi ₂ , Si and the like may be used. Good.

[0036]

As described above in detail, in the method for forming a multilayer wiring according to the present invention, the lower layer metal wiring having the antireflection film and the upper layer metal wiring are provided through the via hole provided in the interlayer insulating film. The method for forming a connected multi-layer wiring includes a step of forming a resist pattern after the formation of the lower metal wiring and selectively removing only the antireflection film of the via contact portion using the resist pattern as a mask. It is possible to form a multi-layer wiring having a low resistance via contact resistance while having the effects of improving resistance and preventing hillocks.

[Brief description of drawings]

1A to 1E are cross-sectional views schematically showing each step for explaining a method for forming a multilayer wiring according to an embodiment of the present invention.

FIG. 2 is a graph showing via contact resistance values in Examples and Comparative Examples.

3A to 3D are sectional views schematically showing each step for explaining a conventional method for forming a multilayer wiring.

[Explanation of symbols]

 3 Lower layer Al wiring (lower layer metal wiring) 4 Antireflection film 5 Interlayer insulating film 7 Via hole 7'Via contact part 9 Resist pattern

Claims (1)

[Claims] 1. A method for forming a multilayer wiring in which a lower-layer metal wiring having an antireflection film and an upper-layer metal wiring are connected via a via hole provided in an interlayer insulating film, wherein a resist pattern is formed after the lower-layer metal wiring is formed. A method for forming a multi-layer wiring, which comprises the step of forming and selectively removing the antireflection film in the via contact portion using the resist pattern as a mask.