JPH07201826A - Dry-etching method - Google Patents

Dry-etching method

Info

Publication number
JPH07201826A
JPH07201826A JP35039993A JP35039993A JPH07201826A JP H07201826 A JPH07201826 A JP H07201826A JP 35039993 A JP35039993 A JP 35039993A JP 35039993 A JP35039993 A JP 35039993A JP H07201826 A JPH07201826 A JP H07201826A
Authority
JP
Japan
Prior art keywords
film
etching
tin film
tin
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP35039993A
Other languages
Japanese (ja)
Other versions
JP3202466B2 (en
Inventor
Hideyuki Shoji
秀行 庄司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Anelva Corp
NEC Corp
Original Assignee
NEC Corp
Anelva Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Anelva Corp filed Critical NEC Corp
Priority to JP35039993A priority Critical patent/JP3202466B2/en
Publication of JPH07201826A publication Critical patent/JPH07201826A/en
Application granted granted Critical
Publication of JP3202466B2 publication Critical patent/JP3202466B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/44Compositions for etching metallic material from a metallic material substrate of different composition
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/30Acidic compositions for etching other metallic material

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a dry-etching method whereby the etching rates of TiN films are increased and the formation of a through hole is performed appropriately in a multilayer wiring having the TiN films. CONSTITUTION:In the case of the etching of a multilayer metallic wiring having TiN films 103, 105, the mixture gas of SF6 with a fluorocarbon-based gas is introduced into an etching chamber, and to the space between the electrodes on one of which a semiconductor substrate having the TiN films 103, 105 is put, an RF power is fed for the TiN films to be etched. In this case, it is preferable that the flow rate of SF6 is 10-30sccm and the flow rate of CF4 as the fluorocarbon based gas is 20-60sccm and the pressure of the etching chamber is 20-60 Pa and the density of the RF power is 2.2-4.4W/cm<2>. Thereby, the etching rates of the TiN films are increased, and the depositions which can not be removed from the inner sidewall of a through hole is prevented from being generated on it.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体デバイスに用いら
れるTiN(窒化チタン)膜のドライエッチング方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method for a TiN (titanium nitride) film used for semiconductor devices.

【0002】[0002]

【従来の技術】一般に、TiN膜は半導体デバイスにお
いてアルミニウム等の金属配線のマイグレーション対策
として金属配線の上層や下層に用いられている。例え
ば、図5(a)に示す金属配線では、シリコン酸化膜5
01上にTi膜502、TiN膜503、Al−Si−
Cu膜504、TiN膜505をスパッタ技術を用いて
順に成膜を行い、その上でフォトレジスト506を塗布
し、リソグラフィ技術を用いてパターンを形成する。こ
の半導体基板を一般的なリアクティブイオンエッチング
装置により、Cl2、BCl3 等の塩素系ガスを用いて
図5(b)に示すようにTiN膜505、Al−Si−
Cu膜504、TiN膜503、Ti膜502のエッチ
ングを行い配線を形成する。
2. Description of the Related Art Generally, a TiN film is used as an upper layer or a lower layer of a metal wiring in a semiconductor device as a measure against migration of a metal wiring such as aluminum. For example, in the metal wiring shown in FIG.
01 on Ti film 502, TiN film 503, Al-Si-
A Cu film 504 and a TiN film 505 are sequentially formed using a sputtering technique, a photoresist 506 is applied thereon, and a pattern is formed using a lithography technique. As shown in FIG. 5B, a TiN film 505, an Al—Si— layer, and a TiN film 505 were formed on this semiconductor substrate by using a general reactive ion etching apparatus using chlorine-based gas such as Cl 2 and BCl 3 .
The Cu film 504, the TiN film 503, and the Ti film 502 are etched to form wiring.

【0003】しかしこのエッチング方法では、Ti膜、
TiN膜のエッチングにおいて、フォトレジスト506
に対し選択性を有し、かつ量産性を高めるために高速エ
ッチングを行おうとしてもエッチング速度は100Å/
min程度しか得られないという問題があった。この問
題を解決する方法として特開平3−239323号公報
では、CF4 とN2 、またはSF6 とN2 の混合ガスを
用いてTiN膜のエッチングをすることによりTiN膜
の高速エッチングが可能となることが示されている。
However, in this etching method, a Ti film,
In etching the TiN film, photoresist 506
The etching rate is 100Å /
There was a problem that you could only get about min. As a method for solving this problem, Japanese Patent Laid-Open No. 3-239323 discloses that the TiN film can be etched at a high speed by etching the TiN film using a mixed gas of CF 4 and N 2 or SF 6 and N 2. It has been shown that

【0004】近年、半導体デバイスの高集積化、高速化
に対応するために配線の多層構造化が求められている。
ここでも配線はストレスマイグレーション、エレクトロ
マイグレーションの防止対策として積層構造の金属配線
が適用されているが、このような積層構造では上下の各
金属配線を相互に接続するためのスルーホールを形成す
ることが要求される。図6はその工程の一部を示す図で
あり、先ず、図6(a)に示すようにシリコン酸化膜6
01上にTi膜602、TiN膜603、Al−Si−
Cu膜604、TiN膜605からなる積層構造の金属
配線を一般的なリソグラフィ技術、エッチング技術によ
り形成した後、シリコン酸化膜等の層間絶縁膜606を
成膜し、フォトレジスト607を塗布し、リソグラフィ
技術によりスルーホールのパターンを形成する。
In recent years, in order to cope with higher integration and higher speed of semiconductor devices, a multilayer structure of wiring has been required.
Here again, the wiring is applied with a laminated metal wiring as a measure for preventing stress migration and electromigration. In such a laminated structure, through holes for connecting the upper and lower metal wirings to each other can be formed. Required. FIG. 6 is a diagram showing a part of the process. First, as shown in FIG. 6A, the silicon oxide film 6 is formed.
01 on Ti film 602, TiN film 603, Al-Si-
After forming a metal wiring having a laminated structure including a Cu film 604 and a TiN film 605 by a general lithography technique or etching technique, an interlayer insulating film 606 such as a silicon oxide film is formed, a photoresist 607 is applied, and lithography is performed. A pattern of through holes is formed by a technique.

【0005】続いて、図6(b)に示すように、一般的
なRIE(リアクティブイオンエッチング)装置を用い
てCF4 ,CHF3 等のフルオロカーボン系のガスにO
2 ,Ar等の不活性ガスを添加したエッチングガスを用
いて層間絶縁膜606をエッチングし、スルーホール6
08を形成する。このとき次工程で形成を行う上層部の
配線と、下層の配線間の抵抗を抑えるために、下層配線
上部のTiN膜605も同時にエッチングを行う。最後
に、図6(c)に示すように、Al−Si−Cu膜60
9、TiN膜610を順に成膜し、一般的なリソグラフ
ィ、エッチング技術を用いて上層の配線を形成し、多層
配線が完成する。
Subsequently, as shown in FIG. 6B, a general RIE (reactive ion etching) apparatus is used to add O to a fluorocarbon-based gas such as CF 4 or CHF 3.
2 , the interlayer insulating film 606 is etched by using an etching gas to which an inert gas such as Ar is added, and the through hole 6
08 is formed. At this time, the TiN film 605 on the upper portion of the lower layer wiring is also etched at the same time in order to suppress the resistance between the upper layer wiring formed in the next step and the lower layer wiring. Finally, as shown in FIG. 6C, the Al-Si-Cu film 60 is formed.
9. A TiN film 610 is sequentially formed, and an upper wiring is formed by using a general lithography and etching technique to complete a multilayer wiring.

【0006】しかし、このスルーホールの形成方法で
は、Al−Si−Cu膜609を成膜する際に段切れが
生じ易く、配線間で短絡してしまうという問題があっ
た。またスルーホール608の形成のために層間絶縁膜
606をエッチングし、引き続きAl−Si−Cu膜6
04上のTiN膜をエッチングする際に、CF4 ,CH
3 またはこれらにO2 を添加したエッチングガスによ
るエッチングでは、TiN膜のエッチング速度は200
Å/min程度しか得られず量産性に問題があった。ま
たエッチング速度を増加させる方法としてCF4 ,CH
3 にArを添加したエッチングガスによるエッチング
ではTiN膜のエッチング速度は約500Å/minに
増加するが、TiN膜が除去されるとともにAl−Si
−Cu膜もスパッタエッチングされて、スルーホール側
壁にアルミニウム系の堆積物が付着する。この堆積物は
プラズマや薬液等の処理を行っても除去することは不可
能であり、スルーホール内に堆積物を残したままで上層
の配線を形成した場合、デバイスの信頼性が低下すると
いう問題があった。
However, this method of forming a through hole has a problem in that a step break is likely to occur when the Al-Si-Cu film 609 is formed and a short circuit occurs between wirings. Further, the interlayer insulating film 606 is etched to form the through hole 608, and then the Al--Si--Cu film 6 is formed.
When etching the TiN film on 04, CF 4 , CH
When etching with F 3 or an etching gas in which O 2 is added to these, the etching rate of the TiN film is 200
Only Å / min was obtained, and there was a problem in mass productivity. As a method of increasing the etching rate, CF 4 , CH
The etching rate of the TiN film is increased to about 500 Å / min by etching with an etching gas in which Ar is added to F 3 , but the TiN film is removed and Al-Si is removed.
The Cu film is also sputter-etched, and aluminum-based deposits adhere to the sidewalls of the through holes. This deposit cannot be removed even by treating it with plasma or chemicals, and if the upper wiring is formed with the deposit remaining in the through hole, the reliability of the device will decrease. was there.

【0007】この問題を解決する方法として特開平4−
102331号公報にスルーホールの形成方法が示され
ている。図7はその工程の一部を示す図であり、先ず、
図7(a)に示すように、シリコン酸化膜701上にA
l−Si−Cu膜702を7000Å、続いてTiN膜
703を700Å成膜する。これを一般的なリソグラフ
ィ技術及びエッチング技術により配線の形成を行う。次
いで、シリコン酸化膜等の層間絶縁膜704を成長し、
フォトレジストを塗布し露光技術によりフォトレジスト
にスルーホールパターンの形成を行い、エッチングガス
に層間絶縁膜704とTiN膜703との間でエッチン
グの選択性が得られるCHF3 等のフッ素ガスを用いて
エッチングを行いスルーホール705を形成する。
As a method for solving this problem, Japanese Unexamined Patent Publication No.
No. 102331 discloses a method of forming through holes. FIG. 7 is a diagram showing a part of the process. First,
As shown in FIG. 7A, A is formed on the silicon oxide film 701.
An l-Si-Cu film 702 is formed at 7,000 Å, and then a TiN film 703 is formed at 700 Å. Wiring is formed from this by general lithography technology and etching technology. Then, an interlayer insulating film 704 such as a silicon oxide film is grown,
A photoresist is applied, a through-hole pattern is formed in the photoresist by an exposure technique, and a fluorine gas such as CHF 3 that provides etching selectivity between the interlayer insulating film 704 and the TiN film 703 is used as an etching gas. The through hole 705 is formed by etching.

【0008】フォトレジストを除去した後、層間絶縁膜
704の表面をRIE装置を用い、Arによるスパッタ
エッチングを行う。この結果、図7(b)に示すように
スルーホール開口部にほぼ45°のテーパー状側壁面が
形成される。最後にAl−Si−Cu膜702との間で
エッチングの選択性の得られるSF6 等のフッ素系ガス
によりエッチングを行うことにより、図7(c)に示す
ようにスルーホール705の底面にはTiN膜及び堆積
物の無いAl−Si−Cu面を表出することが可能とな
る。また、スルーホール705の開口部をArスパッタ
エッチングによりテーパー形状としているので次工程の
配線形成において段切れ無い配線の形成が可能となる。
After removing the photoresist, the surface of the interlayer insulating film 704 is sputter-etched by Ar using an RIE apparatus. As a result, as shown in FIG. 7B, a tapered side wall surface of approximately 45 ° is formed in the through hole opening. Finally, etching is performed with a fluorine-based gas such as SF 6 which provides etching selectivity between the Al-Si-Cu film 702 and the bottom surface of the through hole 705 as shown in FIG. 7C. It is possible to expose the Al-Si-Cu surface without the TiN film and the deposit. Further, since the opening of the through hole 705 is formed into a taper shape by Ar sputter etching, it is possible to form a wiring without breaks in the wiring formation in the next step.

【0009】[0009]

【発明が解決しようとする課題】しかし、特開平3−2
39323号公報に示されているCF4 ,N2 によるT
iN膜のエッチングでは200〜250Å/min程度
しかエッチング速度は得られないため、CF4 ,CHF
3 によるTiN膜のエッチングと同様に量産性に問題が
あった。またSF6 ,N2 によるTiN膜のエッチング
ではTiN膜が基板に対し平行方向にもエッチングが進
行してしまうためにストレスマイグレーション、エレク
トロマイグレーション耐性が低下するという問題があっ
た。
However, Japanese Unexamined Patent Publication No. 3-2.
T by CF 4 , N 2 shown in Japanese Patent No. 39323
Since an etching rate of only about 200 to 250 Å / min can be obtained by etching the iN film, CF 4 , CHF
Similar to the etching of the TiN film by 3 , there was a problem in mass productivity. Further, the etching of the TiN film by SF 6 and N 2 has a problem that the resistance to stress migration and electromigration is lowered because the etching of the TiN film progresses in the direction parallel to the substrate.

【0010】また、特開平4−102331号公報に示
されているスルーホールの形成方法では、RIE装置に
よるArスパッタエッチングを行った場合、陰極降下電
圧によりArはエネルギを有するため、基板面に対して
垂直方向のエッチング速度が殆ど0となることはない。
つまりArスパッタエッチングにより層間絶縁膜と共に
TiN膜もエッチングされてしまい、最後にはAl−S
i−Cu膜もスパッタエッチングされてスルーホール側
壁に堆積し、この堆積物706はいかなる処理を施して
も除去できないために、デバイスの信頼性を低下させる
という問題があった。またTiN膜のエッチングをSF
6 単独で行った場合、TiN膜が基板に対し平行方向に
もエッチングが進行してしまい、スルーホールを開口す
る以外のAl−Si−Cu配線上のTiN膜もエッチン
グしてしまうために、ストレスマイグレーション、エレ
クトロマイグレーション耐性が低下するという問題があ
った。本発明の目的は、エッチング速度の高速化を図る
とともに、スルーホールの形成時においてもその側壁に
除去不可能な反応生成物を堆積させることがないドライ
エッチング方法を提供することにある。
Further, in the method of forming a through hole disclosed in Japanese Patent Application Laid-Open No. 4-102331, when Ar sputter etching is performed by the RIE apparatus, Ar has energy due to the cathode drop voltage, so that the substrate surface is affected. Therefore, the etching rate in the vertical direction hardly becomes zero.
That is, the TiN film is etched together with the interlayer insulating film by Ar sputter etching, and finally the Al-S film is formed.
The i-Cu film is also sputter-etched and deposited on the side wall of the through hole, and since the deposit 706 cannot be removed by any treatment, there is a problem that the reliability of the device is lowered. In addition, etching of the TiN film is performed by SF
6 If it is performed alone, the etching of the TiN film also progresses in the direction parallel to the substrate, and the TiN film on the Al-Si-Cu wiring other than the opening of the through hole is also etched. There is a problem that the resistance to migration and electromigration is reduced. An object of the present invention is to provide a dry etching method for increasing the etching rate and preventing deposition of irremovable reaction products on the sidewalls of through holes even when they are formed.

【0011】[0011]

【課題を解決するための手段】本発明のドライエッチン
グ方法は、TiN膜をSF6 とフルオロカーボン系ガス
の混合ガスを用いてエッチングする。この場合、TiN
膜を含む積層膜の金属配線をエッチングする際、或いは
TiN膜を含む積層膜の配線間の接続部を形成するに際
して、層間膜をエッチングし、続いて積層膜の上層を形
成しているTiN膜をエッチングする際に適用される。
例えば、本発明のドライエッチング方法は、チャンバ内
に一対の電極を有し、このチャンバ内にSF6 とフルオ
ロカーボン系ガスの混合ガスを導入し、一方の電極にT
iN膜を有する半導体基板が載置され、かつ両電極間に
RF電力を供給してTiN膜のエッチングを行う。この
場合、SF6 の流量が10〜30sccm、フルオロカ
ーボン系ガスとしてCF4 の流量が20〜60scc
m、圧力が20〜60Pa、RFパワー密度が2.2〜
4.4W/cm2 であることが好ましい。
According to the dry etching method of the present invention, a TiN film is etched using a mixed gas of SF 6 and a fluorocarbon type gas. In this case, TiN
When etching the metal wiring of the laminated film including the film or forming the connection portion between the wiring of the laminated film including the TiN film, the interlayer film is etched and subsequently the TiN film forming the upper layer of the laminated film is formed. Applied when etching.
For example, the dry etching method of the present invention has a pair of electrodes in a chamber, a mixed gas of SF 6 and a fluorocarbon-based gas is introduced into the chamber, and T
A semiconductor substrate having an iN film is placed, and RF power is supplied between both electrodes to etch the TiN film. In this case, the flow rate of SF 6 is 10 to 30 sccm, and the flow rate of CF 4 as the fluorocarbon gas is 20 to 60 sccc.
m, pressure 20 to 60 Pa, RF power density 2.2 to
It is preferably 4.4 W / cm 2 .

【0012】[0012]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明のドライエッチング方法を積層構造の
金属配線の形成に適用したときの半導体基板の模式断面
図である。まず、図1(a)に示すようにシリコン酸化
膜101上に、300Åの膜厚のTi膜102と、10
00Åの膜厚のTiN膜103と、5000Åの膜厚の
Al−Si−Cu膜104と、250Åの膜厚のTiN
膜105を順次スパッタ法により成膜を行なう。そし
て、フォトレジスト106を塗布し、リソグラフィ技術
によりパターンを形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor substrate when the dry etching method of the present invention is applied to the formation of metal wiring having a laminated structure. First, as shown in FIG. 1A, a Ti film 102 having a film thickness of 300 Å and a 10
A TiN film 103 having a film thickness of 00Å, an Al-Si-Cu film 104 having a film thickness of 5000Å, and a TiN film having a film thickness of 250Å
The film 105 is sequentially formed by a sputtering method. Then, a photoresist 106 is applied and a pattern is formed by a lithographic technique.

【0013】続いて、この半導体基板を図2に示すカソ
ードカップル型RIE装置を用いてエッチングを行う。
このRIE装置は、上部にガス供給を有するチャンバ2
01の内部に上部電極202と下部電極203を備え、
下部電極203にはマッチングボックス204を介して
RF電源205が接続されている。そして、半導体基板
Wは下部電極203上に載置する。
Subsequently, this semiconductor substrate is etched using the cathode couple type RIE apparatus shown in FIG.
This RIE device has a chamber 2 having a gas supply at the top.
01 is provided with an upper electrode 202 and a lower electrode 203 inside,
An RF power source 205 is connected to the lower electrode 203 via a matching box 204. Then, the semiconductor substrate W is placed on the lower electrode 203.

【0014】このエッチングに際しては、初めに、エッ
チングガスとして、SF6 (流量10sccm)とCF
4 (流量20sccm)、圧力20Pa、RFパワー密
度3.3W/cm2 の条件でTiN膜105のエッチン
グを行う。続いて、Cl2 (流量30sccm)とBC
3 (流量70sccm)、圧力30Pa、RFパワー
密度3.8W/cm2 の条件でAl−Si−Cu膜10
4のエッチングを行う。更に、TiN膜103はTiN
膜105と同じエッチング条件で、最後にTiN膜10
2はAl−Si−Cu膜104と同じエッチング条件で
それぞれエッチングを行う。これにより、図1(b)の
ように所要パターンの金属配線が形成される。
In this etching, first, SF 6 (flow rate 10 sccm) and CF are used as etching gas.
The TiN film 105 is etched under the conditions of 4 (flow rate 20 sccm), pressure 20 Pa, and RF power density 3.3 W / cm 2 . Subsequently, Cl 2 (flow rate 30 sccm) and BC
Al—Si—Cu film 10 under the conditions of l 3 (flow rate 70 sccm), pressure 30 Pa, and RF power density 3.8 W / cm 2.
Etching 4 is performed. Further, the TiN film 103 is made of TiN.
Under the same etching conditions as the film 105, finally the TiN film 10
2 is etched under the same etching conditions as the Al-Si-Cu film 104. As a result, metal wiring having a required pattern is formed as shown in FIG.

【0015】図3は前記したTiN膜のエッチングに際
しての、エッチング速度のCF4 流量依存性を示してい
るが、エッチング速度は2000〜3000Å/min
となっており、従来技術に比べて10倍以上のエッチン
グ速度が得られていることが分かる。ここで、本発明者
の検討によれば、TiN膜を高速のエッチング速度でエ
ッチング可能な条件は、上記のエッチング条件に限ら
ず、SF6 (流量10〜30sccm)、CF4 (流量
20〜60sccm)、圧力20〜60Pa、RFパワ
ー密度2.2〜4.4W/cm2 の範囲の適当な組み合
わせにより、エッチング速度1500Å/min以上の
TiN膜のエッチングが可能であることが確認されてい
る。また、CF4 の他にCHF3 を用いても同等の性能
を得ることが可能である。
FIG. 3 shows the CF 4 flow rate dependency of the etching rate when etching the TiN film described above. The etching rate is 2000 to 3000 Å / min.
It can be seen that the etching rate is 10 times or more that of the conventional technique. Here, according to the study by the present inventor, the conditions under which the TiN film can be etched at a high etching rate are not limited to the above etching conditions, but SF 6 (flow rate 10 to 30 sccm) and CF 4 (flow rate 20 to 60 sccm). ), A pressure of 20 to 60 Pa, and an RF power density of 2.2 to 4.4 W / cm 2 in an appropriate combination, it has been confirmed that the TiN film can be etched at an etching rate of 1500 Å / min or more. Further, it is possible to obtain equivalent performance by using CHF 3 in addition to CF 4 .

【0016】図4は本発明のドライエッチング方法をス
ルーホールの形成に適用したときの半導体基板の模式断
面図である。先ず、図4(a)に示すように、シリコン
酸化膜401上にTi膜402、TiN膜403、Al
−Si−Cu膜404、TiN膜405をスパッタによ
り成膜を行い、リソグラフィ技術及びエッチング技術に
より積層構造の配線を形成する。次にシリコン酸化膜等
の層間絶縁膜404を成膜し、フォトレジスト407を
塗布してリソグラフィ技術によりスルーホールパターン
を形成する。そして、HF液等により層間絶縁膜406
の膜厚の40〜60%を等方的にエッチングを行う。こ
のときのエッチングはHF液等のウェットエッチングの
他に、CF4 、O2 によるRIE処理でも可能である。
FIG. 4 is a schematic sectional view of a semiconductor substrate when the dry etching method of the present invention is applied to the formation of through holes. First, as shown in FIG. 4A, a Ti film 402, a TiN film 403, and an Al film are formed on the silicon oxide film 401.
A —Si—Cu film 404 and a TiN film 405 are formed by sputtering, and a wiring having a laminated structure is formed by a lithography technique and an etching technique. Next, an interlayer insulating film 404 such as a silicon oxide film is formed, a photoresist 407 is applied, and a through hole pattern is formed by a lithography technique. Then, the interlayer insulating film 406 is formed by HF liquid or the like.
Isotropically etched to 40 to 60% of the film thickness. The etching at this time can be performed by wet etching with an HF solution or the like, or by RIE treatment with CF 4 or O 2 .

【0017】この半導体基板を図2に示したカソードカ
ップル型RIE装置を用いてエッチングを行う。即ち、
図4(b)に示すように、層間絶縁膜406をTiN膜
405に対し選択的にエッチングすることが可能な条件
であるCF4 (流量20sccm)、CHF3 (流量4
0sccm)、圧力20Pa、RFパワー密度5.5W
/cm2 でエッチングを行う。引き続き、TiN膜405
をSF6 (流量10sccm)、CF4 (流量20sc
cm)、圧力20Pa、RFパワー密度3.3W/cm
2 の条件でエッチングを行う。
This semiconductor substrate is etched using the cathode couple type RIE apparatus shown in FIG. That is,
As shown in FIG. 4B, CF 4 (flow rate 20 sccm) and CHF 3 (flow rate 4) are conditions under which the interlayer insulating film 406 can be selectively etched with respect to the TiN film 405.
0sccm), pressure 20Pa, RF power density 5.5W
Etching is performed at / cm 2 . Next, TiN film 405
SF 6 (flow rate 10 sccm), CF 4 (flow rate 20 sccm)
cm), pressure 20 Pa, RF power density 3.3 W / cm
Etching is performed under the condition of 2 .

【0018】しかる後、フォトレジスト407を除去し
た後、図4(c)に示すように、Al−Si−Cu膜4
09、TiN膜410を順に成膜し、一般的なリソグラ
フィ、エッチング技術を用いて上層の配線を形成し、多
層配線が完成する。この実施例では、スルーホール40
8の形成において初めに等方性エッチングを行っている
ので上層の配線を形成する際に段切れが生じないこと。
またスルーホール408の形成により露出するTiN膜
405を従来に比べて高速でエッチングを行い、かつス
ルーホール408の側壁に反応生成物を堆積させること
がないので、デバイスの信頼性を従来よりも大幅に向上
することが可能である。
Then, after removing the photoresist 407, as shown in FIG. 4C, the Al-Si-Cu film 4 is formed.
09 and a TiN film 410 are sequentially formed, an upper wiring is formed by using a general lithography and etching technique, and a multi-layer wiring is completed. In this embodiment, the through hole 40
Since isotropic etching is first performed in the formation of No. 8, step disconnection does not occur when forming the wiring of the upper layer.
Further, since the TiN film 405 exposed by the formation of the through hole 408 is etched at a higher speed than in the past and the reaction product is not deposited on the sidewall of the through hole 408, the reliability of the device is greatly improved as compared with the conventional one. It is possible to improve.

【0019】[0019]

【発明の効果】以上説明したように本発明は、TiN
膜、或いはTiN膜を含む金属配線の積層膜をSF6
フルオロカーボン系ガスの混合ガスを用いてエッチング
することにより、高速のエッチングが実現できる効果が
ある。特に、積層構造の配線間の接続部であるスルーホ
ールの形成においてTiN膜をエッチングする際に、ス
ルーホール側壁に除去することが不可能な反応生成物を
堆積させることがないので、従来に比べてデバイスの信
頼性を大幅に向上することが可能であるという効果もあ
る。また、チャンバ内に一対の電極を有し、このチャン
バ内にSF6 とフルオロカーボン系ガスの混合ガスを導
入し、一方の電極にTiN膜を有する半導体基板が載置
され、かつ両電極間にRF電力を供給してTiN膜のエ
ッチングを行うドライエッチングに際し、SF6 の流量
が10〜30sccm、フルオロカーボン系ガスとして
CF4 の流量が20〜60sccm、圧力が20〜60
Pa、RFパワー密度が2.2〜4.4W/cm2 に設
定することにより、高速でかつ除去不可能な反応生成物
を堆積することがないエッチングが実現できる。
As described above, according to the present invention, the TiN
By etching a film or a laminated film of metal wiring including a TiN film using a mixed gas of SF 6 and a fluorocarbon-based gas, there is an effect that high-speed etching can be realized. In particular, when a TiN film is etched in forming a through hole that is a connecting portion between wirings of a laminated structure, a reaction product that cannot be removed is not deposited on the side wall of the through hole. This also has the effect of significantly improving the reliability of the device. In addition, a chamber has a pair of electrodes, a mixed gas of SF 6 and a fluorocarbon-based gas is introduced into the chamber, a semiconductor substrate having a TiN film is placed on one of the electrodes, and an RF electrode is placed between the electrodes. In dry etching in which electric power is supplied to etch the TiN film, the flow rate of SF 6 is 10 to 30 sccm, the flow rate of CF 4 as a fluorocarbon-based gas is 20 to 60 sccm, and the pressure is 20 to 60.
By setting the Pa and RF power densities to 2.2 to 4.4 W / cm 2 , it is possible to realize etching at high speed without depositing an irremovable reaction product.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のエッチング方法を工程順に示す模式的
な断面図である。
FIG. 1 is a schematic cross-sectional view showing an etching method of the present invention in the order of steps.

【図2】本発明方法を実施するためのRIE装置の概略
構成図である。
FIG. 2 is a schematic configuration diagram of an RIE device for carrying out the method of the present invention.

【図3】本発明方法におけるTiNのエッチング速度と
ガス流量との関係を示す図である。
FIG. 3 is a diagram showing a relationship between a TiN etching rate and a gas flow rate in the method of the present invention.

【図4】本発明のエッチング方法によりスルーホールを
形成する工程を示す断面図である。
FIG. 4 is a cross-sectional view showing a step of forming a through hole by the etching method of the present invention.

【図5】従来のエッチング方法を工程順に示す断面図で
ある。
FIG. 5 is a cross-sectional view showing a conventional etching method in the order of steps.

【図6】従来のスルーホールの形成方法を工程順に示す
断面図である。
FIG. 6 is a cross-sectional view showing a method of forming a conventional through hole in the order of steps.

【図7】従来の改善されたスルーホールの形成方法を工
程順に示す断面図である。
FIG. 7 is a cross-sectional view showing a conventional improved through-hole forming method in process order.

【符号の説明】[Explanation of symbols]

101 シリコン酸化膜 102 Ti膜 103 TiN膜 104 Al−Si−Cu膜 105 TiN膜 101 Silicon oxide film 102 Ti film 103 TiN film 104 Al-Si-Cu film 105 TiN film

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 // C23F 4/00 E 8417−4K Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI technical display area // C23F 4/00 E 8417-4K

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 TiN膜をSF6 とフルオロカーボン系
ガスの混合ガスを用いてエッチングすることを特徴とす
るドライエッチング方法。
1. A dry etching method comprising etching a TiN film using a mixed gas of SF 6 and a fluorocarbon-based gas.
【請求項2】 TiN膜を含む積層膜の金属配線をエッ
チングする請求項1のドライエッチング方法。
2. The dry etching method according to claim 1, wherein the metal wiring of the laminated film including the TiN film is etched.
【請求項3】 TiN膜を含む積層膜の配線間の接続部
を形成するに際して、層間膜をエッチングし、続いて積
層膜の上層を形成しているTiN膜をSF6とフルオロ
カーボン系ガスの混合ガスを用いてエッチングすること
を特徴とするドライエッチング方法。
3. When forming a connection portion between wirings of a laminated film containing a TiN film, the interlayer film is etched, and then the TiN film forming the upper layer of the laminated film is mixed with SF 6 and a fluorocarbon-based gas. A dry etching method characterized by etching using a gas.
【請求項4】 チャンバ内に一対の電極を有し、このチ
ャンバ内にSF6 とフルオロカーボン系ガスの混合ガス
を導入し、一方の電極にTiN膜を有する半導体基板が
載置され、かつ両電極間にRF電力を供給してTiN膜
のエッチングを行うドライエッチング方法。
4. A chamber is provided with a pair of electrodes, a mixed gas of SF 6 and a fluorocarbon-based gas is introduced into the chamber, and a semiconductor substrate having a TiN film is placed on one of the electrodes, and both electrodes are placed. A dry etching method in which RF power is supplied to etch the TiN film.
【請求項5】 SF6 の流量が10〜30sccm、フ
ルオロカーボン系ガスとしてCF4 の流量が20〜60
sccm、圧力が20〜60Pa、RFパワー密度が
2.2〜4.4W/cm2 である請求項4のドライエッ
チング方法。
5. The flow rate of SF 6 is 10 to 30 sccm, and the flow rate of CF 4 as the fluorocarbon gas is 20 to 60.
The dry etching method according to claim 4, wherein the sccm is 20 to 60 Pa, the RF power density is 2.2 to 4.4 W / cm 2 .
JP35039993A 1993-12-28 1993-12-28 Dry etching method Expired - Fee Related JP3202466B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35039993A JP3202466B2 (en) 1993-12-28 1993-12-28 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35039993A JP3202466B2 (en) 1993-12-28 1993-12-28 Dry etching method

Publications (2)

Publication Number Publication Date
JPH07201826A true JPH07201826A (en) 1995-08-04
JP3202466B2 JP3202466B2 (en) 2001-08-27

Family

ID=18410234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35039993A Expired - Fee Related JP3202466B2 (en) 1993-12-28 1993-12-28 Dry etching method

Country Status (1)

Country Link
JP (1) JP3202466B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162287A (en) * 1995-12-11 1997-06-20 Nec Corp Manufacture of semiconductor device
JPH09232424A (en) * 1996-02-21 1997-09-05 Nec Kyushu Ltd Manufacture of semiconductor device
JP2003347276A (en) * 2003-06-30 2003-12-05 Hitachi Ltd Plasma treatment method and method for manufacturing semiconductor device
KR20040001487A (en) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 emthod for etching metal layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162287A (en) * 1995-12-11 1997-06-20 Nec Corp Manufacture of semiconductor device
JPH09232424A (en) * 1996-02-21 1997-09-05 Nec Kyushu Ltd Manufacture of semiconductor device
KR20040001487A (en) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 emthod for etching metal layer
JP2003347276A (en) * 2003-06-30 2003-12-05 Hitachi Ltd Plasma treatment method and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP3202466B2 (en) 2001-08-27

Similar Documents

Publication Publication Date Title
US5786272A (en) Metallization over tungsten plugs
JP3291889B2 (en) Dry etching method
JPH10223608A (en) Manufacture of semiconductor device
JPH10223760A (en) Method for formation of air gap by plasma treatment of aluminum interconnection
JP3781175B2 (en) Contact hole formation method
JP3202466B2 (en) Dry etching method
JPH0487332A (en) Manufacture of semiconductor integrated circuit device
JP2003124312A (en) Semiconductor device and method for manufacturing the same
JP2754578B2 (en) Etching method
JPH08186120A (en) Manufacture of semiconductor device
JPH11238732A (en) Wiring structure and formation of bonding pad opening
JPH09232424A (en) Manufacture of semiconductor device
JP2776727B2 (en) Method for manufacturing semiconductor device
JPH05182937A (en) Dry-etching method
JP3135020B2 (en) Method of manufacturing multilayer wiring structure
JP2000299376A (en) Semiconductor device and manufacturing method
JP3541329B2 (en) Dry etching method
JP4207284B2 (en) Manufacturing method of semiconductor device
JP2003197737A (en) Method for manufacturing semiconductor device
JPH09134959A (en) Formation of wiring plug
JP2001015494A (en) Manufacture of semiconductor device and etching method
JP2002246393A (en) Method of forming metal wiring
JPH04313255A (en) Formation of interconnection
JP2000133711A (en) Semiconductor device and its manufacture
JP3495492B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees