JP2003197737A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having highly reliable wiring layers. <P>SOLUTION: The manufacturing method comprises a process of forming the first wiring layer 30 with a predetermined pattern, a process of forming the second interlayer insulation layer 40 above the first wiring layer 30, a process of forming a sacrifice layer 50 above the second interlayer insulation layer 40, a process of forming a through-hole 60 in the second interlayer insulation layer 40 and the sacrifice layer 50, a process of forming an electrically conductive layer 72 which is a contact layer 70 in the through-hole 60, and a process of removing at least a part of the sacrifice layer 50 or the contact layer 70 in the through-hole 60 formed in the sacrifice layer 50. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device characterized by forming a contact layer.

[0002]

BACKGROUND ART As a technique for forming a contact layer that interconnects wirings of different layers, there are the following techniques, for example.

This technique will be described with reference to FIG. The first interlayer insulating layer 212 is formed on the semiconductor substrate 210 on which semiconductor elements and the like are formed. A first conductive layer is formed on the first interlayer insulating layer 212, and the first conductive layer is patterned by lithography and dry etching to form the lower wiring layer 220. The second interlayer insulating layer 23 is formed on the lower wiring layer 220 and the first interlayer insulating layer 212.
Form 0.

Then, a resist layer having a predetermined pattern is formed on the second interlayer insulating layer 230. The resist layer has an opening above a region where a through hole is desired to be formed. Using the resist layer as a mask, the second interlayer insulating layer 230 is dry-etched to form the lower wiring layer 22.
A through hole 240 reaching 0 is formed.

Next, the through hole 240 is filled with a conductive material to form a contact layer 250. A second conductive layer is formed on the second interlayer insulating layer 230 and the contact layer 250, and by lithography and dry etching,
The second conductive layer is patterned to form the upper wiring layer 260.

In the above-mentioned technique, in order to reduce and stabilize the contact resistance, in the through hole, before the contact layer is formed, the damage due to the etching at the time of forming the through hole, the recovery of heavy metal, carbon, Sometimes mixed impurities such as oxygen and fluorine are removed, or etching products are removed. In order to remove the damage layer and the mixed impurities or etching products by etching, the surface inside the through hole is slightly oxidized and these layers are taken in, the oxide is etched, and the reactive gas is used by dry etching. There are a method of lightly etching only the surface layer, a method of physically removing it by sputter etching with a gas such as argon, and the like.

[0007]

If, for example, sputter etching using a gas such as argon is used in order to remove impurities contained in the through holes and the like, FIG.
As shown in FIG. 5, the upper end of the through hole 240 is shaved to form the tapered side surface 300, and the diameter of the upper portion of the through hole 240 becomes larger than the diameter of the lower portion thereof. Then, after filling the through hole 240 with the contact layer 250 and forming the upper wiring layer 260 thereon, the contact layer 25 is formed.
At 0, a part 310 which is exposed without being covered with the upper wiring layer 260 may be formed. In particular, in a device that is miniaturized, the contact layer 250 having the exposed portion 310 because the pitch between the wirings is small,
This may cause a device problem such as a short circuit with an adjacent wiring layer.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a highly reliable wiring layer.

[0009]

A method of manufacturing a semiconductor device according to the present invention includes the following steps (a) to (f).

(A) forming a wiring layer having a predetermined pattern, (b) forming an interlayer insulating layer above the wiring layer, (c) forming a sacrificial layer above the interlayer insulating layer. Forming step, (d) forming a through hole in the interlayer insulating layer and the sacrificial layer, (e) forming a contact layer in the through hole, and (f)
Removing at least a portion of the sacrificial layer and the contact layer in the through hole formed in the sacrificial layer.

According to the method of manufacturing a semiconductor device of the present invention,
The through hole is formed so as to penetrate the interlayer insulating layer and the sacrificial layer. Then, after forming a conductive layer inside the through hole, at least a part of the sacrificial layer and the contact layer inside the through hole formed in the sacrificial layer are removed. Thus, when the diameter of the upper portion of the through hole is formed to be wider than the predetermined shape, that portion is removed, so that it is possible to prevent a problem such as a short circuit with an adjacent wiring. The present invention can have the following aspects.

The step (d) further includes (g) forming a taper on a side surface of the through hole so that a diameter of an upper end portion of the through hole becomes larger than a diameter of a lower portion. be able to.

The step (g) can be performed by sputter etching for removing impurities mixed in the through holes.

A conductive layer can be used as the sacrificial layer. In that case, in the step (f), it is possible to remove all of the sacrificial layer and the contact layer in the through hole formed in the sacrificial layer.

An insulating layer may be used as the sacrificial layer.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. 1 to 7 are cross-sectional views schematically showing the manufacturing process of the present invention. (First Embodiment) In the first embodiment, a case where the sacrificial layer is an insulating layer will be described.

(1) Formation of First Wiring Layer First, description will be given with reference to FIG. A semiconductor element (eg, MOSF) is formed on the surface of the substrate 10 by a general method.
ET), a wiring layer, and an element isolation region (not shown) are formed. The first interlayer insulating layer 20 is formed on the substrate 10. The first interlayer insulating layer 20 can be formed by a known method. For example, the first interlayer insulating layer 20 can be formed in the same manner as the second interlayer insulating layer 40 described later with respect to the forming method, material, film thickness, and the like. A contact hole (not shown) is formed in the first interlayer insulating layer 20 by anisotropic reactive ion etching (RIE). A contact layer (not shown) such as a tungsten plug or an aluminum alloy layer is formed in the contact hole by a known method.

First wiring layer 30 is formed on first interlayer insulating layer 20 and contact layer, for example, as follows.

A conductive layer for the first wiring layer 30 is formed on the first interlayer insulating layer 20 and the contact layer. The conductive layer is formed by, for example, a sputtering method. The material of the conductive layer is, for example, a laminated structure of titanium nitride, Al-Cu, and titanium nitride, and the film thickness is about 30 nm and about 25 nm, respectively.
0 nm and about 23 nm. The thickness of the conductive layer is 100 to 1000 nm, though it varies depending on the device design.
The material of the conductive layer is not particularly limited, and examples thereof include aluminum, copper, aluminum alloys, copper alloys, polycrystalline silicon, tungsten, and laminated films of these, in addition to the above. As a method of forming the first conductive layer, a CVD method,
A vapor deposition method, a coating method, etc. can be mentioned.

Next, a resist layer having a predetermined pattern is formed on the conductive layer by lithography, and dry etching is performed to form a pattern. This dry etching can be performed, for example, by anisotropic dry etching, and as an etchant, for example, C
A mixed gas of l ₂ / BCl ₃ / Ar is used. Then, the resist layer is removed by ashing removal or the like, and washed with an organic stripping solution. In this way, the first wiring layer 30 is formed.

(2) Formation of Second Interlayer Insulating Layer Next, as shown in FIG. 2, a second wiring layer 30 is formed on the first wiring layer 30 and the first interlayer insulating layer 20 so as to cover the first wiring layer 30.
The interlayer insulating layer 40 is formed as follows. The second interlayer insulating layer 40 is formed by, for example, high density plasma CVD method using FSG (Fluorine-doped Silica).
te Glass) and plasma CVD
It is obtained by stacking TEOS oxide films by the method. The film thickness of FSG is, for example, about 400 nm and TE
The film thickness of the OS oxide film is about 1000 nm. afterwards,
If necessary, it can be flattened by a CMP method or the like. In this embodiment, the second interlayer insulating layer 40 is flattened by the CMP method until the film thickness becomes about 550 nm.

The thickness of the second interlayer insulating layer 40 is preferably 400 to 2500 nm before planarization, for example, 400 to 2500 nm based on the upper surface of the first wiring layer 30, and 400 to 2000 nm after planarization. Preferably there is.

As the material of the second interlayer insulating layer 40, other materials such as silicon oxide and silicon oxide containing phosphorus can be used.

As a method of forming the second interlayer insulating layer 40,
In addition to the above-mentioned methods, a thermal CVD method, an atmospheric pressure CVD method, a coating method (method using SOG) such as a spin coating method, a sputtering method, a thermal vapor deposition method and the like can be mentioned.

(3) Formation of Sacrificial Layer As shown in FIG. 2, a sacrificial layer 50 is formed on the second interlayer insulating layer 40. The sacrificial layer 50 is, for example, plasma C
It is formed by the VD method and uses a nitride film as the material. The thickness of the sacrificial layer 50 is about 100 nm, but is not limited to this, and is sufficient to include the tapered side surface 62 (see FIG. 4) formed during sputter etching in a later step. It is desirable to have Sacrificial layer 50
In addition to the above-mentioned method, the thermal CVD method and atmospheric pressure C
A coating method (method using SOG) such as a VD method or a spin coating method, a sputtering method, or a thermal evaporation method can be used. As the material of the sacrificial layer 50, silicon oxide or the like can be used in addition to the above.

(4) Formation of Through Hole Next, as shown in FIG. 3, a resist layer R1 having a predetermined pattern is formed on the sacrificial layer 50 by lithography. The resist layer R1 has an opening above the first wiring layer 30. That is, the resist layer R1
Has an opening above the region of the sacrificial layer 50 where the through hole 60 is desired to be formed.

Next, using the resist layer R1 as a mask, the sacrificial layer 50 and the second interlayer insulating layer 40 are etched by the following method, for example.

First, the sacrifice layer 50 is etched until the upper surface of the second interlayer insulating layer 40 is exposed. The sacrifice layer 50 is etched by, for example, anisotropic dry etching, and as an etchant, CHF ₃ / O ₂ /
Ar mixed gas is used. Next, the second interlayer insulating layer 40 is subsequently etched. Similar to the etching of the sacrificial layer 50, this etching method is performed by anisotropic dry etching, and the etchant is C ₄ H ₈ / O ₂ /
Performed with an Ar / CO mixed gas. The dry etching method is not limited to the above method, and reactive ion etching, inductively coupled plasma etching, or ECR plasma etching can be used. The etchant is not limited to the above-mentioned ones, and known ones such as a mixed gas containing a CF-based gas can be used according to the material of the sacrificial layer.

After the through hole 60 penetrating the second interlayer insulating layer 40 and the sacrificial layer 50 is formed in this way, the resist layer R1 is removed by ashing removal or the like, and washed with an organic stripping solution.

(5) Pretreatment for Forming Contact Layer Next, as pretreatment for embedding the conductive layer 72 (see FIG. 5) in the through hole 60, for example, sputtering with an inert gas such as argon gas is performed. Etch.

By this sputter etching, the natural oxide film on the surface of the first wiring layer 30 forming the bottom of the through hole 60 is removed and the clean wiring surface is exposed, so that a good contact layer described later can be obtained. Electrical contact can be obtained. Sputter etching is a method of physically performing etching by the sputtering effect of inert gas ions that does not involve a chemical reaction. Therefore, FIG.
As shown in FIG. 5, the side surface of the upper end of the through hole 60 is shaved to form a tapered side surface 62 in the sacrificial layer 50.

(6) Formation of Contact Layer Next, the contact layer 70 is formed in the through hole 60 by the following method.

In this step, it is preferable to continuously perform the process without exposing the wafer to the atmosphere after the process of the step (5) is completed. First, in the through hole 60,
A wetting layer and a barrier layer 64 are formed. The wetting layer is formed by, for example, a sputtering method, and its material is titanium. The barrier layer is, for example,
TDMAT (Tetrakis Di-Methyl)
CV using Amino Titanium) as source gas
Titanium nitride can be formed by the D method.

Next, as shown in FIG.
A conductive layer 72 is formed so as to fill the inside of 0. Conductive layer 7
2 is, for example, WF₆Is used as a source gas by the CVD method.
Formed. Then, it is formed above the sacrificial layer 50.
Even if the conductive layer 72 and at least a part of the sacrificial layer 50 are
For example, it is removed by etch back or CMP method.
It At this time, the sacrificial layer 50 has the tapered side surface 62.
Preferably removed to the extent that there are no existing areas
Yes. When performing etch back, for example, source gas
To SF₆/ Ar to form conductive layer 72 and barrier layer
Removed, CH₂F ₂/ Ar / O₂Sacrificial layer 5 with mixed gas
Remove 0.

As the conductive layer 72, for example, tungsten, aluminum, aluminum alloy, copper or copper alloy can be used. As a method of filling the conductive layer 72 in the through hole 60, a CVD method, a PVD method, a plating method and the like can be mentioned.

(7) Formation of Second Wiring Layer Next, as shown in FIG. 7, a second conductive layer is formed on the second interlayer insulating layer 40 and the contact layer 70. The film thickness, formation method, material and the like are similar to those of the above-described first conductive layer, for example. Then, patterning is performed by lithography and dry etching to form the second wiring layer 80, and the semiconductor device 100 according to the present invention is obtained.

In this embodiment, the through hole 60 is
After penetrating the second interlayer insulating layer 40 and the sacrificial layer 50 and burying the conductive layer 72 in the through hole 60, CMP is performed.
Alternatively, the conductive layer 72 and the sacrificial layer 50 are etched back.
Is removed to form the contact layer 70. As a result, the tapered side surface 62 is formed in the through hole 60 by the sputter etching or the like in the step (5).
When the is formed, the portion where the tapered side surface 62 is formed can be removed. That is, it is possible to prevent the problem that the through hole 60 is formed to have a diameter larger than a predetermined diameter and short-circuits with the adjacent wiring.

Further, since the sacrificial layer 50 is composed of an insulating layer such as silicon oxide or silicon nitride, it is not necessary to remove all of the sacrificial layer 50 formed in the step (6). The portion where the side surface 62 is formed can be removed, and the remaining sacrificial layer 50 can be left. (Second Embodiment) In the second embodiment, the case where the sacrificial layer is a conductive layer will be described.

Steps (1) and (2) are performed in the same manner as in the first embodiment.

(3) Formation of Sacrificial Layer As shown in FIG. 2, a sacrificial layer 50 is formed on the second interlayer insulating layer 40. The sacrificial layer 50 is formed by, for example, a sputtering method, and the material thereof is titanium nitride. The thickness of the sacrificial layer 50 is about 50 nm, but is not limited to this, and is sufficient to include the tapered side surface 62 (see FIG. 4) formed during sputter etching in a later step. It is desirable to have As a method for forming the sacrificial layer 50, a coating method (method utilizing SOG) such as an atmospheric pressure CVD method, a spin coating method, or a vapor deposition method can be used in addition to the above method. As the material of the sacrificial layer 50, titanium, tungsten, or the like can be used in addition to the above.

(4) Formation of Through Hole Next, as shown in FIG. 3, a resist layer R1 having a predetermined pattern is formed on the sacrificial layer 50 by lithography. The resist layer R1 has an opening above the first wiring layer 30. That is, the resist layer R1
Has an opening above the region of the sacrificial layer 50 where the through hole 60 is desired to be formed.

Next, using the resist layer R1 as a mask, the second interlayer insulating layer 40 and the sacrificial layer 50 are etched by the following method, for example.

First, the sacrifice layer 50 is etched until the upper surface of the second interlayer insulating layer 40 is exposed. The sacrifice layer 50 is etched by, for example, anisotropic dry etching, and the etchant is CF ₄ / CH ₂ F.
_{A 2} / O ₂ / Ar mixed gas is used. Next, the second interlayer insulating layer 40 is subsequently etched. Similar to the etching of the sacrificial layer 50, this etching method is performed by, for example, anisotropic dry etching, and the etchant is C ₄ F ₈
/ O ₂ / Ar / CO mixed gas. The dry etching method is not limited to the above method, but reactive ion etching, inductively coupled plasma etching, E
CR plasma etching can be used. The etchant is not limited to the above, as long as it can etch the sacrificial layer 50.

In this way, after forming the through hole 60 penetrating the second interlayer insulating layer 40 and the sacrificial layer 50, the resist layer R1 is removed by ashing removal or the like, and washed with an organic stripping solution.

(5) Pretreatment for forming contact layer The step (5) is performed in the same manner as in the case of the first embodiment.

(6) Formation of Contact Layer Next, the contact layer 70 is formed in the through hole 60 by the following method.

In this step, it is preferable that the processing is continuously performed without exposing the wafer to the atmosphere after the processing of the step (5) is completed. First, in the through hole 60,
A wetting layer and a barrier layer 64 are formed. The wetting layer is formed by, for example, a sputtering method, and its material is titanium. The barrier layer is, for example,
TDMAT (Tetrakis Di-Methyl)
CV using Amino Titanium) as source gas
Titanium nitride can be formed by the D method.

Next, as shown in FIG.
A conductive layer 72 is formed so as to fill the inside of 0. Conductive layer 7
2 is formed by a CVD method using WF ₆ as a source gas, for example. Then, the conductive layer 72 and the sacrificial layer 50 formed above the sacrificial layer 50 are removed by, for example, an etch back method or a CMP method.

The conductive layer 72 is, for example, tungsten,
Examples thereof include aluminum, aluminum alloys, copper, and copper alloys. As a method of burying the conductive layer 72 in the through hole 60, in addition to the above method, a CVD method, a PV method, or a PV method is used.
Examples of the method include the D method and the plating method.

(7) The step (7) of forming the second wiring layer is carried out in the same manner as in Example 1 to obtain the semiconductor device 100 according to the present invention.

In the present embodiment, the through hole 60 is
After penetrating the second interlayer insulating layer 40 and the sacrificial layer 50 and burying the conductive layer 72 in the through hole 60, CMP is performed.
Alternatively, the conductive layer 72 and the sacrificial layer 50 are etched back.
Are removed to form the contact layer 70. Thereby, when the tapered side surface 62 is formed in the through hole 60 by the sputter etching or the like in the step (5), the portion where the tapered side surface 62 is formed can be removed. That is, it is possible to prevent the problem that the through hole 60 is formed to have a diameter larger than a predetermined diameter and short-circuits with the adjacent wiring.

The sacrificial layer 50 is made of a conductive layer. Therefore, when the removal is performed using CMP, the conductive layer 72 and the sacrifice layer 50 have substantially the same polishing rate. Therefore, the removal is easy, and when etching back is performed, the etching rates of the two are substantially the same. Because
There is an advantage that it can be easily removed.

In the present embodiment, the contact layer connecting the first wiring layer on the first interlayer insulating layer and the second wiring layer on the second interlayer insulating layer has been described, but the present invention is not limited to this. However, the present invention is not limited to this, and can be applied to the formation of a contact layer for electrically connecting mutually different layers.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross sectional view schematically showing a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross sectional view schematically showing a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view schematically showing a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view schematically showing a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view schematically showing a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view schematically showing a semiconductor device manufactured by the semiconductor device manufacturing method according to the embodiment of the present invention.

FIG. 8 is a sectional view schematically showing a semiconductor device according to a conventional example.

[Explanation of symbols]

10 substrates 20 First interlayer insulating layer 30 First wiring layer 40 Second interlayer insulating layer 50 sacrificial layer 60 through holes 62 tapered side 64 Wetting Layer and Barrier Layer 70 Contact layer 72 Conductive layer 80 Second wiring layer 100 semiconductor devices

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH04 HH08 HH09 HH11 HH12                       HH19 HH33 JJ08 JJ09 JJ11                       JJ12 JJ18 JJ19 JJ33 KK04                       KK08 KK09 KK11 KK12 KK19                       KK33 MM05 MM08 MM13 NN06                       NN07 NN29 PP06 PP15 PP19                       PP26 QQ08 QQ09 QQ10 QQ11                       QQ12 QQ13 QQ14 QQ16 QQ21                       QQ31 QQ37 QQ48 QQ91 QQ92                       QQ94 RR04 RR06 RR09 RR11                       RR14 SS04 SS08 SS10 SS12                       SS13 SS15 SS22 TT02 XX01                       XX31

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device including the following steps (a) to (f). (A) forming a wiring layer having a predetermined pattern; (b) forming an interlayer insulating layer above the wiring layer; (c) forming a sacrificial layer above the interlayer insulating layer. (D) forming a through hole in the interlayer insulating layer and the sacrificial layer, (e) forming a contact layer in the through hole, and (f) forming the sacrificial layer and the sacrificial layer. Removing at least a part of the contact layer formed in the through hole. 2. The step (d) according to claim 1, further comprising: (g) applying a step to a side surface of the through hole so that a diameter of an upper end portion of the through hole becomes larger than a diameter of a lower portion thereof. A method of manufacturing a semiconductor device, comprising the step of forming a taper. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step (g) is sputter etching for removing impurities mixed in the through holes. 4. The method according to any one of claims 1 to 3, The method for manufacturing a semiconductor device, wherein the sacrificial layer is a conductive layer. 5. The sacrificial layer and the contact layer in the through hole formed in the sacrificial layer in the step (f) according to claim 4.
A method for manufacturing a semiconductor device, wherein all of the above are removed. 6. The method according to any one of claims 1 to 3, The method for manufacturing a semiconductor device, wherein the sacrificial layer is an insulating layer.