JP6292740B2 - データ受信装置 - Google Patents
データ受信装置 Download PDFInfo
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- JP6292740B2 JP6292740B2 JP2012113726A JP2012113726A JP6292740B2 JP 6292740 B2 JP6292740 B2 JP 6292740B2 JP 2012113726 A JP2012113726 A JP 2012113726A JP 2012113726 A JP2012113726 A JP 2012113726A JP 6292740 B2 JP6292740 B2 JP 6292740B2
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02T90/10—Technologies relating to charging of electric vehicles
- Y02T90/16—Information or communication technologies improving the operation of electric vehicles
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- Synchronisation In Digital Transmission Systems (AREA)
Description
(a)受信開始からフレーム確定までの遅延を、1ビット相当の時間にまで、縮小することができ、システム設計時の最大遅延時間想定を縮小することの可能なデータ受信装置を提供することができる。
(b)トランスポンダシステムのように、地上子と車上子結合時間が短いシステムでも、通信できるフレーム数を多くすることができ、地上子の小型化あるいは、最高通過速度の高速化が可能なデータ受信装置を提供することができる。
3 フレーム検定部
5 切替部
Claims (2)
- 繰り返し送信される伝送フレームのシリアルデータからなるビット列を繰り返し受信するデータ受信装置であって、
前記伝送フレームのフレームごとの前記ビット列を逐次格納し、1ビット受信するごとに、前記1ビット受信の期間内に、前記ビット列を、最初から最後まで、一巡するように循環シフトさせ、
フレーム検定部は、前記循環シフトの度に格納されている前記各ビットを個別的に検定し、
前記ビット列の特徴が検出されたとき、正規の前記伝送フレームが検出されたとして、格納された全ての前記ビット列を正規のデータとして確定する、データ受信装置。 - 請求項1に記載されたデータ受信装置であって、列車制御用車上装置又は列車制御用地上装置の何れかである、データ受信装置。
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JP2012113726A JP6292740B2 (ja) | 2012-05-17 | 2012-05-17 | データ受信装置 |
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JP2012113726A JP6292740B2 (ja) | 2012-05-17 | 2012-05-17 | データ受信装置 |
Publications (2)
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JP2013243425A JP2013243425A (ja) | 2013-12-05 |
JP6292740B2 true JP6292740B2 (ja) | 2018-03-14 |
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JP2012113726A Active JP6292740B2 (ja) | 2012-05-17 | 2012-05-17 | データ受信装置 |
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Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63310238A (ja) * | 1987-06-12 | 1988-12-19 | Fujitsu Ltd | 固定パタ−ン同期回路 |
JP2562035B2 (ja) * | 1987-09-04 | 1996-12-11 | 日立電子株式会社 | 連続デイジタル・コーデット・スケルチ方式 |
JPH04317228A (ja) * | 1991-04-17 | 1992-11-09 | Mitsubishi Electric Corp | フレーム同期保護装置 |
JPH0865289A (ja) * | 1994-08-17 | 1996-03-08 | Japan Radio Co Ltd | 2値直列データ通信における同期方式 |
JPH10126366A (ja) * | 1996-10-18 | 1998-05-15 | Matsushita Electric Ind Co Ltd | フレーム同期回路 |
JP2001163220A (ja) * | 1999-12-06 | 2001-06-19 | Central Japan Railway Co | 自動列車制御装置 |
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- 2012-05-17 JP JP2012113726A patent/JP6292740B2/ja active Active
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