JP6259393B2 - 電流生成が向上した半導体デバイス - Google Patents
電流生成が向上した半導体デバイス Download PDFInfo
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 131
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
1.GaAsの格子定数とInAsの格子定数との間の格子定数の低−%−In GaInAsバリアおよび高−%−In GaInAsウェル;
2.InP格子定数の低−%−In GaInAsバリアおよび高−%−InGaInAsウェル;
3.GaPの格子定数とGaAsの格子定数との間の格子定数の低−%−In GaInPバリアおよび高−%−In GaInPウェル;
4.GaAsの格子定数とInPの格子定数との間の格子定数の低−%−In GaInPバリアおよび高−%−In GaInPウェル;
5.GaAsの格子定数とInAsの格子定数との間の格子定数のGa(In)(P)AsバリアおよびGa(In)NAs(Sb)ウェル;
6.InP格子定数のGa(In)(P)AsバリアおよびGa(In)NAs(Sb)ウェル。
1.GaPの格子定数とInPの格子定数との間の格子定数の無秩序化されたGaInPバリアおよび秩序化されたGaInPウェル;
2.GaPの格子定数とInPの格子定数との間の格子定数の高−Al−% AlGa(In)Pバリアおよび低−Al−% AlGa(In)Pウェル;
3.GaAsの格子定数とInAsの格子定数との間の格子定数の高−Al−% AlGa(In)Asバリアおよび低−Al−% AlGa(In)Asウェル;
4.GaAsの格子定数とInAsの格子定数との間の格子定数の高−P−% GaInPAsバリアおよび低−P−% GaInPAsウェル;
5.GaAsの格子定数とInAsの格子定数との間の格子定数のGa(In)(P)AsバリアおよびGa(In)NAs(Sb)ウェル。
1.GaAsの格子定数とInAsの格子定数との間の格子定数の低−%−In GaInAsバリアおよび高−%−In GaInAsウェル;
2.GaAsの格子定数とGaSbの格子定数との間の格子定数の低−%−Sb GaAsSbバリアおよび高−%−Sb GaAsSbウェル;
3.GaPの格子定数とGaAsの格子定数との間の格子定数の高−%−P GaPAsバリアおよび低−%−P GaPAsウェル;
4.GaPの格子定数とGaAsの格子定数との間の格子定数の低−%−In GaInPバリアおよび高−%−In GaInPウェル;
5.GaAsの格子定数とInPの格子定数との間の格子定数の低−%−In GaInPバリアおよび高−%−In GaInPウェル;
6.GaAsの格子定数とInAsの格子定数との間の格子定数の低−%−N(または、ゼロ−N)GaInNAs(Sb)バリアおよび高−%−N GaInNAs(Sb)ウェル。
1.GaPの格子定数とInPの格子定数との間の格子定数の無秩序化されたGaInPバリアおよび秩序化されたGaInPウェル;
2.GaPの格子定数とInPの格子定数との間の格子定数の高−Al−% AlGa(In)Pバリアおよび低−Al−% AlGa(In)Pウェル;
3.GaAsの格子定数とInAsの格子定数との間の格子定数の高−Al−% AlGa(In)Asバリアおよび低−Al−% AlGa(In)Asウェル;
4.GaPの格子定数とInAsの格子定数との間の格子定数の高−P−% GaInPAsバリアおよび低−P−% GaInPAsウェル;
5.GaAsの格子定数とInAsの格子定数との間の格子定数の低−%−N(または、ゼロ−N)GaInNAs(Sb)バリアおよび高−%−N GaInNAs(Sb)ウェル。
3J−L:格子整合型3接合太陽電池、LBARまたはブラッグ反射器が無い
3J−LW:格子整合型3接合太陽電池、LBARおよびブラッグ反射器を伴う
3J−M:変成3接合太陽電池、LBARまたはブラッグ反射器が無い
3J−MW:変成3接合太陽電池、LBARおよびブラッグ反射器を伴う
また、AM1.5 Direct、ASTM G173−03太陽光スペクトル、すなわち、集光型光起電(CPV)太陽電池を評価して特徴付けるために使用される標準的な太陽光スペクトルにおける光子束に対応する単位波長当たりの電流密度は、1000ワット/cm2の強度に正規化されて、セルの測定された外部量子効率(EQE)と比較するために波長の関数として図中にプロットされる。更に、1000ワット/cm2全強度に正規化される、標準的なAM1.5 DirectASTM G173−03太陽光スペクトルに対応する単位波長当たりの強度も、比較のために波長の関数として図中にプロットされる。
また、本願は以下に記載する態様を含む。
(態様1)
ベース層と、
前記ベース層と電気的に接続するエミッタ層であって、前記エミッタ層と共に光起電力セルまたは他の光電子デバイスのp−n接合を形成するエミッタ層と、
前記ベース層および前記エミッタ層のうちの一方または両方に配置される低バンドギャップ吸収領域と
を備える半導体デバイス。
(態様2)
前記低バンドギャップ吸収領域が、前記光起電力セルまたは前記光電子デバイスの前記p−n接合の片側の空間電荷領域に組み込まれている、態様1に記載の半導体デバイス。
(態様3)
前記低バンドギャップ吸収領域が、前記光起電力セルまたは前記光電子デバイスの前記p−n接合の片側の準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様4)
前記低バンドギャップ吸収領域が、前記光起電力セルまたは前記光電子デバイスの前記p−n接合の片側の空間電荷領域および準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様5)
前記低バンドギャップ吸収領域が、前記光起電力セルまたは前記光電子デバイスの前記p−n接合の両側の空間電荷領域に組み込まれている、態様1に記載の半導体デバイス。
(態様6)
前記低バンドギャップ吸収領域が、前記光起電力セルまたは前記光電子デバイスの前記p−n接合の両側の空間電荷領域および準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様7)
前記低バンドギャップ吸収領域が前記ベース層の空間電荷領域に組み込まれている、態様1に記載の半導体デバイス。
(態様8)
前記低バンドギャップ吸収領域が前記エミッタ層の空間電荷領域に組み込まれている、態様1に記載の半導体デバイス。
(態様9)
前記低バンドギャップ吸収領域が前記ベースの準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様10)
前記低バンドギャップ吸収領域が前記エミッタ層の準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様11)
前記低バンドギャップ吸収領域が前記ベース層の空間電荷領域および準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様12)
前記低バンドギャップ吸収領域が前記エミッタ層の空間電荷領域および準中性領域に組み込まれている、態様1に記載の半導体デバイス。
(態様13)
前記低バンドギャップ吸収領域が2次元である、態様1に記載の半導体デバイス。
(態様14)
前記低バンドギャップ吸収領域が1次元である、態様1に記載の半導体デバイス。
(態様15)
前記低バンドギャップ吸収領域が0次元である、態様1に記載の半導体デバイス。
(態様16)
前記低バンドギャップ吸収領域が1つ以上の低バンドギャップ吸収領域を含んでいる、態様1に記載の半導体デバイス。
(態様17)
前記光起電力セルが1つ以上の小格子定数歪み補償領域を更に含んでいる、態様16に記載の半導体デバイス。
(態様18)
格子不整合形態を有している、態様1ないし態様17のいずれか1項に記載の半導体デバイス。
(態様19)
変成形態を有している、態様1ないし態様17のいずれか1項に記載の半導体デバイス。
(態様20)
前記光起電力セルが多接合デバイスのサブセルである、態様1ないし態様19のいずれか1項に記載の半導体デバイス。
(態様21)
1つ以上の裏面電界層を更に備えている、態様1ないし態様20のいずれか1項に記載の半導体デバイス。
(態様22)
前記ベースがp型変成GaInAsベースである、態様1ないし態様21のいずれか1項に記載の半導体デバイス。
(態様23)
前記エミッタがn型GaInAsエミッタである、態様1ないし態様22のいずれか1項に記載の半導体デバイス。
(態様24)
1つ以上の前記低バンドギャップ吸収領域が前記ベースまたは前記エミッタよりも低いバンドギャップを有している、態様1ないし態様23のいずれか1項に記載の半導体デバイス。
(態様25)
1つ以上の前記低バンドギャップ吸収領域および1つ以上の前記小格子定数歪み補償領域が前記ベースまたは前記エミッタよりも低いバンドギャップを有している、態様1ないし態様23のいずれか1項に記載の半導体デバイス。
(態様26)
前記ベースが秩序化されている、態様1ないし態様25のいずれか1項に記載の半導体デバイス。
(態様27)
前記ベースが無秩序化されている、態様1ないし態様25のいずれか1項に記載の半導体デバイス。
(態様28)
前記ベースには秩序化および無秩序化の両方がなされている、態様1ないし態様25のいずれか1項に記載の半導体デバイス。
(態様29)
前記光起電力セルが3接合デバイスの中央サブセルである、態様1に記載の半導体デバイス。
(態様30)
前記光起電力セルが多接合デバイスの上端サブセルである、態様1に記載の半導体デバイス。
(態様31)
前記光起電力セルが多接合デバイスの下端サブセルである、態様1に記載の半導体デバイス。
(態様32)
前記光起電力セルは、上端サブセルと下端サブセルとの間に位置づけられる多接合デバイスのサブセルである、態様1に記載の半導体デバイス。
(態様33)
基板を更に含み、1つ以上の更なるセルが、前記基板の前記ベース層とは反対側で成長される、態様1ないし態様32のいずれか1項に記載の半導体デバイス。
(態様34)
前記セルが逆成長される、態様1ないし態様33のいずれか1項に記載の半導体デバイス。
(態様35)
態様1ないし態様34のいずれか1項に記載の格子不整合半導体デバイスまたは変成半導体デバイスを形成する方法であって、
半導体デバイスのベース、エミッタ、またはベースおよびエミッタに1つ以上の低バンドギャップ吸収領域を形成することを含む方法。
(態様36)
前記1つ以上の低バンドギャップ吸収領域に隣接する1つ以上の小格子定数歪み補償領域を形成することを更に含む態様35に記載の方法。
Claims (12)
- 少なくとも1つのサブセルを備える半導体デバイスであって、前記半導体デバイスが格子不整合形態または変成形態を有しており、前記少なくとも1つのサブセルが、
ベース層と、
前記ベース層と電気的に接続するエミッタ層であって、前記ベース層と共に光起電力セルまたは他の光電子デバイスのp−n接合を形成するエミッタ層と、
前記ベース層に配置される低バンドギャップ吸収領域と
を備え、
前記低バンドギャップ吸収領域が、前記ベース層の準中性領域に組み込まれており、
前記低バンドギャップ吸収領域が、周りの半導体層よりも高い光生成および低いバンドギャップを有し、
前記低バンドギャップ吸収領域が、前記半導体デバイスの平均格子定数よりも小さい格子定数と大きい格子定数とが交互に入れ替わる格子定数を有する伸張性および圧縮性がある領域を形成し、前記低バンドギャップ吸収領域が基板に対して格子不整合または変成である、半導体デバイス。 - 前記低バンドギャップ吸収領域が2次元、1次元または0次元である、請求項1に記載の半導体デバイス。
- 前記少なくとも1つのサブセルが1つ以上の低バンドギャップ吸収領域を含んでいる、請求項1に記載の半導体デバイス。
- 前記光起電力セルが多接合デバイスのサブセルである、請求項1から3のいずれか1項に記載の半導体デバイス。
- 1つ以上の裏面電界層を更に備えている、請求項1から4のいずれか1項に記載の半導体デバイス。
- 前記ベースがp型変成GaInAsベースである、請求項1から5のいずれか1項に記載の半導体デバイス。
- 前記エミッタがn型GaInAsエミッタである、請求項1から6のいずれか1項に記載の半導体デバイス。
- 前記低バンドギャップ吸収領域が前記ベースまたは前記エミッタよりも低いバンドギャップを有している、請求項1から7のいずれか1項に記載の半導体デバイス。
- 前記少なくとも1つのサブセルが3接合デバイスの中央サブセルである、請求項1に記載の半導体デバイス。
- 前記少なくとも1つのサブセルが多接合デバイスの上端サブセル、下端サブセル、または上端サブセルと下端サブセルとの間に位置づけられるサブセルである、請求項1に記載の半導体デバイス。
- 基板を更に含み、1つ以上の更なるセルが、前記基板の前記ベース層とは反対側で成長される、請求項1から10のいずれか1項に記載の半導体デバイス。
- 請求項1から11のいずれか1項に記載の半導体デバイスを形成する方法であって、
半導体デバイスのベースの準中性領域に1つ以上の低バンドギャップ吸収領域を形成することを含む方法。
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US20120240987A1 (en) | 2012-09-27 |
JP2014514746A (ja) | 2014-06-19 |
EP2689465B1 (en) | 2022-07-20 |
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JP2018026570A (ja) | 2018-02-15 |
EP3444848A1 (en) | 2019-02-20 |
JP6650916B2 (ja) | 2020-02-19 |
US10170652B2 (en) | 2019-01-01 |
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