JP6239130B2 - 作業負荷に従ってメモリバス帯域幅を低減するためのシステムおよび方法 - Google Patents

作業負荷に従ってメモリバス帯域幅を低減するためのシステムおよび方法 Download PDF

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JP6239130B2
JP6239130B2 JP2016544034A JP2016544034A JP6239130B2 JP 6239130 B2 JP6239130 B2 JP 6239130B2 JP 2016544034 A JP2016544034 A JP 2016544034A JP 2016544034 A JP2016544034 A JP 2016544034A JP 6239130 B2 JP6239130 B2 JP 6239130B2
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memory
bus
channel
width
soc
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JP2016534484A5 (enExample
JP2016534484A (ja
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ハウ−ジン・ロ
デクスター・チュン
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
JP2016544034A 2013-09-20 2014-09-19 作業負荷に従ってメモリバス帯域幅を低減するためのシステムおよび方法 Active JP6239130B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/033,233 2013-09-20
US14/033,233 US9430434B2 (en) 2013-09-20 2013-09-20 System and method for conserving memory power using dynamic memory I/O resizing
PCT/US2014/056659 WO2015042469A1 (en) 2013-09-20 2014-09-19 System and method for conserving memory power using dynamic memory i/o resizing

Publications (3)

Publication Number Publication Date
JP2016534484A JP2016534484A (ja) 2016-11-04
JP2016534484A5 JP2016534484A5 (enExample) 2017-07-20
JP6239130B2 true JP6239130B2 (ja) 2017-11-29

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JP2016544034A Active JP6239130B2 (ja) 2013-09-20 2014-09-19 作業負荷に従ってメモリバス帯域幅を低減するためのシステムおよび方法

Country Status (7)

Country Link
US (1) US9430434B2 (enExample)
EP (1) EP3047352B1 (enExample)
JP (1) JP6239130B2 (enExample)
KR (1) KR101914350B1 (enExample)
CN (1) CN105556421B (enExample)
TW (1) TWI627526B (enExample)
WO (1) WO2015042469A1 (enExample)

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US10222853B2 (en) * 2016-03-03 2019-03-05 Qualcomm Incorporated Power saving techniques for memory systems by consolidating data in data lanes of a memory bus
US10126979B2 (en) * 2016-10-04 2018-11-13 Qualcomm Incorporated Bus encoding using metadata
US10152379B1 (en) * 2016-12-27 2018-12-11 EMC IP Holding Company LLP Efficient garbage collection for distributed storage with forward error correction
US10409513B2 (en) * 2017-05-08 2019-09-10 Qualcomm Incorporated Configurable low memory modes for reduced power consumption
US20180335828A1 (en) * 2017-05-19 2018-11-22 Qualcomm Incorporated Systems and methods for reducing memory power consumption via device-specific customization of ddr interface parameters
CN109032973B (zh) * 2018-07-09 2020-10-16 芯来科技(武汉)有限公司 Icb总线系统
KR102731057B1 (ko) * 2018-09-21 2024-11-15 삼성전자주식회사 메모리 장치와 통신하는 데이터 처리 장치 및 방법
US11693794B2 (en) * 2020-08-31 2023-07-04 Sandisk Technologies Llc Tunable and scalable command/address protocol for non-volatile memory
KR20230047823A (ko) 2021-10-01 2023-04-10 삼성전자주식회사 시스템 온 칩 및 어플리케이션 프로세서
US11893240B2 (en) * 2021-10-28 2024-02-06 Qualcomm Incorporated Reducing latency in pseudo channel based memory systems
CN117519451A (zh) * 2022-07-28 2024-02-06 华为技术有限公司 数据读写的方法、控制器和存储设备
US20250068574A1 (en) * 2023-08-23 2025-02-27 Qualcomm Incorporated Efficiency mode in a memory system

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US6727533B2 (en) * 2000-11-29 2004-04-27 Fujitsu Limited Semiconductor apparatus having a large-size bus connection
US7469311B1 (en) * 2003-05-07 2008-12-23 Nvidia Corporation Asymmetrical bus
US7188198B2 (en) 2003-09-11 2007-03-06 International Business Machines Corporation Method for implementing dynamic virtual lane buffer reconfiguration
US7694060B2 (en) 2005-06-17 2010-04-06 Intel Corporation Systems with variable link widths based on estimated activity levels
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US20070101168A1 (en) 2005-10-31 2007-05-03 Lee Atkinson Method and system of controlling data transfer speed and power consumption of a bus
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US9798370B2 (en) * 2009-03-30 2017-10-24 Lenovo (Singapore) Pte. Ltd. Dynamic memory voltage scaling for power management
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US8762760B2 (en) * 2010-09-14 2014-06-24 Xilinx, Inc. Method and apparatus for adaptive power control in a multi-lane communication channel
JP5630348B2 (ja) 2011-03-18 2014-11-26 株式会社リコー メモリモジュールおよびメモリシステム
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Also Published As

Publication number Publication date
EP3047352A1 (en) 2016-07-27
CN105556421A (zh) 2016-05-04
TWI627526B (zh) 2018-06-21
JP2016534484A (ja) 2016-11-04
KR20160055828A (ko) 2016-05-18
KR101914350B1 (ko) 2018-11-01
CN105556421B (zh) 2018-12-25
US20150089112A1 (en) 2015-03-26
TW201527947A (zh) 2015-07-16
US9430434B2 (en) 2016-08-30
WO2015042469A1 (en) 2015-03-26
EP3047352B1 (en) 2017-03-15

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