JP6233971B2 - スプリット・ゲート・ビット・セルのプログラミング - Google Patents

スプリット・ゲート・ビット・セルのプログラミング Download PDF

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Publication number
JP6233971B2
JP6233971B2 JP2014011512A JP2014011512A JP6233971B2 JP 6233971 B2 JP6233971 B2 JP 6233971B2 JP 2014011512 A JP2014011512 A JP 2014011512A JP 2014011512 A JP2014011512 A JP 2014011512A JP 6233971 B2 JP6233971 B2 JP 6233971B2
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Prior art keywords
voltage
memory cell
coupled
gate
coupling
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Japanese (ja)
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JP2014146407A5 (enExample
JP2014146407A (ja
Inventor
エム.ホン チョン
エム.ホン チョン
ジェイ.シズデク ロナルド
ジェイ.シズデク ロナルド
エイ.ウィンステッド ブライアン
エイ.ウィンステッド ブライアン
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NXP USA Inc
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NXP USA Inc
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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/12Programming voltage switching circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
JP2014011512A 2013-01-28 2014-01-24 スプリット・ゲート・ビット・セルのプログラミング Active JP6233971B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/751,548 US8885403B2 (en) 2013-01-28 2013-01-28 Programming a split gate bit cell
US13/751,548 2013-01-28

Publications (3)

Publication Number Publication Date
JP2014146407A JP2014146407A (ja) 2014-08-14
JP2014146407A5 JP2014146407A5 (enExample) 2017-02-23
JP6233971B2 true JP6233971B2 (ja) 2017-11-22

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ID=51222804

Family Applications (1)

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JP2014011512A Active JP6233971B2 (ja) 2013-01-28 2014-01-24 スプリット・ゲート・ビット・セルのプログラミング

Country Status (3)

Country Link
US (1) US8885403B2 (enExample)
JP (1) JP6233971B2 (enExample)
CN (1) CN103971736B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018049674A (ja) * 2016-09-21 2018-03-29 ルネサスエレクトロニクス株式会社 半導体装置
US10147734B1 (en) * 2017-08-30 2018-12-04 Cypress Semiconductor Corporation Memory gate driver technology for flash memory cells

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091634A (en) * 1997-04-11 2000-07-18 Programmable Silicon Solutions Compact nonvolatile memory using substrate hot carrier injection
JP2003046002A (ja) * 2001-07-26 2003-02-14 Sony Corp 不揮発性半導体メモリ装置およびその動作方法
JP4647175B2 (ja) * 2002-04-18 2011-03-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP2004319034A (ja) * 2003-04-18 2004-11-11 Renesas Technology Corp データプロセッサ
US7236398B1 (en) * 2005-08-31 2007-06-26 Altera Corporation Structure of a split-gate memory cell
JP5300773B2 (ja) * 2010-03-29 2013-09-25 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
US8643123B2 (en) 2011-04-13 2014-02-04 Freescale Semiconductor, Inc. Method of making a semiconductor structure useful in making a split gate non-volatile memory cell

Also Published As

Publication number Publication date
CN103971736A (zh) 2014-08-06
US8885403B2 (en) 2014-11-11
US20140211559A1 (en) 2014-07-31
CN103971736B (zh) 2019-10-18
JP2014146407A (ja) 2014-08-14

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