JP6224454B2 - Vertical semiconductor device - Google Patents

Vertical semiconductor device Download PDF

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JP6224454B2
JP6224454B2 JP2013271576A JP2013271576A JP6224454B2 JP 6224454 B2 JP6224454 B2 JP 6224454B2 JP 2013271576 A JP2013271576 A JP 2013271576A JP 2013271576 A JP2013271576 A JP 2013271576A JP 6224454 B2 JP6224454 B2 JP 6224454B2
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conductivity type
semiconductor substrate
electrode
peripheral
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JP2015126192A (en
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佐智子 青井
佐智子 青井
渡辺　行彦
行彦 渡辺
順 斎藤
順 斎藤
巨裕 鈴木
巨裕 鈴木
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Priority to PCT/JP2014/077090 priority patent/WO2015098237A1/en
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Description

本明細書では、半導体基板の表面に形成されている表面電極と半導体基板の裏面に形成されている裏面電極の間の抵抗を変えることができる縦型半導体装置を開示する。特に、前記抵抗を変える半導体構造が形成されている素子領域と、素子領域を一巡する周辺領域を備えている縦型半導体装置を開示する。   The present specification discloses a vertical semiconductor device that can change the resistance between a front surface electrode formed on the surface of a semiconductor substrate and a back surface electrode formed on the back surface of the semiconductor substrate. In particular, a vertical semiconductor device is disclosed that includes an element region in which a semiconductor structure for changing the resistance is formed and a peripheral region that goes around the element region.

ゲート電極に印加する電圧によって表面電極と裏面電極の間の抵抗が変化する縦型半導体装置が知られている。ＭＯＳの場合、ソース領域とドリフト領域を分離するボディ領域と、そのボディ領域にゲート絶縁膜を介して対向するゲート電極を備えている。あるいはＩＧＢＴの場合、エミッタ領域とドリフト領域を分離するボディ領域と、そのボディ領域にゲート絶縁膜を介して対向するゲート電極を備えている。いずれも場合も、表面側第１導電型領域（ソース領域あるいはエミッタ領域）と裏面側第１導電型領域（ドリフト領域）を分離する第２導電型領域（ボディ領域）と、第２導電型領域にゲート絶縁膜を介して対向するゲート電極を備えている。ゲート電極にオン電圧を印加し、ゲート絶縁膜を介してゲート電極に対向する範囲の第２導電型領域（ボディ領域）に反転層を形成すると、表面電極と裏面電極の間の抵抗が低下する。   2. Description of the Related Art A vertical semiconductor device in which resistance between a front electrode and a back electrode changes according to a voltage applied to a gate electrode is known. In the case of MOS, a body region that separates a source region and a drift region and a gate electrode that faces the body region through a gate insulating film are provided. Alternatively, the IGBT includes a body region that separates the emitter region and the drift region, and a gate electrode that faces the body region via a gate insulating film. In any case, a second conductivity type region (body region) that separates the front side first conductivity type region (source region or emitter region) and the back side first conductivity type region (drift region), and the second conductivity type region Are provided with a gate electrode facing each other through a gate insulating film. When an inversion layer is formed in the second conductivity type region (body region) in the range facing the gate electrode through the gate insulating film by applying an on-voltage to the gate electrode, the resistance between the front electrode and the back electrode decreases. .

表面電極と裏面電極の間に加える電圧を高めると、ゲート電極にオン電圧を印加しないにも関わらず、表面電極と裏面電極の間を電流が流れてしまう現象が生じる。本明細書では、この現象を耐圧が破れるという。耐圧を高めるために、素子領域に形成する半導体構造に様々の改良が加えられている。   When the voltage applied between the front electrode and the back electrode is increased, a phenomenon occurs in which a current flows between the front electrode and the back electrode although no on-voltage is applied to the gate electrode. In this specification, this phenomenon is said to break the breakdown voltage. In order to increase the breakdown voltage, various improvements have been made to the semiconductor structure formed in the element region.

素子領域に形成する半導体構造を改善するだけでは、表面電極と裏面電極の間に加える電圧を高めた場合に、半導体基板の周辺領域を介して表面電極と裏面電極の間を電流が流れてしまう。耐圧向上のためには、周辺領域の半導体構造にも改善を要する。   By simply improving the semiconductor structure formed in the element region, if the voltage applied between the front electrode and the back electrode is increased, a current flows between the front electrode and the back electrode via the peripheral region of the semiconductor substrate. . In order to improve the breakdown voltage, the semiconductor structure in the peripheral region needs to be improved.

特許文献１と２に、半導体基板の表面に臨むとともに素子領域を一巡する範囲に、第２導電型不純物領域を形成する技術が開示されている。素子領域を一巡することからリング形状をしている。特許文献１と２の技術では、素子領域の周りに複数個のリング状領域を多重に配置する。本明細書では、この技術をガードリング構造という。周辺領域にガードリング構造を配置すると、周辺領域での耐圧が向上する。
特許文献１の図９には、周辺領域での耐圧をさらに向上させるために、ガードリング構造に加えて、裏面側第１導電型領域（ドリフト領域）の中間深さに第２導電型領域（特許文献１ではＰ＋電位固定領域と称している）を形成する技術を開示している。特許文献１の技術では、複数個の第２導電型領域をとびとびに（すなわち相互に離反した位置に）配置する。
特許文献２には、周辺領域での耐圧を向上させるために、ガードリング構造に加えて、半導体基板の表面に臨む範囲に第２導電型不純物領域（特許文献２ではリサーフ層と称している）を形成する技術が開示されている。リサーフ層もガードリングも第２導電型であるが、前者の不純物濃度が後者の不純物濃度より薄いことから、リサーフ層とガードリングが区別される。特許文献２では、リサーフ層に包まれる範囲内にガードリング構造が形成されている。 Patent Documents 1 and 2 disclose a technique for forming a second conductivity type impurity region in a range that faces the surface of a semiconductor substrate and goes around the device region. Since it goes around the element region, it has a ring shape. In the techniques of Patent Documents 1 and 2, a plurality of ring-shaped regions are arranged in a multiple manner around the element region. In this specification, this technique is called a guard ring structure. When the guard ring structure is arranged in the peripheral region, the breakdown voltage in the peripheral region is improved.
In FIG. 9 of Patent Document 1, in order to further improve the breakdown voltage in the peripheral region, in addition to the guard ring structure, the second conductivity type region (drift region) is formed at an intermediate depth of the back side first conductivity type region (drift region). Patent Document 1 discloses a technique for forming a P + potential fixing region). In the technique of Patent Document 1, a plurality of second conductivity type regions are arranged in a discrete manner (that is, at positions separated from each other).
In Patent Document 2, in order to improve the breakdown voltage in the peripheral region, in addition to the guard ring structure, a second conductivity type impurity region (referred to as RESURF layer in Patent Document 2) is provided in a range facing the surface of the semiconductor substrate. Techniques for forming the are disclosed. Both the RESURF layer and the guard ring are of the second conductivity type, but the RESURF layer and the guard ring are distinguished from each other because the former impurity concentration is lower than the latter impurity concentration. In Patent Document 2, a guard ring structure is formed within a range covered by the RESURF layer.

特開２００７−３１１８２２号公報JP 2007-31822 A 特開２００３−１０１０３９号公報JP 2003-101039 A

半導体装置を破壊から保護するためには、「素子領域の耐圧＜周辺領域の耐圧」の関係であるが好ましい。その関係が得られると、耐圧が破れる場合には素子領域で耐圧が破れる関係を得ることができる。素子領域の面積は周辺領域の面積より広い。広い領域で耐圧が破れる場合には、狭い領域で耐圧が破れる場合に比して、電流密度を下げることができ、半導体装置が破壊されないようにすることができる。半導体装置が破壊されないうちに、耐圧が破れるような異常事象に対する処理を実施することが可能となる。
特許文献１に記載されている「ガードリング構造＋裏面側第１導電型領域の中間深さに複数個の第２導電型領域をとびとびに配置する」構造では、とびとびに配置されている第２導電型領域と裏面側第１導電型領域の界面から空乏層が十分に発達しない。「素子領域の耐圧＜周辺領域の耐圧」の関係を得ることが難しい。
特許文献２に記載されている「リサーフ領域の内部にガードリング構造を配置する」構造でも、「素子領域の耐圧＜周辺領域の耐圧」の関係を得ることが難しい。
本明細書では、「素子領域の耐圧＜周辺領域の耐圧」の関係を得ることができる半導体構造を提案する。 In order to protect the semiconductor device from destruction, it is preferable that “the breakdown voltage of the element region <the breakdown voltage of the peripheral region”. When the relationship is obtained, when the breakdown voltage is broken, a relationship in which the breakdown voltage is broken in the element region can be obtained. The area of the element region is larger than the area of the peripheral region. When the breakdown voltage is broken in a wide region, the current density can be lowered and the semiconductor device can be prevented from being destroyed as compared with the case where the breakdown voltage is broken in a narrow region. Before the semiconductor device is destroyed, it is possible to carry out processing for an abnormal event in which the breakdown voltage is broken.
In the structure described in Patent Document 1, “a plurality of second conductivity type regions are arranged at intermediate depths between the guard ring structure and the first conductivity type region on the back surface side”, the second is arranged in a discrete manner. The depletion layer does not develop sufficiently from the interface between the conductive type region and the back side first conductive type region. It is difficult to obtain the relationship of “breakdown voltage of element region <breakdown voltage of peripheral region”.
Even in the structure of “disposing the guard ring structure inside the RESURF region” described in Patent Document 2, it is difficult to obtain the relationship “the breakdown voltage of the element region <the breakdown voltage of the peripheral region”.
In this specification, a semiconductor structure capable of obtaining the relationship of “breakdown voltage of element region <breakdown voltage of peripheral region” is proposed.

本明細書で開示する半導体装置は、半導体基板を平面視したときに、素子領域と、素子領域を一巡する周辺領域を備えている。
素子領域では、半導体基板の表面に形成されている表面電極と、半導体基板の裏面に形成されている裏面電極と、表面電極に導通する表面側第１導電型領域（ＭＯＳの場合にはソース領域であり、ＩＧＢＴの場合にはエミッタ領域）と、裏面電極に導通する裏面側第１導電型領域（ドリフト領域）と、表面側第１導電型領域と裏面側第１導電型領域を分離する第２導電型領域（ボディ領域）と、表面側第１導電型領域と裏面側第１導電型領域を分離する範囲の第２導電型領域にゲート絶縁膜を介して対向するゲート電極を備えている。上記の半導体構造を備えていると、ゲート電極の電圧によって表面電極と裏面電極の間の抵抗が変化する。 The semiconductor device disclosed in this specification includes an element region and a peripheral region that goes around the element region when the semiconductor substrate is viewed in plan.
In the element region, a front surface electrode formed on the surface of the semiconductor substrate, a back surface electrode formed on the back surface of the semiconductor substrate, and a first conductive type region on the surface side that conducts to the front surface electrode (source region in the case of MOS) In the case of an IGBT, an emitter region), a back side first conductivity type region (drift region) conducting to the back electrode, and a front side first conductivity type region and a back side first conductivity type region are separated. A gate electrode is provided opposite to the second conductivity type region (body region) and the second conductivity type region in a range separating the first conductivity type region on the front surface side and the first conductivity type region on the back surface side through a gate insulating film. . When the semiconductor structure is provided, the resistance between the front electrode and the back electrode changes depending on the voltage of the gate electrode.

本明細書で開示する半導体装置の周辺領域では、半導体基板の表面と外周の双方に臨む位置に形成されている第１導電型不純物高濃度領域と、素子領域に接する位置から第１導電型不純物高濃度領域に向けて延びているものの第１導電型不純物高濃度領域に達していない範囲の半導体基板の表面に臨む位置に形成されている第２導電型不純物低濃度領域と、半導体基板の表面に臨む範囲において素子領域を一巡している第２導電型不純物高濃度リング状領域の多重構造と、裏面側第１導電型領域の中間深さに形成されている第２導電型フローティング領域を備えている。周辺領域に形成されている第２導電型不純物低濃度領域と第２導電型不純物高濃度リング状領域はともに第２導電型不純物を含んでおり、しかも、第２導電型不純物高濃度リング状領域の多重構造の少なくとも一部は第２導電型不純物低濃度領域に含まれる範囲に形成されている。第２導電型不純物低濃度領域と第２導電型不純物高濃度リング状領域では不純物濃度が相違し、前者の不純物濃度の方が後者の不純物濃度より薄いことから、両者を区別することができる。第２導電型フローティング領域は、最内周の第２導電型不純物高濃度リング状領域より内側の位置から、半導体基板の外周に向けて、第２導電型不純物低濃度領域と第２導電型不純物高濃度リング状領域の多重構造の両者が配置されている領域の外周側位置より外側にまで、連続的に延びている。ただし、第１導電型不純物高濃度領域の裏面側には達していない。ここでいう「連続的に延びている」は、「複数個の領域に分割されずに連続的に延びている」ことを意味する。 In the peripheral region of the semiconductor device disclosed in this specification, the first conductivity type impurity high concentration region formed at a position facing both the surface and the outer periphery of the semiconductor substrate, and the first conductivity type impurity from the position in contact with the element region. A second conductivity type impurity low concentration region formed at a position facing the surface of the semiconductor substrate in a range extending toward the high concentration region but not reaching the first conductivity type impurity high concentration region; and a surface of the semiconductor substrate And a second conductive type floating region formed at an intermediate depth of the first conductive type region on the back surface side. ing. The second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring region formed in the peripheral region both contain the second conductivity type impurity, and the second conductivity type impurity high concentration ring region At least a part of the multiple structure is formed in a range included in the second conductivity type impurity low concentration region. Since the impurity concentration is different between the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region, and the former impurity concentration is lower than the latter impurity concentration , both can be distinguished. The second conductivity type floating region has a second conductivity type impurity low concentration region and a second conductivity type impurity from a position inside the innermost second conductivity type impurity high concentration ring-shaped region toward the outer periphery of the semiconductor substrate. It extends continuously from the outer peripheral side position of the region where both of the multiple structures of the high-density ring-shaped region are arranged . However, it does not reach the back side of the first conductivity type impurity high concentration region . Here, the "communication has continued to extend" means "without being divided into a plurality of regions extending continuously".

上記の半導体装置では、周辺領域に、「第２導電型不純物低濃度領域＋第２導電型不純物高濃度リング状領域＋第２導電型フローティング領域」の組み合わせが形成されている。上記構造によると、裏面側第１導電型領域（ドリフト領域）と第２導電型不純物低濃度領域の界面から空乏層が発達するのみならず、裏面側第１導電型領域（ドリフト領域）と第２導電型フローティング領域の界面からも空乏層が発達し、周辺領域の広い範囲が空乏化して耐圧が向上する。また空乏層の周囲に形成される電界集中領域での集中度が緩和され、その作用によっても耐圧が向上する。その結果、主として第２導電型領域と裏面側第１導電型領域の界面から発達する空乏層によって耐圧を確保する素子領域よりも高い耐圧を確保することができる。すなわち、「素子領域の耐圧＜周辺領域の耐圧」の関係を得ることができる。その関係が得られると、耐圧が破れる場合には素子領域で耐圧が破れる関係を得ることができる。素子領域の面積は周辺領域の面積より広い。広い領域で耐圧が破れる場合には、狭い領域で耐圧が破れる場合に比して、電流密度を下げることができ、半導体装置が破壊されないようにすることができる。半導体装置が破壊されないうちに、耐圧が破れるような異常事象に対する処理を施すことが可能となる。   In the semiconductor device, a combination of “second conductivity type impurity low concentration region + second conductivity type impurity high concentration ring region + second conductivity type floating region” is formed in the peripheral region. According to the above structure, not only the depletion layer develops from the interface between the backside first conductivity type region (drift region) and the second conductivity type impurity low concentration region, but also the backside first conductivity type region (drift region) and the second A depletion layer develops also from the interface of the two-conductivity floating region, and a wide range of the peripheral region is depleted and the breakdown voltage is improved. Further, the degree of concentration in the electric field concentration region formed around the depletion layer is relaxed, and the breakdown voltage is improved by the action. As a result, it is possible to ensure a higher breakdown voltage than the element region in which the breakdown voltage is ensured mainly by the depletion layer that develops from the interface between the second conductivity type region and the back side first conductivity type region. That is, the relationship of “breakdown voltage of element region <breakdown voltage of peripheral region” can be obtained. When the relationship is obtained, when the breakdown voltage is broken, a relationship in which the breakdown voltage is broken in the element region can be obtained. The area of the element region is larger than the area of the peripheral region. When the breakdown voltage is broken in a wide region, the current density can be lowered and the semiconductor device can be prevented from being destroyed as compared with the case where the breakdown voltage is broken in a narrow region. Before the semiconductor device is destroyed, it is possible to perform processing for an abnormal event that breaks the breakdown voltage.

半導体基板がＳｉＣで形成されている場合、欠陥密度が高いことと、ｐ型のＳｉＣ領域の抵抗が高いことから、従来の周辺耐圧構造では、周辺領域での耐圧を確保することが難しい。特に、ソース領域とドリフト領域を分離するボディ領域がゲート絶縁膜を介してゲート電極に対向しており、ドリフト領域と裏面電極の間にドレイン領域が形成されているＭＯＳの場合、周辺領域での耐圧を確保することが難しい。ＳｉＣはＳｉに比して欠陥密度が高いために、フローティング領域がとびとびに形成されている従来の周辺耐圧構造は、Ｓｉに対しては有効に機能するけれども、ＳｉＣに対しては有効に機能しない。
ＳｉＣでＭＯＳを形成する場合、裏面側第１導電型領域（ドリフト領域）の中間深さを最内周の第２導電型不純物高濃度リング状領域より内側の位置から半導体基板の外周に向けて連続的に延びている第２導電型フローティング領域を形成することが特に効果的である。 When the semiconductor substrate is made of SiC, the defect density is high and the resistance of the p-type SiC region is high. Therefore, it is difficult to ensure the breakdown voltage in the peripheral region with the conventional peripheral breakdown voltage structure. In particular, in the case of a MOS in which the body region that separates the source region and the drift region is opposed to the gate electrode through the gate insulating film, and the drain region is formed between the drift region and the back surface electrode, It is difficult to ensure a breakdown voltage. Since SiC has a higher defect density than Si, the conventional peripheral voltage structure in which the floating region is formed in a discrete manner functions effectively for Si, but does not function effectively for SiC. .
When the MOS is formed of SiC, the intermediate depth of the first conductivity type region (drift region) on the back surface side is directed from the inner position to the outer periphery of the semiconductor substrate from the innermost second conductivity type impurity high-concentration ring-shaped region. It is particularly effective to form the second conductive type floating region extending continuously.

ともに半導体基板の表面に臨む位置に形成されている第２導電型不純物低濃度領域と第２導電型不純物高濃度リング状領域の形成範囲の関係は次のいずれかである。
（１）後者が前者よりも外側にまで延びている。すなわち最外周のリング状領域が第２導電型不純物低濃度領域の外側に形成されている。この場合は、第２導電型フローティング領域が第２導電型不純物低濃度領域の外周側位置より外側まで延びていることが好ましい。
（２）前者が後者よりも外側にまで延びている。すなわち最外周のリング状領域が第２導電型不純物低濃度領域の内部に形成されている。この場合は、第２導電型フローティング領域が最外周のリング状領域の位置より外側まで延びていることが好ましい。
すなわち、第２導電型フローティング領域が、第２導電型不純物低濃度領域と第２導電型不純物高濃度リング状領域の多重構造の両者が配置されている領域の外周側位置より外側にまで延びていることが好ましい。
上記の関係を満たしていると、第２導電型フローティング領域を形成することで周辺領域の耐圧が向上する効果が顕著に発揮される。
上記（１）の場合、第２導電型フローティング領域が最外周のリング状領域の位置より外側まで延びていることがさらに好ましい。上記（２）の場合、第２導電型フローティング領域が第２導電型不純物低濃度領域の外周側位置より外側まで延びていることがさらに好ましい。すなわち、第２導電型フローティング領域が、第２導電型不純物低濃度領域と第２導電型不純物高濃度リング状領域の多重構造の少なくとも一方が配置されている領域の外周側位置より外側にまで延びていることがさらに好ましい。 In either case, the relationship between the formation range of the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region formed at a position facing the surface of the semiconductor substrate is either of the following.
(1) The latter extends outside the former. Or ring-shaped region of the outermost periphery is formed outside the second conductivity type impurity low concentration region. In this case, it is preferable that the second conductivity type floating region extends to the outside from the outer peripheral side position of the second conductivity type impurity low concentration region.
(2) The former extends outward beyond the latter. Or ring-shaped region of the outermost periphery are formed inside the second conductivity type impurity low concentration region. In this case, it is preferable that the second conductivity type floating region extends from the position of the outermost ring-shaped region to the outside.
That is, the second conductivity type floating region extends to the outside from the outer peripheral side position of the region where both the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region multiple structure are arranged. Preferably it is.
When the above relationship is satisfied, the effect of improving the breakdown voltage of the peripheral region is significantly exhibited by forming the second conductivity type floating region.
In the case of (1) above, it is more preferable that the second conductivity type floating region extends to the outside from the position of the outermost ring region. In the case of (2) above, it is more preferable that the second conductivity type floating region extends outward from the outer peripheral side position of the second conductivity type impurity low concentration region. In other words, the second conductivity type floating region extends outward from the outer peripheral side position of the region where at least one of the multiple structure of the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring region is disposed. More preferably.

第２導電型フローティング領域は、裏面側第１導電型領域の中間深さに形成されていることが好ましい。すなわち、裏面側第１導電型領域の表面側の深さから裏面側の深さまでの厚みを１０等分したときに、表面側から８／１０の位置にあるレベルより表面側に形成されていることが好ましい。裏面側第１導電型領域の表面側の深さをＨ１とし、裏面側第１導電型領域の裏面側の深さをＨ２としたときに、第２導電型フローティング領域が、Ｈ１＋０．８×（Ｈ２−Ｈ１）の深さより表面側に形成されていることが好ましい。この条件を満たしていると、第２導電型フローティング領域による耐圧向上効果が効果的に発揮される。
第２導電型フローティング領域は、一層で形成されていてもよいが、複数層に分割されていてもよい。すなわち、複数個の中間深さのそれぞれに第２導電型フローティング領域が形成されていてもよい。複数枚の第２導電型フローティング領域を形成することによって、周辺領域での耐圧向上効果が改善される。 The second conductivity type floating region is preferably formed at an intermediate depth of the back side first conductivity type region. That is, when the thickness from the depth on the front surface side to the depth on the rear surface side of the first conductivity type region on the back surface side is divided into 10 equal parts, it is formed on the front surface side from a level at a position of 8/10 from the front surface side. It is preferable. When the depth on the front surface side of the back surface side first conductivity type region is H1, and the depth on the back surface side of the back surface side first conductivity type region is H2, the second conductivity type floating region is H1 + 0.8 × ( It is preferably formed on the surface side from the depth of H2-H1). If this condition is satisfied, the breakdown voltage improving effect by the second conductivity type floating region is effectively exhibited.
The second conductivity type floating region may be formed of one layer, but may be divided into a plurality of layers. That is, the second conductivity type floating region may be formed in each of the plurality of intermediate depths. By forming a plurality of second conductivity type floating regions, the effect of improving the breakdown voltage in the peripheral region is improved.

第１実施例の半導体装置の素子領域から周辺領域に亘る範囲の断面図。Sectional drawing of the range ranging from the element region of the semiconductor device of 1st Example to a peripheral region. 第２実施例の半導体装置の素子領域から周辺領域に亘る範囲の断面図。Sectional drawing of the range ranging from the element region of the semiconductor device of 2nd Example to a peripheral region. 第３実施例の半導体装置の素子領域から周辺領域に亘る範囲の断面図。Sectional drawing of the range ranging from the element region of the semiconductor device of 3rd Example to a peripheral region. 第４実施例の半導体装置の素子領域から周辺領域に亘る範囲の断面図。Sectional drawing of the range ranging from the element region of the semiconductor device of 4th Example to a peripheral region. 第５実施例の半導体装置の素子領域から周辺領域に亘る範囲の断面図。Sectional drawing of the range ranging from the element region of the semiconductor device of 5th Example to a peripheral region. 第６実施例の半導体装置の素子領域から周辺領域に亘る範囲の断面図。Sectional drawing of the range ranging from the element region of the semiconductor device of 6th Example to a peripheral region. 周辺領域の耐圧と、第２導電型フローティング領域の形成範囲の関係を示す図。The figure which shows the relationship between the withstand pressure | voltage of a peripheral region, and the formation range of a 2nd conductivity type floating region.

以下、本明細書で開示する技術の特徴を整理する。なお、以下に記す事項は、各々単独で技術的な有用性を有している。
（第１特徴）半導体基板はＳｉＣであり、半導体装置はＭＯＳである。本明細書でいう第１導電型はｎ型であり、第２導電型はｐ型である。素子領域では、半導体基板の表面から裏面に向けて、表面側第１導電型領域（ｎ型ソース領域）と第２導電型領域（ｐ型ボディ領域）と裏面側第１導電型領域（ｎ型ドリフト領域）と第１導電型領域（ｎ型ドレイン領域）の順に積層されている積層構造が形成されている。半導体基板の表面から、ｎ型ソース領域とｐ型ボディ領域を貫通してｎ型ドリフト領域に達するトレンチが形成されている。トレンチの壁面はゲート絶縁膜によって被覆されており、その内側にトレンチゲート電極が充填されている。
（第２特徴）周辺領域に形成されている第２導電型（ｐ型）不純物低濃度領域は、ｐ型ボディ領域に連続しており、リサーフ層と称される。第２導電型不純物高濃度リング状領域は、素子領域の周囲を多重に取り囲んでおり、ガードリングと称される。第２導電型フローティング領域は、周辺領域におけるｎ型ドリフト領域の中間深さに形成されている。 The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(First Feature) The semiconductor substrate is SiC, and the semiconductor device is MOS. In the present specification, the first conductivity type is n-type, and the second conductivity type is p-type. In the element region, from the front surface to the back surface of the semiconductor substrate, the front surface side first conductivity type region (n type source region), the second conductivity type region (p type body region), and the back surface side first conductivity type region (n type). A stacked structure in which a drift region) and a first conductivity type region (n-type drain region) are stacked in this order is formed. A trench is formed from the surface of the semiconductor substrate to reach the n-type drift region through the n-type source region and the p-type body region. A wall surface of the trench is covered with a gate insulating film, and a trench gate electrode is filled inside.
(Second Feature) The second conductivity type (p-type) impurity low concentration region formed in the peripheral region is continuous with the p-type body region and is called a RESURF layer. The second conductivity type impurity high-concentration ring-shaped region surrounds the element region in multiple layers and is called a guard ring. The second conductivity type floating region is formed at an intermediate depth of the n-type drift region in the peripheral region.

図１は、ＭＯＳとして動作する第１実施例の縦型半導体装置２の素子領域４から周辺領域６に亘る範囲の断面図を示している。参照番号８は半導体基板９の外周を示している。図１の左方には素子領域４が連続して延びている。半導体基板９はＳｉＣで形成されている。
参照番号１０は半導体基板９の表面に形成されている表面電極であり、ＭＯＳのソース電極となる。参照番号１８は半導体基板９の裏面に形成されている裏面電極であり、ＭＯＳのドレイン電極となる。 FIG. 1 shows a cross-sectional view of a range from the element region 4 to the peripheral region 6 of the vertical semiconductor device 2 of the first embodiment operating as a MOS. Reference numeral 8 indicates the outer periphery of the semiconductor substrate 9. The element region 4 extends continuously on the left side of FIG. The semiconductor substrate 9 is made of SiC.
Reference numeral 10 denotes a surface electrode formed on the surface of the semiconductor substrate 9 and serves as a MOS source electrode. Reference numeral 18 denotes a back electrode formed on the back surface of the semiconductor substrate 9 and serves as a MOS drain electrode.

半導体基板の表面から裏面に向かってトレンチが延びている。トレンチの壁面はゲート絶縁膜２４で覆われ、その内部にゲート電極２６が充填されている。
ゲート絶縁膜２４を介してゲート電極２６の側面に対向する位置には、半導体基板の表面側からソース領域２０とボディ領域１２とドリフト領域１４の順に積層された積層構造が形成されている。本実施例では、第１導電型がｎ型であり、第２導電型がｐ型である。ソース領域２０はｎ型であり、表面側第１導電型領域の実施例である。ボディ領域１２はｐ型であり、第２導電型領域の実施例である。ドリフト領域１４はｎ型であり、裏面側第１導電型領域の実施例である。ドリフト領域１４と裏面電極（ドレイン電極）１８の間にドレイン領域１６が形成されている。ドレイン領域１６はｎ型であり、第１導電型領域の実施例である。ゲート電極２６の側面には、ゲート絶縁膜２４を介してソース領域２０とドリフト領域１４を分離しているボディ領域１２が対向している。参照番号２２は、ボディコンタクト領域であり、表面電極（ソース電極）１０にオーミック接触し、ボディ領域１２の電位をソース電位に維持する。 A trench extends from the front surface to the back surface of the semiconductor substrate. A wall surface of the trench is covered with a gate insulating film 24, and a gate electrode 26 is filled therein.
A stacked structure in which the source region 20, the body region 12, and the drift region 14 are stacked in this order from the surface side of the semiconductor substrate is formed at a position facing the side surface of the gate electrode 26 with the gate insulating film 24 interposed therebetween. In this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. The source region 20 is n-type and is an embodiment of the surface side first conductivity type region. The body region 12 is p-type and is an example of the second conductivity type region. The drift region 14 is n-type, and is an embodiment of the back side first conductivity type region. A drain region 16 is formed between the drift region 14 and the back electrode (drain electrode) 18. The drain region 16 is n-type and is an embodiment of the first conductivity type region. The body region 12 that separates the source region 20 and the drift region 14 via the gate insulating film 24 faces the side surface of the gate electrode 26. Reference numeral 22 denotes a body contact region that is in ohmic contact with the surface electrode (source electrode) 10 and maintains the potential of the body region 12 at the source potential.

ソース領域２０の不純物濃度は表面電極（ソース電極）１０にオーミック接触する程度に濃い。ボディ領域１２の不純物濃度は、ゲート電極２６に正電圧を印加すると、ゲート絶縁膜２４を介してゲート電極２６の側面に対向する範囲がｎ型に反転する程度に薄い。また、ドリフト領域１４の不純物濃度は、ゲート電極２６に電圧を印加しないと、ボディ領域１２とドリフト領域１４の界面からドリフト領域１４の広い範囲に空乏層が広がる程度に薄い。ドレイン領域１６の不純物濃度は裏面電極（ドレイン電極）１８にオーミック接触する程度に濃い。   The impurity concentration of the source region 20 is high enough to make ohmic contact with the surface electrode (source electrode) 10. The impurity concentration in the body region 12 is so thin that when a positive voltage is applied to the gate electrode 26, the range facing the side surface of the gate electrode 26 via the gate insulating film 24 is inverted to n-type. Further, the impurity concentration of the drift region 14 is so thin that a depletion layer spreads over a wide range of the drift region 14 from the interface between the body region 12 and the drift region 14 when no voltage is applied to the gate electrode 26. The impurity concentration of the drain region 16 is high enough to make ohmic contact with the back electrode (drain electrode) 18.

上記の半導体構造を備えていると、ゲート電極２６に正電圧を印加した状態では、ゲート絶縁膜２４を介してゲート電極２６の側面に対向する範囲のボディ領域１２がｎ型に反転し、表面電極（ソース電極）１０と裏面電極（ドレイン電極）１８間の抵抗が低下する。ゲート電極２６に正電圧を印加しない状態では、ボディ領域１２とドリフト領域１４の界面からボディ領域１２とドリフト領域１４の広い範囲に空乏層が広がり、高い耐圧を得ることができる。   With the semiconductor structure described above, when a positive voltage is applied to the gate electrode 26, the body region 12 in a range facing the side surface of the gate electrode 26 through the gate insulating film 24 is inverted to n-type, and the surface The resistance between the electrode (source electrode) 10 and the back electrode (drain electrode) 18 decreases. In a state where no positive voltage is applied to the gate electrode 26, a depletion layer extends from the interface between the body region 12 and the drift region 14 to a wide range of the body region 12 and the drift region 14, and a high breakdown voltage can be obtained.

最外周のトレンチよりも半導体基板９の外周側には、周辺耐圧構造が形成されている。本明細書では、最外周のトレンチよりも内側の範囲を素子領域４といい、外周側の範囲を周辺領域６といい、その境界を参照符号Ｂで示す。
周辺領域６では、リサーフ層３２とガードリング群３０とフローティング層４０が形成されている。図示の便宜上、一部のガードリングに対してのみ、参照番号３０が付されている。リサーフ層３２はｐ型であり、ガードリング群３０よりも不純物濃度が低い。リサーフ層３２は、第２導電型不純物低濃度領域の実施例である。リサーフ層３２の不純物濃度は一様であってもよいが、半導体基板の外周８に近づくほど徐々に薄くなってもよい。個々のガードリング３０もｐ型であり、第２導電型不純物高濃度リング状領域の実施例である。複数本のガードリングが形成されている。複数本のガードリング３０が素子領域４の周囲を多重に取り囲んでいる。最外周のガードリング３０ｂは、リサーフ層３２の外側に形成されている。リサーフ層３２の外側に形成されているガードリングはなくてもよいし、１本以上を形成してもよい。周辺領域６では、ｎ型ドリフト領域１４の中間深さにｐ型層４０が形成されている。ｐ型層４０はｎ型のドリフト領域１４によって取り囲まれており、フローティング状態にある。ｐ型層４０は、第２導電型フローティング領域の実施例である。ｐ型層４０は、素子領域４と周辺領域６の境界位置Ｂから、最外周のガードリング３０ｂの存在位置Ｄ２まで、連続的に形成されている。周辺領域６では、半導体基板９の表面が絶縁膜２８で覆われている。また半導体基板０の外周８に接する位置の表面側には、ｎ型の不純物高濃度領域３６が形成されている。
ｐ型の領域、例えばボディコンタクト領域２２、ボディ領域１２、リサーフ層３２、ガードリング群３０、フローティング層４０は、リンを注入して形成することができる。ボロンを注入して形成することもできる。 A peripheral breakdown voltage structure is formed on the outer peripheral side of the semiconductor substrate 9 with respect to the outermost peripheral trench. In the present specification, a range on the inner side of the outermost trench is referred to as an element region 4, a range on the outer peripheral side is referred to as a peripheral region 6, and a boundary thereof is indicated by a reference sign B.
In the peripheral region 6, the RESURF layer 32, the guard ring group 30, and the floating layer 40 are formed. For convenience of illustration, reference numeral 30 is given only to some guard rings. The RESURF layer 32 is p-type and has a lower impurity concentration than the guard ring group 30. The RESURF layer 32 is an example of the second conductivity type impurity low concentration region. The impurity concentration of the RESURF layer 32 may be uniform, but may gradually decrease as the outer periphery 8 of the semiconductor substrate is approached. Each guard ring 30 is also p-type, and is an embodiment of the second conductivity type impurity high-concentration ring-shaped region. A plurality of guard rings are formed. A plurality of guard rings 30 surround the element region 4 in multiple layers. The outermost guard ring 30 b is formed outside the RESURF layer 32. There may be no guard ring formed outside the RESURF layer 32, or one or more guard rings may be formed. In peripheral region 6, p-type layer 40 is formed at an intermediate depth of n-type drift region 14. The p-type layer 40 is surrounded by the n-type drift region 14 and is in a floating state. The p-type layer 40 is an example of a second conductivity type floating region. The p-type layer 40 is continuously formed from the boundary position B between the element region 4 and the peripheral region 6 to the existing position D2 of the outermost guard ring 30b. In the peripheral region 6, the surface of the semiconductor substrate 9 is covered with an insulating film 28. An n-type impurity high concentration region 36 is formed on the surface side of the semiconductor substrate 0 at a position in contact with the outer periphery 8.
The p-type region, for example, the body contact region 22, the body region 12, the RESURF layer 32, the guard ring group 30, and the floating layer 40 can be formed by implanting phosphorus. It can also be formed by implanting boron.

周辺領域６に、リサーフ層３２と、ガードリング群３０と、フローティング層４０が形成されていると、周辺領域６における耐圧が向上する。本実施例の場合、リサーフ層３２とガードリング群３０を形成してフローティング層４０を形成しない場合の周辺領域６の耐圧は１０５０ボルトであった。それに対して、リサーフ層３２とガードリング群３０とフローティング層４０の全部を形成した場合の周辺領域６の耐圧は１４７０ボルトであった。フローティング層４０を追加することで、耐圧が４２０ボルト上昇した。
詳しくは後記するように、フローティング層４０が最内周のガードリング３０ａの存在位置Ｃより内側の位置から半導体基板９の外周８に向けて連続的に延びていると、フローティング層４０による耐圧向上効果が顕著に得られる。第１実施例では、フローティング層４０の内周側位置Ｅが、最内周のガードリング３０ａの存在位置Ｃよりも内側にあり、上記条件を満たしている。
また、フローティング層４０が周辺耐圧構造の外周側位置Ｄまで連続的に延びていると、フローティング層４０による耐圧向上効果が顕著に得られる。周辺耐圧構造の外周側位置Ｄは、リサーフ層３２とガードリング群３０の両者が形成されている領域の外周側位置のことをいう。図１に示すように、最外周ガードリング３０ｂの位置Ｄ２がリサーフ層３２の外周側位置Ｄ１より外側にある場合は、リサーフ層３２の外周側位置Ｄ１が周辺耐圧構造の外周側位置Ｄとなる。図３に示すように、最外周ガードリング３０ｂの位置Ｄ２がリサーフ層３２の外周側位置Ｄ１より内側にある場合は、最外周ガードリング３０ｂの位置Ｄ２が周辺耐圧構造の外周側位置Ｄとなる。第１実施例では、フローティング層４０の外周側位置Ｆが、周辺耐圧構造の外周側位置Ｄの外側まで延びており、上記条件を満たしている。
フローティング層４０が、最内周のガードリング３０ａの存在位置Ｃと周辺耐圧構造の外周側位置Ｄの間を連続的に延びていると、フローティング層４０による耐圧向上効果が顕著に得られる。 When the RESURF layer 32, the guard ring group 30, and the floating layer 40 are formed in the peripheral region 6, the breakdown voltage in the peripheral region 6 is improved. In the case of this example, the breakdown voltage of the peripheral region 6 when the RESURF layer 32 and the guard ring group 30 were formed and the floating layer 40 was not formed was 1050 volts. On the other hand, the breakdown voltage of the peripheral region 6 when the RESURF layer 32, the guard ring group 30, and the floating layer 40 are all formed is 1470 volts. By adding the floating layer 40, the breakdown voltage increased by 420 volts.
As will be described in detail later, when the floating layer 40 continuously extends from the position inside the position C where the innermost guard ring 30a exists toward the outer periphery 8 of the semiconductor substrate 9, the breakdown voltage is improved by the floating layer 40. The effect is remarkably obtained. In the first embodiment, the inner circumferential side position E of the floating layer 40 is on the inner side of the position C where the innermost guard ring 30a is present, and satisfies the above conditions.
In addition, when the floating layer 40 continuously extends to the outer peripheral side position D of the peripheral withstand voltage structure, the withstand voltage improvement effect by the floating layer 40 is remarkably obtained. The outer peripheral side position D of the peripheral withstand voltage structure refers to the outer peripheral side position of the region where both the RESURF layer 32 and the guard ring group 30 are formed. As shown in FIG. 1, when the position D2 of the outermost peripheral guard ring 30b is outside the outer peripheral side position D1 of the RESURF layer 32, the outer peripheral side position D1 of the RESURF layer 32 becomes the outer peripheral side position D of the peripheral pressure-resistant structure. . As shown in FIG. 3, when the position D2 of the outermost peripheral guard ring 30b is inside the outer peripheral side position D1 of the RESURF layer 32, the position D2 of the outermost peripheral guard ring 30b becomes the outer peripheral side position D of the peripheral pressure-resistant structure. . In the first embodiment, the outer peripheral side position F of the floating layer 40 extends to the outer side of the outer peripheral side position D of the peripheral withstand voltage structure, and satisfies the above conditions.
When the floating layer 40 continuously extends between the position C where the innermost guard ring 30a is present and the outer peripheral side position D of the peripheral pressure-resistant structure, the effect of improving the breakdown voltage by the floating layer 40 is significantly obtained.

（第２実施例）
以下では、図２以降を参照して第２実施例以降を説明する。第１実施例と同じ部分については同じ参照番号を使うことによって重複説明を省略する。なお、フローティング層に関しては、実施例毎に相違するので、４０，５０，６０，７０，８０，９０の番号を使用する。
フローティング層５０の形成範囲は、図１に示したＢからＤ２の位置までには限定されない。図２に示す第２実施例では、フローティング層５０の最も内側の位置Ｅは、素子領域４と周辺領域６の境界Ｂよりも外側にある。内周側位置Ｅが境界Ｂより外側であっても、内周側位置Ｅが最内周ガードリング３０ａの形成位置Ｃよりも内側にあれば、フローティング層５０によって周辺領域６の耐圧向上効果が得られる。また、フローティング層５０の外周側位置Ｆは、半導体基板９の表面に臨む範囲に形成されている周辺耐圧構造の外周側位置Ｄより外側にまで延びていることが好ましい。図２の場合、リサーフ層３２の外側に最外周ガードリング３０ｂが形成されており、周辺耐圧構造の外周側位置Ｄはリサーフ層３２の外周側位置Ｄ１となる。図３に示すように、リサーフ層３２の外側にガードリングが形成されていない場合は、周辺耐圧構造の外周側位置Ｄは最外周ガードリング３０ｂの位置Ｄ２となる。 (Second embodiment)
Hereinafter, the second and subsequent embodiments will be described with reference to FIG. About the same part as 1st Example, duplication description is abbreviate | omitted by using the same reference number. Since the floating layer is different for each embodiment, the numbers 40, 50, 60, 70, 80, and 90 are used.
The formation range of the floating layer 50 is not limited to the position from B to D2 shown in FIG. In the second embodiment shown in FIG. 2, the innermost position E of the floating layer 50 is outside the boundary B between the element region 4 and the peripheral region 6. Even if the inner circumferential position E is outside the boundary B, the floating layer 50 can improve the breakdown voltage of the peripheral region 6 if the inner circumferential position E is inside the innermost guard ring 30a formation position C. can get. Further, it is preferable that the outer peripheral side position F of the floating layer 50 extends to the outer side from the outer peripheral side position D of the peripheral withstand voltage structure formed in the range facing the surface of the semiconductor substrate 9. In the case of FIG. 2, the outermost peripheral guard ring 30 b is formed outside the RESURF layer 32, and the outer peripheral side position D of the peripheral breakdown voltage structure is the outer peripheral side position D1 of the RESURF layer 32. As shown in FIG. 3, when the guard ring is not formed outside the RESURF layer 32, the outer peripheral side position D of the peripheral withstand voltage structure is the position D2 of the outermost peripheral guard ring 30b.

図７の縦軸は周辺領域の耐圧を示し、レベル９０は、リサーフ層３２とガードリング群３０を形成してフローティング層を形成しない場合の耐圧を示している。図７の横軸は、フローティング層の外周側位置Ｆと、半導体基板の表面に臨む範囲に形成されている周辺耐圧構造の外周側位置Ｄとの位置関係を示している。位置Ｆが位置Ｄより外側にある場合をプラスとしている。図７に示すように、フローティング層を追加することで耐圧が向上するが、その耐圧向上効果はフローティング層が延びている外周側位置Ｆによって変化し、位置Ｆが位置Ｄより外側にあるほど耐圧向上効果が増大することがわかる。
図７において、ゼロの点は、位置Ｄ１とＤ２のうちの内側の方を示している。５μｍの位置は、位置Ｄ１とＤ２のうちの外側の方を示している。フローティング層は、リサーフ層３２とガードリング群３０の双方が形成されている位置Ｄまでは延び、好ましくは、リサーフ層３２とガードリング群３０いずれかが形成されている位置（Ｄ１とＤ２のうちの外側の方）まで延びていることが好ましい。
それに対して、フローティング層の内周側位置Ｅについては、耐圧向上効果に与える影響が小さく、図２に示すように、境界Ｂよりも外側にあっても、最内周ガードリング３０ａの形成位置Ｃよりも内側にあれば、必要な耐圧向上効果を得ることができる。ガードリング群３０では、最内周のガードリング３０ａから外周側のガードリングに向けて順々に電位が分担されている。フローティング層が最内周ガードリング３０ａの形成位置Ｃより内側の位置から外側に向かって連続的に形成されていると、フローティング層によって効率よく電位分担することができる。 The vertical axis in FIG. 7 indicates the breakdown voltage of the peripheral region, and the level 90 indicates the breakdown voltage when the RESURF layer 32 and the guard ring group 30 are formed and the floating layer is not formed. The abscissa in FIG. 7 shows the positional relationship between the outer peripheral side position F of the floating layer and the outer peripheral side position D of the peripheral withstand voltage structure formed in the range facing the surface of the semiconductor substrate. The case where the position F is outside the position D is positive. As shown in FIG. 7, the breakdown voltage is improved by adding the floating layer, but the breakdown voltage improvement effect varies depending on the outer peripheral side position F where the floating layer extends, and the breakdown voltage increases as the position F is located outside the position D. It can be seen that the improvement effect increases.
In FIG. 7, the zero point indicates the inner side of the positions D1 and D2. The position of 5 μm indicates the outer side of the positions D1 and D2. The floating layer extends to a position D where both the RESURF layer 32 and the guard ring group 30 are formed, and preferably, the position where either the RESURF layer 32 and the guard ring group 30 are formed (of D1 and D2) It is preferable that it extends to the outer side.
On the other hand, the inner peripheral side position E of the floating layer has a small influence on the breakdown voltage improvement effect, and as shown in FIG. 2, the innermost peripheral guard ring 30a is formed even if it is outside the boundary B. If it is on the inner side than C, the required withstand voltage improvement effect can be obtained. In the guard ring group 30, potentials are sequentially shared from the innermost guard ring 30 a toward the outer guard ring. When the floating layer is formed continuously from the position inside the formation position C of the innermost guard ring 30a toward the outside, the potential can be efficiently shared by the floating layer.

（第３実施例）
図３に示すように、フローティング層６０の最も内側の位置Ｅが、境界Ｂよりも内側にあってもよい。すなわちフローティング層６０が素子領域４内にまで入り込んでいてもよい。その場合も、フローティング層６０による耐圧向上効果を得ることができる。フローティング層６０が素子領域４内にまで入り込んでいると、素子領域のオン抵抗が増大する可能性があるが、その侵入距離が小さければオン抵抗に与える影響を無視することができる。図３において、記号Ａは、最外周のゲート電極から内側に２本目のゲート電極の形成位置を示している。フローティング層６０の内周側位置Ｅが、ＡとＣの間（つなぎ領域Ｚ内）にあれば、素子領域のオン抵抗が増大するのを防止しながら、周辺領域での耐圧を向上させることができる。 (Third embodiment)
As shown in FIG. 3, the innermost position E of the floating layer 60 may be inside the boundary B. That is, the floating layer 60 may enter the element region 4. Also in this case, the effect of improving the breakdown voltage due to the floating layer 60 can be obtained. If the floating layer 60 penetrates into the element region 4, the on-resistance of the element region may increase. However, if the penetration distance is small, the influence on the on-resistance can be ignored. In FIG. 3, symbol A indicates the formation position of the second gate electrode inward from the outermost peripheral gate electrode. If the inner peripheral position E of the floating layer 60 is between A and C (within the connecting region Z), it is possible to improve the breakdown voltage in the peripheral region while preventing the on-resistance of the element region from increasing. it can.

（第４実施例）
図４に示すように、フローティング層７０の内側部分に、開孔７０ａ〜７０ｄを形成してもよい。開孔７０ａ〜７０ｄは、素子領域４を一巡していてもよいし、ゲート電極２６と平行に延びていてもよい。フローティング層７０の内周側位置Ｅが、Ａの位置より外側にあれば、素子領域のオン抵抗が増大するのを防止できる。フローティング層７０がＣ位置より外側で連続していれば（すなわちＣ位置より外側では開口が形成されていなければ）、フローティング層７０によって周辺領域での耐圧を向上させることができる。開孔７０ａ〜７０ｄを形成する場合には、フローティング層７０の内周側位置Ｅを素子領域４に深く侵入させることができる。すなわちＡ位置に近づけることができる。 (Fourth embodiment)
As shown in FIG. 4, openings 70 a to 70 d may be formed in the inner portion of the floating layer 70. The openings 70 a to 70 d may go around the element region 4 or may extend in parallel with the gate electrode 26. If the inner peripheral side position E of the floating layer 70 is outside the position A, it is possible to prevent the ON resistance of the element region from increasing. If the floating layer 70 is continuous outside the C position (that is, if no opening is formed outside the C position), the floating layer 70 can improve the breakdown voltage in the peripheral region. When the openings 70 a to 70 d are formed, the inner peripheral side position E of the floating layer 70 can be deeply penetrated into the element region 4. That is, it can be brought close to the A position.

（第５実施例）
図１〜図４の実施例では、フローティング層が一層で形成されているが、図５に示すように、複数のフローティング層８０ａ，８０ｂが形成されていてもよい。すなわち、ドリフト層１４の複数個の中間深さにフローティング層を形成してもよい。図５の場合、それぞれのフローティング層が、少なくとも位置Ｃから位置Ｄにまで連続的に延びている。それに代え、個々のフローティング層の形成範囲を重複させたときに、位置Ｃから位置Ｄにまで連続的に延びる構成としてもよい。 (5th Example)
1 to 4, the floating layer is formed as a single layer, but a plurality of floating layers 80a and 80b may be formed as shown in FIG. That is, the floating layer may be formed at a plurality of intermediate depths of the drift layer 14. In the case of FIG. 5, each floating layer extends continuously from at least position C to position D. Instead, it may be configured to continuously extend from position C to position D when the formation ranges of the individual floating layers are overlapped.

（第６実施例）
図６は、プレーナ−ゲート電極２６を利用するＭＯＳを示す。図１〜５に示したトレンチゲート型ＭＯＳと、同等または均等の部材には同じ参照番号を付して重複記載を省略する。プレーナ−ゲート電極２６を利用する縦型半導体装置の場合でも、最内周ガードリング３０ａの形成位置Ｃより内側の位置から、周辺対圧構造の外周側位置Ｄに一致するかあるいはその外側まで伸びるフローティング領域９０を形成することで、周辺領域の耐圧を向上させることができる。 (Sixth embodiment)
FIG. 6 shows a MOS that uses the planar gate electrode 26. The same reference numerals are assigned to the same or equivalent members as in the trench gate type MOS shown in FIGS. Even in the case of a vertical semiconductor device that uses the planar gate electrode 26, it extends from the position inside the innermost peripheral guard ring 30a formation position C to the outer peripheral position D of the peripheral counter pressure structure or extends to the outside. By forming the floating region 90, the breakdown voltage of the peripheral region can be improved.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
例えば、第１導電型をｐ型として第２導電型をｎ型とすることができる。また、ＭＯＳに代えてＩＧＢＴに適用することもできる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, the first conductivity type may be p-type and the second conductivity type may be n-type. Further, it can be applied to IGBT instead of MOS.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

２：ＭＯＳとして動作する縦型半導体装置
４：素子領域
６：周辺領域
８：半導体基板の外周
９：半導体基板
１０：表面電極（ソース電極）
１２：第２導電型領域（ｐ型ボディ領域）
１４：裏面側第１導電型領域（ｎ型ドリフト領域）
１６：第１導電型領域（ｎ型ドレイン領域）
１８：裏面電極（ドレイン電極）
２０：表面側第１導電型領域（ｎ型ソース領域）
２２：ボディコンタクト領域
２４：ゲート絶縁膜
２６：ゲート電極
３０：第２導電型不純物高濃度リング状領域（ガードリング）
３２：第２導電型不純物低濃度領域（リサーフ層）
３６：第１導電型領域
４０，５０，６０，７０，８０，９０：第２導電型フローティング領域（ｐ型フローティング層）
Ａ：最外周ゲート電極から内側に２本目のゲート電極の形成位置
Ｂ：素子領域と周辺領域の境界：最外周ゲート電極の形成位置
Ｃ：最内周ガードリングの形成位置
Ｄ１：リサーフ層の外周側位置
Ｄ２：最外周ガードリングの形成位置
Ｄ：周辺耐圧構造の外周側位置（Ｄ１とＤ２のうちの内側の位置）
Ｅ：フローティング領域の内周側位置
Ｆ：フローティング領域の外周側位置 2: Vertical semiconductor device operating as MOS 4: Element region 6: Peripheral region 8: Perimeter of semiconductor substrate 9: Semiconductor substrate 10: Surface electrode (source electrode)
12: Second conductivity type region (p-type body region)
14: Back side first conductivity type region (n-type drift region)
16: First conductivity type region (n-type drain region)
18: Back electrode (drain electrode)
20: Surface side first conductivity type region (n-type source region)
22: body contact region 24: gate insulating film 26: gate electrode 30: second conductivity type impurity high concentration ring-shaped region (guard ring)
32: Second conductivity type impurity low concentration region (Resurf layer)
36: First conductivity type region 40, 50, 60, 70, 80, 90: Second conductivity type floating region (p-type floating layer)
A: formation position of the second gate electrode inside the outermost peripheral gate electrode B: boundary between the element region and the peripheral region: formation position of the outermost peripheral gate electrode C: formation position of the innermost guard ring D1: outer periphery of the RESURF layer Side position D2: formation position of outermost peripheral guard ring D: outer peripheral side position of peripheral pressure-resistant structure (inside position of D1 and D2)
E: Inner side position of floating region F: Outer side position of floating region

Claims (5)

半導体基板を平面視したときに素子領域と素子領域を一巡する周辺領域を備えており、
素子領域では、半導体基板の表面に形成されている表面電極と、半導体基板の裏面に形成されている裏面電極と、前記表面電極に導通している表面側第１導電型領域と、前記裏面電極に導通している裏面側第１導電型領域と、前記表面側第１導電型領域と前記裏面側第１導電型領域を分離している第２導電型領域と、前記表面側第１導電型領域と前記裏面側第１導電型領域を分離している範囲の前記第２導電型領域にゲート絶縁膜を介して対向しているゲート電極が形成されており、前記ゲート電極の電圧によって前記表面電極と前記裏面電極の間の抵抗が変化し、
周辺領域では、半導体基板の表面と外周の双方に臨む位置に形成されている第１導電型不純物高濃度領域と、素子領域に接する位置から前記第１導電型不純物高濃度領域に向けて延びているものの前記第１導電型不純物高濃度領域に達していない範囲の半導体基板の表面に臨む位置に形成されている第２導電型不純物低濃度領域と、半導体基板の表面に臨む範囲において素子領域を一巡している第２導電型不純物高濃度リング状領域の多重構造と、前記裏面側第１導電型領域の中間深さに形成されている第２導電型フローティング領域を備えており、
前記第２導電型不純物高濃度リング状領域の多重構造の少なくとも一部は、前記第２導電型不純物低濃度領域に含まれる範囲に形成されており、
前記第２導電型フローティング領域が、最内周の前記第２導電型不純物高濃度リング状領域より内側の位置から、半導体基板の外周に向けて、前記第２導電型不純物低濃度領域と前記第２導電型不純物高濃度リング状領域の多重構造の両者が配置されている領域の外周側位置より外側にまで、連続的に延びているとともに、前記第１導電型不純物高濃度領域の裏面側に達していないことを特徴とする縦型半導体装置。 When the semiconductor substrate is viewed in plan, it has a peripheral region that goes around the device region and the device region,
In the element region, a front surface electrode formed on the front surface of the semiconductor substrate, a back surface electrode formed on the back surface of the semiconductor substrate, a front side first conductivity type region electrically connected to the front surface electrode, and the back surface electrode A backside first conductivity type region that is electrically connected to the surface, a second conductivity type region that separates the front side first conductivity type region and the back side first conductivity type region, and the front side first conductivity type. A gate electrode is formed opposite to the second conductivity type region in a range separating the region and the back side first conductivity type region through a gate insulating film; The resistance between the electrode and the back electrode changes,
In the peripheral region, a first conductivity type impurity high concentration region formed at a position facing both the surface and the outer periphery of the semiconductor substrate, and extending from a position in contact with the element region toward the first conductivity type impurity high concentration region. A second conductivity type impurity low concentration region formed at a position facing the surface of the semiconductor substrate in a range not reaching the first conductivity type impurity high concentration region, and an element region in the range facing the surface of the semiconductor substrate. A second structure of the second conductivity type impurity high-concentration ring-shaped region in a circuit and a second conductivity type floating region formed at an intermediate depth of the first conductivity type region on the back surface side;
At least a part of the multiple structure of the second conductivity type impurity high-concentration ring-shaped region is formed in a range included in the second conductivity type impurity low-concentration region;
The second conductivity type floating region, from the inside of the position from the innermost circumference of the second conductivity type high impurity concentration ring area, towards the periphery of the semiconductor substrate, the said second conductivity type impurity low concentration region first to the outside from the outer peripheral side position of the region where both the multiple structure of the second conductivity type high impurity concentration ring region is located, both the extend continuously, the back surface side of the first conductivity type high impurity concentration regions A vertical semiconductor device characterized by not reaching the above . 前記半導体基板がＳｉＣで形成されており、前記表面側第１導電型領域がソース領域であり、前記第２導電型領域がボディ領域であり、前記裏面側第１導電型領域がドリフト領域であり、前記裏面側第１導電型領域と前記裏面電極の間に第１導電型のドレイン領域が形成されていることを特徴とする請求項１に記載の縦型半導体装置。   The semiconductor substrate is made of SiC, the front side first conductivity type region is a source region, the second conductivity type region is a body region, and the back side first conductivity type region is a drift region. 2. The vertical semiconductor device according to claim 1, wherein a drain region of the first conductivity type is formed between the back side first conductivity type region and the back electrode. 前記第２導電型フローティング領域が、前記第２導電型不純物低濃度領域と前記第２導電型不純物高濃度リング状領域の多重構造の少なくとも一方が配置されている領域の外周側位置より外側にまで延びていることを特徴とする請求項１または２に記載の縦型半導体装置。 The second conductivity type floating region extends outside a position on the outer peripheral side of a region where at least one of the multiple structure of the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region is disposed. The vertical semiconductor device according to claim 1, wherein the vertical semiconductor device extends. 前記裏面側第１導電型領域の表面側の深さをＨ１とし、前記裏面側第１導電型領域の裏面側の深さをＨ２としたときに、前記第２導電型フローティング領域が、Ｈ１＋０．８×（Ｈ２−Ｈ１）の深さより表面側に形成されていることを特徴とする請求項１〜３のいずれかの１項に記載の縦型半導体装置。   When the depth on the front surface side of the back surface side first conductivity type region is H1, and the depth on the back surface side of the back surface side first conductivity type region is H2, the second conductivity type floating region is H1 + 0. 4. The vertical semiconductor device according to claim 1, wherein the vertical semiconductor device is formed on a surface side from a depth of 8 × (H 2 −H 1). 5. 前記裏面側第１導電型領域の複数個の中間深さのそれぞれに、前記第２導電型フローティング領域が形成されていることを特徴とする請求項１〜４のいずれかの１項に記載の縦型半導体装置。 Each of the plurality of intermediate depth before Symbol rear surface-side first conductive type region, according to any one of claims 1 to 4, characterized in that said second conductivity type floating region is formed Vertical semiconductor device.
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