JP6224454B2 - Vertical semiconductor device - Google Patents

Vertical semiconductor device Download PDF

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JP6224454B2
JP6224454B2 JP2013271576A JP2013271576A JP6224454B2 JP 6224454 B2 JP6224454 B2 JP 6224454B2 JP 2013271576 A JP2013271576 A JP 2013271576A JP 2013271576 A JP2013271576 A JP 2013271576A JP 6224454 B2 JP6224454 B2 JP 6224454B2
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JP2015126192A (en
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佐智子 青井
佐智子 青井
渡辺 行彦
行彦 渡辺
順 斎藤
順 斎藤
巨裕 鈴木
巨裕 鈴木
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株式会社豊田中央研究所
トヨタ自動車株式会社
株式会社デンソー
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Description

  The present specification discloses a vertical semiconductor device that can change the resistance between a front surface electrode formed on the surface of a semiconductor substrate and a back surface electrode formed on the back surface of the semiconductor substrate. In particular, a vertical semiconductor device is disclosed that includes an element region in which a semiconductor structure for changing the resistance is formed and a peripheral region that goes around the element region.

  2. Description of the Related Art A vertical semiconductor device in which resistance between a front electrode and a back electrode changes according to a voltage applied to a gate electrode is known. In the case of MOS, a body region that separates a source region and a drift region and a gate electrode that faces the body region through a gate insulating film are provided. Alternatively, the IGBT includes a body region that separates the emitter region and the drift region, and a gate electrode that faces the body region via a gate insulating film. In any case, a second conductivity type region (body region) that separates the front side first conductivity type region (source region or emitter region) and the back side first conductivity type region (drift region), and the second conductivity type region Are provided with a gate electrode facing each other through a gate insulating film. When an inversion layer is formed in the second conductivity type region (body region) in the range facing the gate electrode through the gate insulating film by applying an on-voltage to the gate electrode, the resistance between the front electrode and the back electrode decreases. .

  When the voltage applied between the front electrode and the back electrode is increased, a phenomenon occurs in which a current flows between the front electrode and the back electrode although no on-voltage is applied to the gate electrode. In this specification, this phenomenon is said to break the breakdown voltage. In order to increase the breakdown voltage, various improvements have been made to the semiconductor structure formed in the element region.

  By simply improving the semiconductor structure formed in the element region, if the voltage applied between the front electrode and the back electrode is increased, a current flows between the front electrode and the back electrode via the peripheral region of the semiconductor substrate. . In order to improve the breakdown voltage, the semiconductor structure in the peripheral region needs to be improved.

Patent Documents 1 and 2 disclose a technique for forming a second conductivity type impurity region in a range that faces the surface of a semiconductor substrate and goes around the device region. Since it goes around the element region, it has a ring shape. In the techniques of Patent Documents 1 and 2, a plurality of ring-shaped regions are arranged in a multiple manner around the element region. In this specification, this technique is called a guard ring structure. When the guard ring structure is arranged in the peripheral region, the breakdown voltage in the peripheral region is improved.
In FIG. 9 of Patent Document 1, in order to further improve the breakdown voltage in the peripheral region, in addition to the guard ring structure, the second conductivity type region (drift region) is formed at an intermediate depth of the back side first conductivity type region (drift region). Patent Document 1 discloses a technique for forming a P + potential fixing region). In the technique of Patent Document 1, a plurality of second conductivity type regions are arranged in a discrete manner (that is, at positions separated from each other).
In Patent Document 2, in order to improve the breakdown voltage in the peripheral region, in addition to the guard ring structure, a second conductivity type impurity region (referred to as RESURF layer in Patent Document 2) is provided in a range facing the surface of the semiconductor substrate. Techniques for forming the are disclosed. Both the RESURF layer and the guard ring are of the second conductivity type, but the RESURF layer and the guard ring are distinguished from each other because the former impurity concentration is lower than the latter impurity concentration. In Patent Document 2, a guard ring structure is formed within a range covered by the RESURF layer.

JP 2007-31822 A JP 2003-101039 A

In order to protect the semiconductor device from destruction, it is preferable that “the breakdown voltage of the element region <the breakdown voltage of the peripheral region”. When the relationship is obtained, when the breakdown voltage is broken, a relationship in which the breakdown voltage is broken in the element region can be obtained. The area of the element region is larger than the area of the peripheral region. When the breakdown voltage is broken in a wide region, the current density can be lowered and the semiconductor device can be prevented from being destroyed as compared with the case where the breakdown voltage is broken in a narrow region. Before the semiconductor device is destroyed, it is possible to carry out processing for an abnormal event in which the breakdown voltage is broken.
In the structure described in Patent Document 1, “a plurality of second conductivity type regions are arranged at intermediate depths between the guard ring structure and the first conductivity type region on the back surface side”, the second is arranged in a discrete manner. The depletion layer does not develop sufficiently from the interface between the conductive type region and the back side first conductive type region. It is difficult to obtain the relationship of “breakdown voltage of element region <breakdown voltage of peripheral region”.
Even in the structure of “disposing the guard ring structure inside the RESURF region” described in Patent Document 2, it is difficult to obtain the relationship “the breakdown voltage of the element region <the breakdown voltage of the peripheral region”.
In this specification, a semiconductor structure capable of obtaining the relationship of “breakdown voltage of element region <breakdown voltage of peripheral region” is proposed.

The semiconductor device disclosed in this specification includes an element region and a peripheral region that goes around the element region when the semiconductor substrate is viewed in plan.
In the element region, a front surface electrode formed on the surface of the semiconductor substrate, a back surface electrode formed on the back surface of the semiconductor substrate, and a first conductive type region on the surface side that conducts to the front surface electrode (source region in the case of MOS) In the case of an IGBT, an emitter region), a back side first conductivity type region (drift region) conducting to the back electrode, and a front side first conductivity type region and a back side first conductivity type region are separated. A gate electrode is provided opposite to the second conductivity type region (body region) and the second conductivity type region in a range separating the first conductivity type region on the front surface side and the first conductivity type region on the back surface side through a gate insulating film. . When the semiconductor structure is provided, the resistance between the front electrode and the back electrode changes depending on the voltage of the gate electrode.

In the peripheral region of the semiconductor device disclosed in this specification, the first conductivity type impurity high concentration region formed at a position facing both the surface and the outer periphery of the semiconductor substrate, and the first conductivity type impurity from the position in contact with the element region. A second conductivity type impurity low concentration region formed at a position facing the surface of the semiconductor substrate in a range extending toward the high concentration region but not reaching the first conductivity type impurity high concentration region; and a surface of the semiconductor substrate And a second conductive type floating region formed at an intermediate depth of the first conductive type region on the back surface side. ing. The second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring region formed in the peripheral region both contain the second conductivity type impurity, and the second conductivity type impurity high concentration ring region At least a part of the multiple structure is formed in a range included in the second conductivity type impurity low concentration region. Since the impurity concentration is different between the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region, and the former impurity concentration is lower than the latter impurity concentration , both can be distinguished. The second conductivity type floating region has a second conductivity type impurity low concentration region and a second conductivity type impurity from a position inside the innermost second conductivity type impurity high concentration ring-shaped region toward the outer periphery of the semiconductor substrate. It extends continuously from the outer peripheral side position of the region where both of the multiple structures of the high-density ring-shaped region are arranged . However, it does not reach the back side of the first conductivity type impurity high concentration region . Here, the "communication has continued to extend" means "without being divided into a plurality of regions extending continuously".

  In the semiconductor device, a combination of “second conductivity type impurity low concentration region + second conductivity type impurity high concentration ring region + second conductivity type floating region” is formed in the peripheral region. According to the above structure, not only the depletion layer develops from the interface between the backside first conductivity type region (drift region) and the second conductivity type impurity low concentration region, but also the backside first conductivity type region (drift region) and the second A depletion layer develops also from the interface of the two-conductivity floating region, and a wide range of the peripheral region is depleted and the breakdown voltage is improved. Further, the degree of concentration in the electric field concentration region formed around the depletion layer is relaxed, and the breakdown voltage is improved by the action. As a result, it is possible to ensure a higher breakdown voltage than the element region in which the breakdown voltage is ensured mainly by the depletion layer that develops from the interface between the second conductivity type region and the back side first conductivity type region. That is, the relationship of “breakdown voltage of element region <breakdown voltage of peripheral region” can be obtained. When the relationship is obtained, when the breakdown voltage is broken, a relationship in which the breakdown voltage is broken in the element region can be obtained. The area of the element region is larger than the area of the peripheral region. When the breakdown voltage is broken in a wide region, the current density can be lowered and the semiconductor device can be prevented from being destroyed as compared with the case where the breakdown voltage is broken in a narrow region. Before the semiconductor device is destroyed, it is possible to perform processing for an abnormal event that breaks the breakdown voltage.

When the semiconductor substrate is made of SiC, the defect density is high and the resistance of the p-type SiC region is high. Therefore, it is difficult to ensure the breakdown voltage in the peripheral region with the conventional peripheral breakdown voltage structure. In particular, in the case of a MOS in which the body region that separates the source region and the drift region is opposed to the gate electrode through the gate insulating film, and the drain region is formed between the drift region and the back surface electrode, It is difficult to ensure a breakdown voltage. Since SiC has a higher defect density than Si, the conventional peripheral voltage structure in which the floating region is formed in a discrete manner functions effectively for Si, but does not function effectively for SiC. .
When the MOS is formed of SiC, the intermediate depth of the first conductivity type region (drift region) on the back surface side is directed from the inner position to the outer periphery of the semiconductor substrate from the innermost second conductivity type impurity high-concentration ring-shaped region. It is particularly effective to form the second conductive type floating region extending continuously.

In either case, the relationship between the formation range of the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region formed at a position facing the surface of the semiconductor substrate is either of the following.
(1) The latter extends outside the former. Or ring-shaped region of the outermost periphery is formed outside the second conductivity type impurity low concentration region. In this case, it is preferable that the second conductivity type floating region extends to the outside from the outer peripheral side position of the second conductivity type impurity low concentration region.
(2) The former extends outward beyond the latter. Or ring-shaped region of the outermost periphery are formed inside the second conductivity type impurity low concentration region. In this case, it is preferable that the second conductivity type floating region extends from the position of the outermost ring-shaped region to the outside.
That is, the second conductivity type floating region extends to the outside from the outer peripheral side position of the region where both the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region multiple structure are arranged. Preferably it is.
When the above relationship is satisfied, the effect of improving the breakdown voltage of the peripheral region is significantly exhibited by forming the second conductivity type floating region.
In the case of (1) above, it is more preferable that the second conductivity type floating region extends to the outside from the position of the outermost ring region. In the case of (2) above, it is more preferable that the second conductivity type floating region extends outward from the outer peripheral side position of the second conductivity type impurity low concentration region. In other words, the second conductivity type floating region extends outward from the outer peripheral side position of the region where at least one of the multiple structure of the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring region is disposed. More preferably.

The second conductivity type floating region is preferably formed at an intermediate depth of the back side first conductivity type region. That is, when the thickness from the depth on the front surface side to the depth on the rear surface side of the first conductivity type region on the back surface side is divided into 10 equal parts, it is formed on the front surface side from a level at a position of 8/10 from the front surface side. It is preferable. When the depth on the front surface side of the back surface side first conductivity type region is H1, and the depth on the back surface side of the back surface side first conductivity type region is H2, the second conductivity type floating region is H1 + 0.8 × ( It is preferably formed on the surface side from the depth of H2-H1). If this condition is satisfied, the breakdown voltage improving effect by the second conductivity type floating region is effectively exhibited.
The second conductivity type floating region may be formed of one layer, but may be divided into a plurality of layers. That is, the second conductivity type floating region may be formed in each of the plurality of intermediate depths. By forming a plurality of second conductivity type floating regions, the effect of improving the breakdown voltage in the peripheral region is improved.

Sectional drawing of the range ranging from the element region of the semiconductor device of 1st Example to a peripheral region. Sectional drawing of the range ranging from the element region of the semiconductor device of 2nd Example to a peripheral region. Sectional drawing of the range ranging from the element region of the semiconductor device of 3rd Example to a peripheral region. Sectional drawing of the range ranging from the element region of the semiconductor device of 4th Example to a peripheral region. Sectional drawing of the range ranging from the element region of the semiconductor device of 5th Example to a peripheral region. Sectional drawing of the range ranging from the element region of the semiconductor device of 6th Example to a peripheral region. The figure which shows the relationship between the withstand pressure | voltage of a peripheral region, and the formation range of a 2nd conductivity type floating region.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(First Feature) The semiconductor substrate is SiC, and the semiconductor device is MOS. In the present specification, the first conductivity type is n-type, and the second conductivity type is p-type. In the element region, from the front surface to the back surface of the semiconductor substrate, the front surface side first conductivity type region (n type source region), the second conductivity type region (p type body region), and the back surface side first conductivity type region (n type). A stacked structure in which a drift region) and a first conductivity type region (n-type drain region) are stacked in this order is formed. A trench is formed from the surface of the semiconductor substrate to reach the n-type drift region through the n-type source region and the p-type body region. A wall surface of the trench is covered with a gate insulating film, and a trench gate electrode is filled inside.
(Second Feature) The second conductivity type (p-type) impurity low concentration region formed in the peripheral region is continuous with the p-type body region and is called a RESURF layer. The second conductivity type impurity high-concentration ring-shaped region surrounds the element region in multiple layers and is called a guard ring. The second conductivity type floating region is formed at an intermediate depth of the n-type drift region in the peripheral region.

FIG. 1 shows a cross-sectional view of a range from the element region 4 to the peripheral region 6 of the vertical semiconductor device 2 of the first embodiment operating as a MOS. Reference numeral 8 indicates the outer periphery of the semiconductor substrate 9. The element region 4 extends continuously on the left side of FIG. The semiconductor substrate 9 is made of SiC.
Reference numeral 10 denotes a surface electrode formed on the surface of the semiconductor substrate 9 and serves as a MOS source electrode. Reference numeral 18 denotes a back electrode formed on the back surface of the semiconductor substrate 9 and serves as a MOS drain electrode.

A trench extends from the front surface to the back surface of the semiconductor substrate. A wall surface of the trench is covered with a gate insulating film 24, and a gate electrode 26 is filled therein.
A stacked structure in which the source region 20, the body region 12, and the drift region 14 are stacked in this order from the surface side of the semiconductor substrate is formed at a position facing the side surface of the gate electrode 26 with the gate insulating film 24 interposed therebetween. In this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. The source region 20 is n-type and is an embodiment of the surface side first conductivity type region. The body region 12 is p-type and is an example of the second conductivity type region. The drift region 14 is n-type, and is an embodiment of the back side first conductivity type region. A drain region 16 is formed between the drift region 14 and the back electrode (drain electrode) 18. The drain region 16 is n-type and is an embodiment of the first conductivity type region. The body region 12 that separates the source region 20 and the drift region 14 via the gate insulating film 24 faces the side surface of the gate electrode 26. Reference numeral 22 denotes a body contact region that is in ohmic contact with the surface electrode (source electrode) 10 and maintains the potential of the body region 12 at the source potential.

  The impurity concentration of the source region 20 is high enough to make ohmic contact with the surface electrode (source electrode) 10. The impurity concentration in the body region 12 is so thin that when a positive voltage is applied to the gate electrode 26, the range facing the side surface of the gate electrode 26 via the gate insulating film 24 is inverted to n-type. Further, the impurity concentration of the drift region 14 is so thin that a depletion layer spreads over a wide range of the drift region 14 from the interface between the body region 12 and the drift region 14 when no voltage is applied to the gate electrode 26. The impurity concentration of the drain region 16 is high enough to make ohmic contact with the back electrode (drain electrode) 18.

  With the semiconductor structure described above, when a positive voltage is applied to the gate electrode 26, the body region 12 in a range facing the side surface of the gate electrode 26 through the gate insulating film 24 is inverted to n-type, and the surface The resistance between the electrode (source electrode) 10 and the back electrode (drain electrode) 18 decreases. In a state where no positive voltage is applied to the gate electrode 26, a depletion layer extends from the interface between the body region 12 and the drift region 14 to a wide range of the body region 12 and the drift region 14, and a high breakdown voltage can be obtained.

A peripheral breakdown voltage structure is formed on the outer peripheral side of the semiconductor substrate 9 with respect to the outermost peripheral trench. In the present specification, a range on the inner side of the outermost trench is referred to as an element region 4, a range on the outer peripheral side is referred to as a peripheral region 6, and a boundary thereof is indicated by a reference sign B.
In the peripheral region 6, the RESURF layer 32, the guard ring group 30, and the floating layer 40 are formed. For convenience of illustration, reference numeral 30 is given only to some guard rings. The RESURF layer 32 is p-type and has a lower impurity concentration than the guard ring group 30. The RESURF layer 32 is an example of the second conductivity type impurity low concentration region. The impurity concentration of the RESURF layer 32 may be uniform, but may gradually decrease as the outer periphery 8 of the semiconductor substrate is approached. Each guard ring 30 is also p-type, and is an embodiment of the second conductivity type impurity high-concentration ring-shaped region. A plurality of guard rings are formed. A plurality of guard rings 30 surround the element region 4 in multiple layers. The outermost guard ring 30 b is formed outside the RESURF layer 32. There may be no guard ring formed outside the RESURF layer 32, or one or more guard rings may be formed. In peripheral region 6, p-type layer 40 is formed at an intermediate depth of n-type drift region 14. The p-type layer 40 is surrounded by the n-type drift region 14 and is in a floating state. The p-type layer 40 is an example of a second conductivity type floating region. The p-type layer 40 is continuously formed from the boundary position B between the element region 4 and the peripheral region 6 to the existing position D2 of the outermost guard ring 30b. In the peripheral region 6, the surface of the semiconductor substrate 9 is covered with an insulating film 28. An n-type impurity high concentration region 36 is formed on the surface side of the semiconductor substrate 0 at a position in contact with the outer periphery 8.
The p-type region, for example, the body contact region 22, the body region 12, the RESURF layer 32, the guard ring group 30, and the floating layer 40 can be formed by implanting phosphorus. It can also be formed by implanting boron.

When the RESURF layer 32, the guard ring group 30, and the floating layer 40 are formed in the peripheral region 6, the breakdown voltage in the peripheral region 6 is improved. In the case of this example, the breakdown voltage of the peripheral region 6 when the RESURF layer 32 and the guard ring group 30 were formed and the floating layer 40 was not formed was 1050 volts. On the other hand, the breakdown voltage of the peripheral region 6 when the RESURF layer 32, the guard ring group 30, and the floating layer 40 are all formed is 1470 volts. By adding the floating layer 40, the breakdown voltage increased by 420 volts.
As will be described in detail later, when the floating layer 40 continuously extends from the position inside the position C where the innermost guard ring 30a exists toward the outer periphery 8 of the semiconductor substrate 9, the breakdown voltage is improved by the floating layer 40. The effect is remarkably obtained. In the first embodiment, the inner circumferential side position E of the floating layer 40 is on the inner side of the position C where the innermost guard ring 30a is present, and satisfies the above conditions.
In addition, when the floating layer 40 continuously extends to the outer peripheral side position D of the peripheral withstand voltage structure, the withstand voltage improvement effect by the floating layer 40 is remarkably obtained. The outer peripheral side position D of the peripheral withstand voltage structure refers to the outer peripheral side position of the region where both the RESURF layer 32 and the guard ring group 30 are formed. As shown in FIG. 1, when the position D2 of the outermost peripheral guard ring 30b is outside the outer peripheral side position D1 of the RESURF layer 32, the outer peripheral side position D1 of the RESURF layer 32 becomes the outer peripheral side position D of the peripheral pressure-resistant structure. . As shown in FIG. 3, when the position D2 of the outermost peripheral guard ring 30b is inside the outer peripheral side position D1 of the RESURF layer 32, the position D2 of the outermost peripheral guard ring 30b becomes the outer peripheral side position D of the peripheral pressure-resistant structure. . In the first embodiment, the outer peripheral side position F of the floating layer 40 extends to the outer side of the outer peripheral side position D of the peripheral withstand voltage structure, and satisfies the above conditions.
When the floating layer 40 continuously extends between the position C where the innermost guard ring 30a is present and the outer peripheral side position D of the peripheral pressure-resistant structure, the effect of improving the breakdown voltage by the floating layer 40 is significantly obtained.

(Second embodiment)
Hereinafter, the second and subsequent embodiments will be described with reference to FIG. About the same part as 1st Example, duplication description is abbreviate | omitted by using the same reference number. Since the floating layer is different for each embodiment, the numbers 40, 50, 60, 70, 80, and 90 are used.
The formation range of the floating layer 50 is not limited to the position from B to D2 shown in FIG. In the second embodiment shown in FIG. 2, the innermost position E of the floating layer 50 is outside the boundary B between the element region 4 and the peripheral region 6. Even if the inner circumferential position E is outside the boundary B, the floating layer 50 can improve the breakdown voltage of the peripheral region 6 if the inner circumferential position E is inside the innermost guard ring 30a formation position C. can get. Further, it is preferable that the outer peripheral side position F of the floating layer 50 extends to the outer side from the outer peripheral side position D of the peripheral withstand voltage structure formed in the range facing the surface of the semiconductor substrate 9. In the case of FIG. 2, the outermost peripheral guard ring 30 b is formed outside the RESURF layer 32, and the outer peripheral side position D of the peripheral breakdown voltage structure is the outer peripheral side position D1 of the RESURF layer 32. As shown in FIG. 3, when the guard ring is not formed outside the RESURF layer 32, the outer peripheral side position D of the peripheral withstand voltage structure is the position D2 of the outermost peripheral guard ring 30b.

The vertical axis in FIG. 7 indicates the breakdown voltage of the peripheral region, and the level 90 indicates the breakdown voltage when the RESURF layer 32 and the guard ring group 30 are formed and the floating layer is not formed. The abscissa in FIG. 7 shows the positional relationship between the outer peripheral side position F of the floating layer and the outer peripheral side position D of the peripheral withstand voltage structure formed in the range facing the surface of the semiconductor substrate. The case where the position F is outside the position D is positive. As shown in FIG. 7, the breakdown voltage is improved by adding the floating layer, but the breakdown voltage improvement effect varies depending on the outer peripheral side position F where the floating layer extends, and the breakdown voltage increases as the position F is located outside the position D. It can be seen that the improvement effect increases.
In FIG. 7, the zero point indicates the inner side of the positions D1 and D2. The position of 5 μm indicates the outer side of the positions D1 and D2. The floating layer extends to a position D where both the RESURF layer 32 and the guard ring group 30 are formed, and preferably, the position where either the RESURF layer 32 and the guard ring group 30 are formed (of D1 and D2) It is preferable that it extends to the outer side.
On the other hand, the inner peripheral side position E of the floating layer has a small influence on the breakdown voltage improvement effect, and as shown in FIG. 2, the innermost peripheral guard ring 30a is formed even if it is outside the boundary B. If it is on the inner side than C, the required withstand voltage improvement effect can be obtained. In the guard ring group 30, potentials are sequentially shared from the innermost guard ring 30 a toward the outer guard ring. When the floating layer is formed continuously from the position inside the formation position C of the innermost guard ring 30a toward the outside, the potential can be efficiently shared by the floating layer.

(Third embodiment)
As shown in FIG. 3, the innermost position E of the floating layer 60 may be inside the boundary B. That is, the floating layer 60 may enter the element region 4. Also in this case, the effect of improving the breakdown voltage due to the floating layer 60 can be obtained. If the floating layer 60 penetrates into the element region 4, the on-resistance of the element region may increase. However, if the penetration distance is small, the influence on the on-resistance can be ignored. In FIG. 3, symbol A indicates the formation position of the second gate electrode inward from the outermost peripheral gate electrode. If the inner peripheral position E of the floating layer 60 is between A and C (within the connecting region Z), it is possible to improve the breakdown voltage in the peripheral region while preventing the on-resistance of the element region from increasing. it can.

(Fourth embodiment)
As shown in FIG. 4, openings 70 a to 70 d may be formed in the inner portion of the floating layer 70. The openings 70 a to 70 d may go around the element region 4 or may extend in parallel with the gate electrode 26. If the inner peripheral side position E of the floating layer 70 is outside the position A, it is possible to prevent the ON resistance of the element region from increasing. If the floating layer 70 is continuous outside the C position (that is, if no opening is formed outside the C position), the floating layer 70 can improve the breakdown voltage in the peripheral region. When the openings 70 a to 70 d are formed, the inner peripheral side position E of the floating layer 70 can be deeply penetrated into the element region 4. That is, it can be brought close to the A position.

(5th Example)
1 to 4, the floating layer is formed as a single layer, but a plurality of floating layers 80a and 80b may be formed as shown in FIG. That is, the floating layer may be formed at a plurality of intermediate depths of the drift layer 14. In the case of FIG. 5, each floating layer extends continuously from at least position C to position D. Instead, it may be configured to continuously extend from position C to position D when the formation ranges of the individual floating layers are overlapped.

(Sixth embodiment)
FIG. 6 shows a MOS that uses the planar gate electrode 26. The same reference numerals are assigned to the same or equivalent members as in the trench gate type MOS shown in FIGS. Even in the case of a vertical semiconductor device that uses the planar gate electrode 26, it extends from the position inside the innermost peripheral guard ring 30a formation position C to the outer peripheral position D of the peripheral counter pressure structure or extends to the outside. By forming the floating region 90, the breakdown voltage of the peripheral region can be improved.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, the first conductivity type may be p-type and the second conductivity type may be n-type. Further, it can be applied to IGBT instead of MOS.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Vertical semiconductor device operating as MOS 4: Element region 6: Peripheral region 8: Perimeter of semiconductor substrate 9: Semiconductor substrate 10: Surface electrode (source electrode)
12: Second conductivity type region (p-type body region)
14: Back side first conductivity type region (n-type drift region)
16: First conductivity type region (n-type drain region)
18: Back electrode (drain electrode)
20: Surface side first conductivity type region (n-type source region)
22: body contact region 24: gate insulating film 26: gate electrode 30: second conductivity type impurity high concentration ring-shaped region (guard ring)
32: Second conductivity type impurity low concentration region (Resurf layer)
36: First conductivity type region 40, 50, 60, 70, 80, 90: Second conductivity type floating region (p-type floating layer)
A: formation position of the second gate electrode inside the outermost peripheral gate electrode B: boundary between the element region and the peripheral region: formation position of the outermost peripheral gate electrode C: formation position of the innermost guard ring D1: outer periphery of the RESURF layer Side position D2: formation position of outermost peripheral guard ring D: outer peripheral side position of peripheral pressure-resistant structure (inside position of D1 and D2)
E: Inner side position of floating region F: Outer side position of floating region

Claims (5)

  1. When the semiconductor substrate is viewed in plan, it has a peripheral region that goes around the device region and the device region,
    In the element region, a front surface electrode formed on the front surface of the semiconductor substrate, a back surface electrode formed on the back surface of the semiconductor substrate, a front side first conductivity type region electrically connected to the front surface electrode, and the back surface electrode A backside first conductivity type region that is electrically connected to the surface, a second conductivity type region that separates the front side first conductivity type region and the back side first conductivity type region, and the front side first conductivity type. A gate electrode is formed opposite to the second conductivity type region in a range separating the region and the back side first conductivity type region through a gate insulating film; The resistance between the electrode and the back electrode changes,
    In the peripheral region, a first conductivity type impurity high concentration region formed at a position facing both the surface and the outer periphery of the semiconductor substrate, and extending from a position in contact with the element region toward the first conductivity type impurity high concentration region. A second conductivity type impurity low concentration region formed at a position facing the surface of the semiconductor substrate in a range not reaching the first conductivity type impurity high concentration region, and an element region in the range facing the surface of the semiconductor substrate. A second structure of the second conductivity type impurity high-concentration ring-shaped region in a circuit and a second conductivity type floating region formed at an intermediate depth of the first conductivity type region on the back surface side;
    At least a part of the multiple structure of the second conductivity type impurity high-concentration ring-shaped region is formed in a range included in the second conductivity type impurity low-concentration region;
    The second conductivity type floating region, from the inside of the position from the innermost circumference of the second conductivity type high impurity concentration ring area, towards the periphery of the semiconductor substrate, the said second conductivity type impurity low concentration region first to the outside from the outer peripheral side position of the region where both the multiple structure of the second conductivity type high impurity concentration ring region is located, both the extend continuously, the back surface side of the first conductivity type high impurity concentration regions A vertical semiconductor device characterized by not reaching the above .
  2.   The semiconductor substrate is made of SiC, the front side first conductivity type region is a source region, the second conductivity type region is a body region, and the back side first conductivity type region is a drift region. 2. The vertical semiconductor device according to claim 1, wherein a drain region of the first conductivity type is formed between the back side first conductivity type region and the back electrode.
  3. The second conductivity type floating region extends outside a position on the outer peripheral side of a region where at least one of the multiple structure of the second conductivity type impurity low concentration region and the second conductivity type impurity high concentration ring-shaped region is disposed. The vertical semiconductor device according to claim 1, wherein the vertical semiconductor device extends.
  4.   When the depth on the front surface side of the back surface side first conductivity type region is H1, and the depth on the back surface side of the back surface side first conductivity type region is H2, the second conductivity type floating region is H1 + 0. 4. The vertical semiconductor device according to claim 1, wherein the vertical semiconductor device is formed on a surface side from a depth of 8 × (H 2 −H 1). 5.
  5. Each of the plurality of intermediate depth before Symbol rear surface-side first conductive type region, according to any one of claims 1 to 4, characterized in that said second conductivity type floating region is formed Vertical semiconductor device.
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